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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Fea.Wang" <fea.wang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 34/39] target/riscv: Check svukte is not enabled in RV32
Date: Thu, 19 Dec 2024 08:30:04 +1000
Message-ID: <20241218223010.1931245-35-alistair.francis@wdc.com>
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From: "Fea.Wang" <fea.wang@sifive.com>
The spec explicitly says svukte doesn't support RV32. So check that it
is not enabled in RV32.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-7-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c221696..3b99c8c9e3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, =
Error **errp)
return;
}
=20
+ if (mcc->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) {
+ error_setg(errp, "svukte is not supported for RV32");
+ return;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
--=20
2.47.1