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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anton Blanchard <antonb@tenstorrent.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 10/39] target/riscv: Add Tenstorrent Ascalon CPU
Date: Thu, 19 Dec 2024 08:29:40 +1000
Message-ID: <20241218223010.1931245-11-alistair.francis@wdc.com>
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From: Anton Blanchard <antonb@tenstorrent.com>
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241113110459.1607299-1-antonb@tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 62115375cd..6547642287 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -49,6 +49,7 @@
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
+#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
=20
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4329015076..66e00ed260 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -579,6 +579,72 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
=20
+/* Tenstorrent Ascalon */
+static void rv64_tt_ascalon_cpu_init(Object *obj)
+{
+ CPURISCVState *env =3D &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu =3D RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
+ env->priv_ver =3D PRIV_VERSION_1_13_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu =3D true;
+ cpu->cfg.vlenb =3D 256 >> 3;
+ cpu->cfg.elen =3D 64;
+ cpu->env.vext_ver =3D VEXT_VERSION_1_00_0;
+ cpu->cfg.rvv_ma_all_1s =3D true;
+ cpu->cfg.rvv_ta_all_1s =3D true;
+ cpu->cfg.misa_w =3D true;
+ cpu->cfg.pmp =3D true;
+ cpu->cfg.cbom_blocksize =3D 64;
+ cpu->cfg.cbop_blocksize =3D 64;
+ cpu->cfg.cboz_blocksize =3D 64;
+ cpu->cfg.ext_zic64b =3D true;
+ cpu->cfg.ext_zicbom =3D true;
+ cpu->cfg.ext_zicbop =3D true;
+ cpu->cfg.ext_zicboz =3D true;
+ cpu->cfg.ext_zicntr =3D true;
+ cpu->cfg.ext_zicond =3D true;
+ cpu->cfg.ext_zicsr =3D true;
+ cpu->cfg.ext_zifencei =3D true;
+ cpu->cfg.ext_zihintntl =3D true;
+ cpu->cfg.ext_zihintpause =3D true;
+ cpu->cfg.ext_zihpm =3D true;
+ cpu->cfg.ext_zimop =3D true;
+ cpu->cfg.ext_zawrs =3D true;
+ cpu->cfg.ext_zfa =3D true;
+ cpu->cfg.ext_zfbfmin =3D true;
+ cpu->cfg.ext_zfh =3D true;
+ cpu->cfg.ext_zfhmin =3D true;
+ cpu->cfg.ext_zcb =3D true;
+ cpu->cfg.ext_zcmop =3D true;
+ cpu->cfg.ext_zba =3D true;
+ cpu->cfg.ext_zbb =3D true;
+ cpu->cfg.ext_zbs =3D true;
+ cpu->cfg.ext_zkt =3D true;
+ cpu->cfg.ext_zvbb =3D true;
+ cpu->cfg.ext_zvbc =3D true;
+ cpu->cfg.ext_zvfbfmin =3D true;
+ cpu->cfg.ext_zvfbfwma =3D true;
+ cpu->cfg.ext_zvfh =3D true;
+ cpu->cfg.ext_zvfhmin =3D true;
+ cpu->cfg.ext_zvkng =3D true;
+ cpu->cfg.ext_smaia =3D true;
+ cpu->cfg.ext_smstateen =3D true;
+ cpu->cfg.ext_ssaia =3D true;
+ cpu->cfg.ext_sscofpmf =3D true;
+ cpu->cfg.ext_sstc =3D true;
+ cpu->cfg.ext_svade =3D true;
+ cpu->cfg.ext_svinval =3D true;
+ cpu->cfg.ext_svnapot =3D true;
+ cpu->cfg.ext_svpbmt =3D true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -2984,6 +3050,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_=
cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_=
cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90=
6_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo=
n_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1=
_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu=
_init),
--=20
2.47.1