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Wed, 18 Dec 2024 14:30:43 -0800 (PST) From: Alistair Francis <alistair23@gmail.com> X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 09/39] docs/specs: add riscv-iommu-sys information Date: Thu, 19 Dec 2024 08:29:39 +1000 Message-ID: <20241218223010.1931245-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241218223010.1931245-1-alistair.francis@wdc.com> References: <20241218223010.1931245-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1734561503875116600 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++--- docs/system/riscv/virt.rst | 10 ++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 463f4cffb6..b1538c9ead 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec version 1.0 `iommu1.0`_. =20 -The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU -RISC-V boards can use. The 'virt' RISC-V machine is compatible with this -device. +The emulation includes a PCI reference device (riscv-iommu-pci) and a plat= form +bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' +RISC-V machine is compatible with both devices. =20 riscv-iommu-pci reference device -------------------------------- @@ -83,6 +83,30 @@ Several options are available to control the capabilitie= s of the device, namely: - "s-stage": enable s-stage support - "g-stage": enable g-stage support =20 +riscv-iommu-sys device +---------------------- + +This device implements the RISC-V IOMMU emulation as a platform bus device= that +RISC-V boards can use. + +For the 'virt' board the device is disabled by default. To enable it use = the +'iommu-sys' machine option: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + +There is no options to configure the capabilities of this device in the 'v= irt' +board using the QEMU command line. The device is configured with the foll= owing +riscv-iommu options: + +- "ioatc-limit": default value (2Mb) +- "intremap": enabled +- "ats": enabled +- "off": on (DMA disabled) +- "s-stage": enabled +- "g-stage": enabled + .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo= ad/v1.0/riscv-iommu.pdf =20 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje= znach@rivosinc.com/ diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 8e9a2e4dda..537aac0340 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -94,6 +94,12 @@ command line: =20 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) =20 +It also has support for the riscv-iommu-sys platform device: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...) + Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU s= upport works. =20 @@ -129,6 +135,10 @@ The following machine-specific options are supported: having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified, the default number of per-HART VS-level AIA IMSIC pages is 0. =20 +- iommu-sys=3D[on|off] + + Enables the riscv-iommu-sys platform device. Defaults to 'off'. + Running Linux kernel -------------------- =20 --=20 2.47.1