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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
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Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 01/39] hw/riscv/riscv-iommu.c: Correct the validness check of
iova
Date: Thu, 19 Dec 2024 08:29:31 +1000
Message-ID: <20241218223010.1931245-2-alistair.francis@wdc.com>
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From: Jason Chien <jason.chien@sifive.com>
From RISCV IOMMU spec section 2.1.3:
When SXL is 1, the following rules apply:
- If the first-stage is not Bare, then a page fault corresponding to the
original access type occurs if the IOVA has bits beyond bit 31 set to 1.
- If the second-stage is not Bare, then a guest page fault corresponding
to the original access type occurs if the incoming GPA has bits beyond bit
33 set to 1.
From RISCV IOMMU spec section 2.3 step 17:
Use the process specified in Section "Two-Stage Address Translation" of
the RISC-V Privileged specification to determine the GPA accessed by the
transaction.
From RISCV IOMMU spec section 2.3 step 19:
Use the second-stage address translation process specified in Section
"Two-Stage Address Translation" of the RISC-V Privileged specification
to translate the GPA A to determine the SPA accessed by the transaction.
This commit adds the iova check with the following rules:
- For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero
extended.
- For Sv39, Sv48 and Sv57, the iova must be signed extended with most
significant bit.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241114065617.25133-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/riscv-iommu.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 07fed36986..b6b9477129 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -392,9 +392,26 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R=
ISCVIOMMUContext *ctx,
=20
/* Address range check before first level lookup */
if (!sc[pass].step) {
- const uint64_t va_mask =3D (1ULL << (va_skip + va_bits)) - 1;
- if ((addr & va_mask) !=3D addr) {
- return RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED;
+ const uint64_t va_len =3D va_skip + va_bits;
+ const uint64_t va_mask =3D (1ULL << va_len) - 1;
+
+ if (pass =3D=3D S_STAGE && va_len > 32) {
+ target_ulong mask, masked_msbs;
+
+ mask =3D (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+ masked_msbs =3D (addr >> (va_len - 1)) & mask;
+
+ if (masked_msbs !=3D 0 && masked_msbs !=3D mask) {
+ return (iotlb->perm & IOMMU_WO) ?
+ RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S :
+ RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S;
+ }
+ } else {
+ if ((addr & va_mask) !=3D addr) {
+ return (iotlb->perm & IOMMU_WO) ?
+ RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS :
+ RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS;
+ }
}
}
=20
--=20
2.47.1
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum
write emulation
Date: Thu, 19 Dec 2024 08:29:32 +1000
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From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM =3D 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."
Update the riscv_aplic_set_pending() to match the spec.
Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation fo=
r APLIC MSI-mode")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241029085349.30412-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 353eec8136..3edab64b97 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -248,9 +248,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState *a=
plic,
=20
if ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
(sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW)) {
- if (!aplic->msimode || (aplic->msimode && !pending)) {
+ if (!aplic->msimode) {
return;
}
+ if (aplic->msimode && !pending) {
+ goto noskip_write_pending;
+ }
if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
(sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW)) {
return;
@@ -261,6 +264,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState *ap=
lic,
}
}
=20
+noskip_write_pending:
riscv_aplic_set_pending_raw(aplic, irq, pending);
}
=20
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
Date: Thu, 19 Dec 2024 08:29:33 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.
With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra caps.
This will allow callers to add IOMMU capabilities before the
realization.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/riscv-iommu.c | 71 +++++++++++++++++++++++-------------------
1 file changed, 39 insertions(+), 32 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index b6b9477129..c461ebbd87 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2130,11 +2130,48 @@ static const MemoryRegionOps riscv_iommu_trap_ops =
=3D {
}
};
=20
+static void riscv_iommu_instance_init(Object *obj)
+{
+ RISCVIOMMUState *s =3D RISCV_IOMMU(obj);
+
+ /* Enable translation debug interface */
+ s->cap =3D RISCV_IOMMU_CAP_DBG;
+
+ /* Report QEMU target physical address space limits */
+ s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS,
+ TARGET_PHYS_ADDR_SPACE_BITS);
+
+ /* TODO: method to report supported PID bits */
+ s->pid_bits =3D 8; /* restricted to size of MemTxAttrs.pid */
+ s->cap |=3D RISCV_IOMMU_CAP_PD8;
+
+ /* register storage */
+ s->regs_rw =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+ s->regs_ro =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+ s->regs_wc =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+
+ /* Mark all registers read-only */
+ memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
+
+ /* Device translation context cache */
+ s->ctx_cache =3D g_hash_table_new_full(riscv_iommu_ctx_hash,
+ riscv_iommu_ctx_equal,
+ g_free, NULL);
+
+ s->iot_cache =3D g_hash_table_new_full(riscv_iommu_iot_hash,
+ riscv_iommu_iot_equal,
+ g_free, NULL);
+
+ s->iommus.le_next =3D NULL;
+ s->iommus.le_prev =3D NULL;
+ QLIST_INIT(&s->spaces);
+}
+
static void riscv_iommu_realize(DeviceState *dev, Error **errp)
{
RISCVIOMMUState *s =3D RISCV_IOMMU(dev);
=20
- s->cap =3D s->version & RISCV_IOMMU_CAP_VERSION;
+ s->cap |=3D s->version & RISCV_IOMMU_CAP_VERSION;
if (s->enable_msi) {
s->cap |=3D RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;
}
@@ -2149,29 +2186,11 @@ static void riscv_iommu_realize(DeviceState *dev, E=
rror **errp)
s->cap |=3D RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
}
- /* Enable translation debug interface */
- s->cap |=3D RISCV_IOMMU_CAP_DBG;
-
- /* Report QEMU target physical address space limits */
- s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS,
- TARGET_PHYS_ADDR_SPACE_BITS);
-
- /* TODO: method to report supported PID bits */
- s->pid_bits =3D 8; /* restricted to size of MemTxAttrs.pid */
- s->cap |=3D RISCV_IOMMU_CAP_PD8;
=20
/* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough=
) */
s->ddtp =3D set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_=
BARE);
=20
- /* register storage */
- s->regs_rw =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
- s->regs_ro =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
- s->regs_wc =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
-
- /* Mark all registers read-only */
- memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
-
/*
* Register complete MMIO space, including MSI/PBA registers.
* Note, PCIDevice implementation will add overlapping MR for MSI/PBA,
@@ -2229,19 +2248,6 @@ static void riscv_iommu_realize(DeviceState *dev, Er=
ror **errp)
memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops,=
s,
"riscv-iommu-trap", ~0ULL);
address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
-
- /* Device translation context cache */
- s->ctx_cache =3D g_hash_table_new_full(riscv_iommu_ctx_hash,
- riscv_iommu_ctx_equal,
- g_free, NULL);
-
- s->iot_cache =3D g_hash_table_new_full(riscv_iommu_iot_hash,
- riscv_iommu_iot_equal,
- g_free, NULL);
-
- s->iommus.le_next =3D NULL;
- s->iommus.le_prev =3D NULL;
- QLIST_INIT(&s->spaces);
}
=20
static void riscv_iommu_unrealize(DeviceState *dev)
@@ -2283,6 +2289,7 @@ static const TypeInfo riscv_iommu_info =3D {
.name =3D TYPE_RISCV_IOMMU,
.parent =3D TYPE_DEVICE,
.instance_size =3D sizeof(RISCVIOMMUState),
+ .instance_init =3D riscv_iommu_instance_init,
.class_init =3D riscv_iommu_class_init,
};
=20
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS
Date: Thu, 19 Dec 2024 08:29:34 +1000
Message-ID: <20241218223010.1931245-5-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Interrupt Generation Support (IGS) is a capability that is tied to the
interrupt deliver mechanism, not with the core IOMMU emulation. We
should allow device implementations to set IGS as they wish.
A new helper is added to make it easier for device impls to set IGS. Use
it in our existing IOMMU device (riscv-iommu-pci) to set
RISCV_IOMMU_CAPS_IGS_MSI.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/riscv-iommu-bits.h | 6 ++++++
hw/riscv/riscv-iommu.h | 4 ++++
hw/riscv/riscv-iommu-pci.c | 1 +
hw/riscv/riscv-iommu.c | 5 +++++
4 files changed, 16 insertions(+)
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
index 6359ae0353..485f36b9c9 100644
--- a/hw/riscv/riscv-iommu-bits.h
+++ b/hw/riscv/riscv-iommu-bits.h
@@ -88,6 +88,12 @@ struct riscv_iommu_pq_record {
#define RISCV_IOMMU_CAP_PD17 BIT_ULL(39)
#define RISCV_IOMMU_CAP_PD20 BIT_ULL(40)
=20
+enum riscv_iommu_igs_modes {
+ RISCV_IOMMU_CAP_IGS_MSI =3D 0,
+ RISCV_IOMMU_CAP_IGS_WSI,
+ RISCV_IOMMU_CAP_IGS_BOTH
+};
+
/* 5.4 Features control register (32bits) */
#define RISCV_IOMMU_REG_FCTL 0x0008
#define RISCV_IOMMU_FCTL_BE BIT(0)
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
index da3f03440c..f9f2827808 100644
--- a/hw/riscv/riscv-iommu.h
+++ b/hw/riscv/riscv-iommu.h
@@ -21,6 +21,9 @@
=20
#include "qom/object.h"
#include "hw/riscv/iommu.h"
+#include "hw/riscv/riscv-iommu-bits.h"
+
+typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode;
=20
struct RISCVIOMMUState {
/*< private >*/
@@ -85,6 +88,7 @@ struct RISCVIOMMUState {
=20
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
Error **errp);
+void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode=
);
=20
/* private helpers */
=20
diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index a695314bbe..a95d0f74c8 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -155,6 +155,7 @@ static void riscv_iommu_pci_init(Object *obj)
qdev_alias_all_properties(DEVICE(iommu), obj);
=20
iommu->icvec_avail_vectors =3D RISCV_IOMMU_PCI_ICVEC_VECTORS;
+ riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
}
=20
static const Property riscv_iommu_pci_properties[] =3D {
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index c461ebbd87..24b879822b 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2130,6 +2130,11 @@ static const MemoryRegionOps riscv_iommu_trap_ops =
=3D {
}
};
=20
+void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode)
+{
+ s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode);
+}
+
static void riscv_iommu_instance_init(Object *obj)
{
RISCVIOMMUState *s =3D RISCV_IOMMU(obj);
--=20
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Subject: [PULL 05/39] hw/riscv: add riscv-iommu-sys platform device
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From: Tomasz Jeznach <tjeznach@rivosinc.com>
This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.
The WSIs are emitted using the input of the s->notify() callback as a
index to an IRQ list. The IRQ list starts at 'base_irq' and goes until
base_irq + 3. This means that boards must have 4 contiguous IRQ lines
available, starting from 'base_irq'.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/iommu.h | 4 ++
hw/riscv/riscv-iommu-sys.c | 128 +++++++++++++++++++++++++++++++++++++
hw/riscv/riscv-iommu.c | 3 +-
hw/riscv/meson.build | 2 +-
4 files changed, 134 insertions(+), 3 deletions(-)
create mode 100644 hw/riscv/riscv-iommu-sys.c
diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index 80769a1400..fc20808553 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -33,4 +33,8 @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
=20
+#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
+typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
+
#endif
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
new file mode 100644
index 0000000000..4b82046ce9
--- /dev/null
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -0,0 +1,128 @@
+/*
+ * QEMU emulation of an RISC-V IOMMU Platform Device
+ *
+ * Copyright (C) 2022-2023 Rivos Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/host-utils.h"
+#include "qemu/module.h"
+#include "qom/object.h"
+
+#include "riscv-iommu.h"
+
+#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
+
+/* RISC-V IOMMU System Platform Device Emulation */
+
+struct RISCVIOMMUStateSys {
+ SysBusDevice parent;
+ uint64_t addr;
+ uint32_t base_irq;
+ DeviceState *irqchip;
+ RISCVIOMMUState iommu;
+ qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
+};
+
+static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
+ unsigned vector)
+{
+ RISCVIOMMUStateSys *s =3D container_of(iommu, RISCVIOMMUStateSys, iomm=
u);
+ uint32_t fctl =3D riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
+
+ /* We do not support MSIs yet */
+ if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
+ return;
+ }
+
+ qemu_irq_pulse(s->irqs[vector]);
+}
+
+static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
+{
+ RISCVIOMMUStateSys *s =3D RISCV_IOMMU_SYS(dev);
+ SysBusDevice *sysdev =3D SYS_BUS_DEVICE(s);
+ PCIBus *pci_bus;
+ qemu_irq irq;
+
+ qdev_realize(DEVICE(&s->iommu), NULL, errp);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
+ if (s->addr) {
+ sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
+ }
+
+ pci_bus =3D (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL=
);
+ if (pci_bus) {
+ riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
+ }
+
+ s->iommu.notify =3D riscv_iommu_sysdev_notify;
+
+ /* 4 IRQs are defined starting from s->base_irq */
+ for (int i =3D 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
+ sysbus_init_irq(sysdev, &s->irqs[i]);
+ irq =3D qdev_get_gpio_in(s->irqchip, s->base_irq + i);
+ sysbus_connect_irq(sysdev, i, irq);
+ }
+}
+
+static void riscv_iommu_sys_init(Object *obj)
+{
+ RISCVIOMMUStateSys *s =3D RISCV_IOMMU_SYS(obj);
+ RISCVIOMMUState *iommu =3D &s->iommu;
+
+ object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
+ qdev_alias_all_properties(DEVICE(iommu), obj);
+
+ iommu->icvec_avail_vectors =3D RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
+ riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
+}
+
+static Property riscv_iommu_sys_properties[] =3D {
+ DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
+ DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
+ DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
+ TYPE_DEVICE, DeviceState *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ dc->realize =3D riscv_iommu_sys_realize;
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ device_class_set_props(dc, riscv_iommu_sys_properties);
+}
+
+static const TypeInfo riscv_iommu_sys =3D {
+ .name =3D TYPE_RISCV_IOMMU_SYS,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .class_init =3D riscv_iommu_sys_class_init,
+ .instance_init =3D riscv_iommu_sys_init,
+ .instance_size =3D sizeof(RISCVIOMMUStateSys),
+};
+
+static void riscv_iommu_register_sys(void)
+{
+ type_register_static(&riscv_iommu_sys);
+}
+
+type_init(riscv_iommu_register_sys)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 24b879822b..9137217cb7 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -94,10 +94,9 @@ static uint8_t riscv_iommu_get_icvec_vector(uint32_t icv=
ec, uint32_t vec_type)
=20
static void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type)
{
- const uint32_t fctl =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FCTL);
uint32_t ipsr, icvec, vector;
=20
- if (fctl & RISCV_IOMMU_FCTL_WSI || !s->notify) {
+ if (!s->notify) {
return;
}
=20
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index adbef8a9b2..3be13d7774 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -10,6 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sif=
ive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs=
oc.c'))
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', '=
riscv-iommu-pci.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', '=
riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
=20
hw_arch +=3D {'riscv': riscv_ss}
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Sunil V L <sunilvl@ventanamicro.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 06/39] hw/riscv/virt: Add IOMMU as platform device if the
option is set
Date: Thu, 19 Dec 2024 08:29:36 +1000
Message-ID: <20241218223010.1931245-7-alistair.francis@wdc.com>
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From: Sunil V L <sunilvl@ventanamicro.com>
Add a new machine option called 'iommu-sys' that enables a
riscv-iommu-sys platform device for the 'virt' machine. The option is
default 'off'.
The device will use IRQs 36 to 39.
We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
the same board in this first implementation. If a riscv-iommu-pci device
is added in the command line we will disable the riscv-iommu-sys device.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/iommu.h | 2 +
include/hw/riscv/virt.h | 6 ++-
hw/riscv/virt.c | 104 ++++++++++++++++++++++++++++++++++++++-
3 files changed, 109 insertions(+), 3 deletions(-)
diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index fc20808553..8a8acfc3f0 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -37,4 +37,6 @@ typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
=20
+#define FDT_IRQ_TYPE_EDGE_LOW 1
+
#endif
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index c0dc41ff9a..48a14bea2e 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -62,6 +62,7 @@ struct RISCVVirtState {
OnOffAuto acpi;
const MemMapEntry *memmap;
struct GPEXHost *gpex_host;
+ OnOffAuto iommu_sys;
};
=20
enum {
@@ -84,7 +85,8 @@ enum {
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
VIRT_PLATFORM_BUS,
- VIRT_PCIE_ECAM
+ VIRT_PCIE_ECAM,
+ VIRT_IOMMU_SYS,
};
=20
enum {
@@ -93,6 +95,7 @@ enum {
VIRTIO_IRQ =3D 1, /* 1 to 8 */
VIRTIO_COUNT =3D 8,
PCIE_IRQ =3D 0x20, /* 32 to 35 */
+ IOMMU_SYS_IRQ =3D 0x24, /* 36-39 */
VIRT_PLATFORM_BUS_IRQ =3D 64, /* 64 to 95 */
};
=20
@@ -129,6 +132,7 @@ enum {
1 + FDT_APLIC_INT_CELLS)
=20
bool virt_is_acpi_enabled(RISCVVirtState *s);
+bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
uint32_t imsic_num_bits(uint32_t count);
=20
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2feb851f15..c5ada635f1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -33,6 +33,7 @@
#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/iommu.h"
+#include "hw/riscv/riscv-iommu-bits.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
@@ -76,6 +77,7 @@ static const MemMapEntry virt_memmap[] =3D {
[VIRT_CLINT] =3D { 0x2000000, 0x10000 },
[VIRT_ACLINT_SSWI] =3D { 0x2F00000, 0x4000 },
[VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 },
+ [VIRT_IOMMU_SYS] =3D { 0x3010000, 0x1000 },
[VIRT_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 },
[VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2=
) },
[VIRT_APLIC_M] =3D { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
@@ -853,7 +855,8 @@ static void create_fdt_virtio(RISCVVirtState *s, const =
MemMapEntry *memmap,
=20
static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
uint32_t irq_pcie_phandle,
- uint32_t msi_pcie_phandle)
+ uint32_t msi_pcie_phandle,
+ uint32_t iommu_sys_phandle)
{
g_autofree char *name =3D NULL;
MachineState *ms =3D MACHINE(s);
@@ -887,6 +890,12 @@ static void create_fdt_pcie(RISCVVirtState *s, const M=
emMapEntry *memmap,
2, virt_high_pcie_memmap.base,
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
=20
+ if (virt_is_iommu_sys_enabled(s)) {
+ qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map",
+ 0, iommu_sys_phandle, 0, 0, 0,
+ iommu_sys_phandle, 0, 0xffff);
+ }
+
create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
}
=20
@@ -1033,6 +1042,44 @@ static void create_fdt_virtio_iommu(RISCVVirtState *=
s, uint16_t bdf)
bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
}
=20
+static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
+ uint32_t *iommu_sys_phandle)
+{
+ const char comp[] =3D "riscv,iommu";
+ void *fdt =3D MACHINE(s)->fdt;
+ uint32_t iommu_phandle;
+ g_autofree char *iommu_node =3D NULL;
+ hwaddr addr =3D s->memmap[VIRT_IOMMU_SYS].base;
+ hwaddr size =3D s->memmap[VIRT_IOMMU_SYS].size;
+ uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] =3D {
+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
+ IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
+ };
+
+ iommu_node =3D g_strdup_printf("/soc/iommu@%x",
+ (unsigned int) s->memmap[VIRT_IOMMU_SYS].ba=
se);
+ iommu_phandle =3D qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_add_subnode(fdt, iommu_node);
+
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
+
+ qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
+ addr >> 32, addr, size >> 32, size);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
+
+ qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
+ iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
+
+ *iommu_sys_phandle =3D iommu_phandle;
+}
+
static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
{
const char comp[] =3D "riscv,pci-iommu";
@@ -1061,6 +1108,7 @@ static void finalize_fdt(RISCVVirtState *s)
{
uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1;
uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1;
+ uint32_t iommu_sys_phandle =3D 1;
=20
create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle,
&irq_pcie_phandle, &irq_virtio_phandle,
@@ -1068,7 +1116,11 @@ static void finalize_fdt(RISCVVirtState *s)
=20
create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
=20
- create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle);
+ if (virt_is_iommu_sys_enabled(s)) {
+ create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
+ }
+ create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
+ iommu_sys_phandle);
=20
create_fdt_reset(s, virt_memmap, &phandle);
=20
@@ -1648,6 +1700,22 @@ static void virt_machine_init(MachineState *machine)
create_fdt(s, memmap);
}
=20
+ if (virt_is_iommu_sys_enabled(s)) {
+ DeviceState *iommu_sys =3D qdev_new(TYPE_RISCV_IOMMU_SYS);
+
+ object_property_set_uint(OBJECT(iommu_sys), "addr",
+ s->memmap[VIRT_IOMMU_SYS].base,
+ &error_fatal);
+ object_property_set_uint(OBJECT(iommu_sys), "base-irq",
+ IOMMU_SYS_IRQ,
+ &error_fatal);
+ object_property_set_link(OBJECT(iommu_sys), "irqchip",
+ OBJECT(mmio_irqchip),
+ &error_fatal);
+
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
+ }
+
s->machine_done.notify =3D virt_machine_done;
qemu_add_machine_init_done_notifier(&s->machine_done);
}
@@ -1661,6 +1729,7 @@ static void virt_machine_instance_init(Object *obj)
s->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6);
s->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8);
s->acpi =3D ON_OFF_AUTO_AUTO;
+ s->iommu_sys =3D ON_OFF_AUTO_AUTO;
}
=20
static char *virt_get_aia_guests(Object *obj, Error **errp)
@@ -1733,6 +1802,28 @@ static void virt_set_aclint(Object *obj, bool value,=
Error **errp)
s->have_aclint =3D value;
}
=20
+bool virt_is_iommu_sys_enabled(RISCVVirtState *s)
+{
+ return s->iommu_sys =3D=3D ON_OFF_AUTO_ON;
+}
+
+static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj);
+ OnOffAuto iommu_sys =3D s->iommu_sys;
+
+ visit_type_OnOffAuto(v, name, &iommu_sys, errp);
+}
+
+static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
+}
+
bool virt_is_acpi_enabled(RISCVVirtState *s)
{
return s->acpi !=3D ON_OFF_AUTO_OFF;
@@ -1759,10 +1850,12 @@ static HotplugHandler *virt_machine_get_hotplug_han=
dler(MachineState *machine,
DeviceState *dev)
{
MachineClass *mc =3D MACHINE_GET_CLASS(machine);
+ RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine);
=20
if (device_is_dynamic_sysbus(mc, dev) ||
object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
+ s->iommu_sys =3D ON_OFF_AUTO_OFF;
return HOTPLUG_HANDLER(machine);
}
=20
@@ -1789,6 +1882,7 @@ static void virt_machine_device_plug_cb(HotplugHandle=
r *hotplug_dev,
=20
if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
+ s->iommu_sys =3D ON_OFF_AUTO_OFF;
}
}
=20
@@ -1851,6 +1945,12 @@ static void virt_machine_class_init(ObjectClass *oc,=
void *data)
NULL, NULL);
object_class_property_set_description(oc, "acpi",
"Enable ACPI");
+
+ object_class_property_add(oc, "iommu-sys", "OnOffAuto",
+ virt_get_iommu_sys, virt_set_iommu_sys,
+ NULL, NULL);
+ object_class_property_set_description(oc, "iommu-sys",
+ "Enable IOMMU platform device");
}
=20
static const TypeInfo virt_machine_typeinfo =3D {
--=20
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Subject: [PULL 07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
Date: Thu, 19 Dec 2024 08:29:37 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
MSIx support is added in the RISC-V IOMMU platform device by including
the required MSIx facilities to alow software to properly setup the MSIx
subsystem.
We took inspiration of what is being done in the riscv-iommu-pci device,
mainly msix_init() and msix_notify(), while keeping in mind that
riscv-iommu-sys isn't a true PCI device and we don't need to copy/paste
all the contents of these MSIx functions.
Two extra MSI MemoryRegions were added: 'msix-table' and 'msix-pba'.
They are used to manage r/w of the MSI table and Pending Bit Array (PBA)
respectively. Both are subregions of the main IOMMU memory region,
iommu->regs_mr, initialized during riscv_iommu_realize(), and each one
has their own handlers for MSIx reads and writes.
This is the expected memory map when using this device in the 'virt'
machine:
0000000003010000-0000000003010fff (prio 0, i/o): riscv-iommu-regs
0000000003010300-000000000301034f (prio 0, i/o): msix-table
0000000003010400-0000000003010407 (prio 0, i/o): msix-pba
We're now able to set IGS to RISCV_IOMMU_CAP_IGS_BOTH, and userspace is
free to decide which interrupt model to use.
Enabling MSIx support for this device in the 'virt' machine requires
adding 'msi-parent' in the iommu-sys DT.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/riscv-iommu-sys.c | 116 +++++++++++++++++++++++++++++++++++--
hw/riscv/virt.c | 6 +-
hw/riscv/trace-events | 2 +
3 files changed, 119 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index 4b82046ce9..a0ef67a20b 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -26,11 +26,15 @@
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qom/object.h"
+#include "exec/exec-all.h"
+#include "trace.h"
=20
#include "riscv-iommu.h"
=20
#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
=20
+#define RISCV_IOMMU_PCI_MSIX_VECTORS 5
+
/* RISC-V IOMMU System Platform Device Emulation */
=20
struct RISCVIOMMUStateSys {
@@ -39,21 +43,123 @@ struct RISCVIOMMUStateSys {
uint32_t base_irq;
DeviceState *irqchip;
RISCVIOMMUState iommu;
+
+ /* Wired int support */
qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
+
+ /* Memory Regions for MSIX table and pending bit entries. */
+ MemoryRegion msix_table_mmio;
+ MemoryRegion msix_pba_mmio;
+ uint8_t *msix_table;
+ uint8_t *msix_pba;
+};
+
+static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ RISCVIOMMUStateSys *s =3D opaque;
+
+ g_assert(addr + size <=3D RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTR=
Y_SIZE);
+ return pci_get_long(s->msix_table + addr);
+}
+
+static void msix_table_mmio_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ RISCVIOMMUStateSys *s =3D opaque;
+
+ g_assert(addr + size <=3D RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTR=
Y_SIZE);
+ pci_set_long(s->msix_table + addr, val);
+}
+
+static const MemoryRegionOps msix_table_mmio_ops =3D {
+ .read =3D msix_table_mmio_read,
+ .write =3D msix_table_mmio_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 8,
+ },
+ .impl =3D {
+ .max_access_size =3D 4,
+ },
+};
+
+static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ RISCVIOMMUStateSys *s =3D opaque;
+
+ return pci_get_long(s->msix_pba + addr);
+}
+
+static void msix_pba_mmio_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static const MemoryRegionOps msix_pba_mmio_ops =3D {
+ .read =3D msix_pba_mmio_read,
+ .write =3D msix_pba_mmio_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 8,
+ },
+ .impl =3D {
+ .max_access_size =3D 4,
+ },
};
=20
+static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s,
+ uint32_t n_vectors)
+{
+ RISCVIOMMUState *iommu =3D &s->iommu;
+ uint32_t table_size =3D table_size =3D n_vectors * PCI_MSIX_ENTRY_SIZE;
+ uint32_t table_offset =3D RISCV_IOMMU_REG_MSI_CONFIG;
+ uint32_t pba_size =3D QEMU_ALIGN_UP(n_vectors, 64) / 8;
+ uint32_t pba_offset =3D RISCV_IOMMU_REG_MSI_CONFIG + 256;
+
+ s->msix_table =3D g_malloc0(table_size);
+ s->msix_pba =3D g_malloc0(pba_size);
+
+ memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio=
_ops,
+ s, "msix-table", table_size);
+ memory_region_add_subregion(&iommu->regs_mr, table_offset,
+ &s->msix_table_mmio);
+
+ memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops=
, s,
+ "msix-pba", pba_size);
+ memory_region_add_subregion(&iommu->regs_mr, pba_offset,
+ &s->msix_pba_mmio);
+}
+
+static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
+ uint32_t vector)
+{
+ uint8_t *table_entry =3D s->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
+ uint64_t msi_addr =3D pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_=
ADDR);
+ uint32_t msi_data =3D pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
+ MemTxResult result;
+
+ address_space_stl_le(&address_space_memory, msi_addr,
+ msi_data, MEMTXATTRS_UNSPECIFIED, &result);
+ trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
+}
+
static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
unsigned vector)
{
RISCVIOMMUStateSys *s =3D container_of(iommu, RISCVIOMMUStateSys, iomm=
u);
uint32_t fctl =3D riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
=20
- /* We do not support MSIs yet */
- if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
+ if (fctl & RISCV_IOMMU_FCTL_WSI) {
+ qemu_irq_pulse(s->irqs[vector]);
+ trace_riscv_iommu_sys_irq_sent(vector);
return;
}
=20
- qemu_irq_pulse(s->irqs[vector]);
+ riscv_iommu_sysdev_send_MSI(s, vector);
}
=20
static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
@@ -82,6 +188,8 @@ static void riscv_iommu_sys_realize(DeviceState *dev, Er=
ror **errp)
irq =3D qdev_get_gpio_in(s->irqchip, s->base_irq + i);
sysbus_connect_irq(sysdev, i, irq);
}
+
+ riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS);
}
=20
static void riscv_iommu_sys_init(Object *obj)
@@ -93,7 +201,7 @@ static void riscv_iommu_sys_init(Object *obj)
qdev_alias_all_properties(DEVICE(iommu), obj);
=20
iommu->icvec_avail_vectors =3D RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
- riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
+ riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
}
=20
static Property riscv_iommu_sys_properties[] =3D {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c5ada635f1..5d058511be 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1043,6 +1043,7 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s=
, uint16_t bdf)
}
=20
static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
+ uint32_t msi_phandle,
uint32_t *iommu_sys_phandle)
{
const char comp[] =3D "riscv,iommu";
@@ -1077,6 +1078,8 @@ static void create_fdt_iommu_sys(RISCVVirtState *s, u=
int32_t irq_chip,
iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
=20
+ qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
+
*iommu_sys_phandle =3D iommu_phandle;
}
=20
@@ -1117,7 +1120,8 @@ static void finalize_fdt(RISCVVirtState *s)
create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
=20
if (virt_is_iommu_sys_enabled(s)) {
- create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
+ create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
+ &iommu_sys_phandle);
}
create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
iommu_sys_phandle);
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
index 0527c56c91..94facbb8b1 100644
--- a/hw/riscv/trace-events
+++ b/hw/riscv/trace-events
@@ -15,3 +15,5 @@ riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "=
ICVEC write: incoming 0
riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64=
_t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64
riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate"
riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group res=
ponse"
+riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
+riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_=
data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x =
result %u"
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 08/39] hw/riscv/riscv-iommu: implement reset protocol
Date: Thu, 19 Dec 2024 08:29:38 +1000
Message-ID: <20241218223010.1931245-9-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Add a riscv_iommu_reset() helper in the base emulation code that
implements the expected reset behavior as defined by the riscv-iommu
spec.
Devices can then use this helper in their own reset callbacks.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/riscv-iommu.h | 1 +
include/hw/riscv/iommu.h | 6 ++++--
hw/riscv/riscv-iommu-pci.c | 20 ++++++++++++++++++++
hw/riscv/riscv-iommu-sys.c | 20 ++++++++++++++++++++
hw/riscv/riscv-iommu.c | 35 +++++++++++++++++++++++++++++++++++
hw/riscv/trace-events | 2 ++
6 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
index f9f2827808..9424989df4 100644
--- a/hw/riscv/riscv-iommu.h
+++ b/hw/riscv/riscv-iommu.h
@@ -89,6 +89,7 @@ struct RISCVIOMMUState {
void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
Error **errp);
void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode=
);
+void riscv_iommu_reset(RISCVIOMMUState *s);
=20
/* private helpers */
=20
diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index 8a8acfc3f0..b03339d75c 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -30,12 +30,14 @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
=20
#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
-OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
+OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PC=
I)
typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
+typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
=20
#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
-OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
+OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SY=
S)
typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
+typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
=20
#define FDT_IRQ_TYPE_EDGE_LOW 1
=20
diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index a95d0f74c8..2c1ae72461 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -31,6 +31,7 @@
#include "cpu_bits.h"
#include "riscv-iommu.h"
#include "riscv-iommu-bits.h"
+#include "trace.h"
=20
/* RISC-V IOMMU PCI Device Emulation */
#define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806
@@ -66,6 +67,12 @@ typedef struct RISCVIOMMUStatePci {
RISCVIOMMUState iommu; /* common IOMMU state */
} RISCVIOMMUStatePci;
=20
+struct RISCVIOMMUPciClass {
+ /*< public >*/
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
/* interrupt delivery callback */
static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
{
@@ -167,10 +174,23 @@ static const Property riscv_iommu_pci_properties[] =
=3D {
DEFINE_PROP_END_OF_LIST(),
};
=20
+static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type)
+{
+ RISCVIOMMUStatePci *pci =3D RISCV_IOMMU_PCI(obj);
+ RISCVIOMMUState *iommu =3D &pci->iommu;
+
+ riscv_iommu_reset(iommu);
+
+ trace_riscv_iommu_pci_reset_hold(type);
+}
+
static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass);
+ ResettableClass *rc =3D RESETTABLE_CLASS(klass);
+
+ rc->phases.hold =3D riscv_iommu_pci_reset_hold;
=20
k->realize =3D riscv_iommu_pci_realize;
k->exit =3D riscv_iommu_pci_exit;
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index a0ef67a20b..605979a0ac 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -54,6 +54,12 @@ struct RISCVIOMMUStateSys {
uint8_t *msix_pba;
};
=20
+struct RISCVIOMMUSysClass {
+ /*< public >*/
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
@@ -212,9 +218,23 @@ static Property riscv_iommu_sys_properties[] =3D {
DEFINE_PROP_END_OF_LIST(),
};
=20
+static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type)
+{
+ RISCVIOMMUStateSys *sys =3D RISCV_IOMMU_SYS(obj);
+ RISCVIOMMUState *iommu =3D &sys->iommu;
+
+ riscv_iommu_reset(iommu);
+
+ trace_riscv_iommu_sys_reset_hold(type);
+}
+
static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
+ ResettableClass *rc =3D RESETTABLE_CLASS(klass);
+
+ rc->phases.hold =3D riscv_iommu_sys_reset_hold;
+
dc->realize =3D riscv_iommu_sys_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
device_class_set_props(dc, riscv_iommu_sys_properties);
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 9137217cb7..72e607c9eb 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2262,6 +2262,41 @@ static void riscv_iommu_unrealize(DeviceState *dev)
g_hash_table_unref(s->ctx_cache);
}
=20
+void riscv_iommu_reset(RISCVIOMMUState *s)
+{
+ uint32_t reg_clr;
+ int ddtp_mode;
+
+ /*
+ * Clear DDTP while setting DDTP_mode back to user
+ * initial setting.
+ */
+ ddtp_mode =3D s->enable_off ?
+ RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE;
+ s->ddtp =3D set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode);
+ riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, s->ddtp);
+
+ reg_clr =3D RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE |
+ RISCV_IOMMU_CQCSR_CQON | RISCV_IOMMU_CQCSR_BUSY;
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, 0, reg_clr);
+
+ reg_clr =3D RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE |
+ RISCV_IOMMU_FQCSR_FQON | RISCV_IOMMU_FQCSR_BUSY;
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, 0, reg_clr);
+
+ reg_clr =3D RISCV_IOMMU_PQCSR_PQEN | RISCV_IOMMU_PQCSR_PIE |
+ RISCV_IOMMU_PQCSR_PQON | RISCV_IOMMU_PQCSR_BUSY;
+ riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, 0, reg_clr);
+
+ riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0,
+ RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
+
+ riscv_iommu_reg_set32(s, RISCV_IOMMU_REG_IPSR, 0);
+
+ g_hash_table_remove_all(s->ctx_cache);
+ g_hash_table_remove_all(s->iot_cache);
+}
+
static const Property riscv_iommu_properties[] =3D {
DEFINE_PROP_UINT32("version", RISCVIOMMUState, version,
RISCV_IOMMU_SPEC_DOT_VER),
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
index 94facbb8b1..aaa2c0eb94 100644
--- a/hw/riscv/trace-events
+++ b/hw/riscv/trace-events
@@ -17,3 +17,5 @@ riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb inva=
lidate"
riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group res=
ponse"
riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_=
data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x =
result %u"
+riscv_iommu_sys_reset_hold(int reset_type) "reset type %d"
+riscv_iommu_pci_reset_hold(int reset_type) "reset type %d"
--=20
2.47.1
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Subject: [PULL 09/39] docs/specs: add riscv-iommu-sys information
Date: Thu, 19 Dec 2024 08:29:39 +1000
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---
docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++---
docs/system/riscv/virt.rst | 10 ++++++++++
2 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
index 463f4cffb6..b1538c9ead 100644
--- a/docs/specs/riscv-iommu.rst
+++ b/docs/specs/riscv-iommu.rst
@@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines
QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
version 1.0 `iommu1.0`_.
=20
-The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
-RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
-device.
+The emulation includes a PCI reference device (riscv-iommu-pci) and a plat=
form
+bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
+RISC-V machine is compatible with both devices.
=20
riscv-iommu-pci reference device
--------------------------------
@@ -83,6 +83,30 @@ Several options are available to control the capabilitie=
s of the device, namely:
- "s-stage": enable s-stage support
- "g-stage": enable g-stage support
=20
+riscv-iommu-sys device
+----------------------
+
+This device implements the RISC-V IOMMU emulation as a platform bus device=
that
+RISC-V boards can use.
+
+For the 'virt' board the device is disabled by default. To enable it use =
the
+'iommu-sys' machine option:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...)
+
+There is no options to configure the capabilities of this device in the 'v=
irt'
+board using the QEMU command line. The device is configured with the foll=
owing
+riscv-iommu options:
+
+- "ioatc-limit": default value (2Mb)
+- "intremap": enabled
+- "ats": enabled
+- "off": on (DMA disabled)
+- "s-stage": enabled
+- "g-stage": enabled
+
.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo=
ad/v1.0/riscv-iommu.pdf
=20
.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje=
znach@rivosinc.com/
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 8e9a2e4dda..537aac0340 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -94,6 +94,12 @@ command line:
=20
$ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
=20
+It also has support for the riscv-iommu-sys platform device:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M virt,iommu-sys=3Don (...)
+
Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU s=
upport
works.
=20
@@ -129,6 +135,10 @@ The following machine-specific options are supported:
having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified,
the default number of per-HART VS-level AIA IMSIC pages is 0.
=20
+- iommu-sys=3D[on|off]
+
+ Enables the riscv-iommu-sys platform device. Defaults to 'off'.
+
Running Linux kernel
--------------------
=20
--=20
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To: qemu-devel@nongnu.org
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Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 10/39] target/riscv: Add Tenstorrent Ascalon CPU
Date: Thu, 19 Dec 2024 08:29:40 +1000
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From: Anton Blanchard <antonb@tenstorrent.com>
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241113110459.1607299-1-antonb@tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 62115375cd..6547642287 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -49,6 +49,7 @@
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
+#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
=20
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4329015076..66e00ed260 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -579,6 +579,72 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
=20
+/* Tenstorrent Ascalon */
+static void rv64_tt_ascalon_cpu_init(Object *obj)
+{
+ CPURISCVState *env =3D &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu =3D RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
+ env->priv_ver =3D PRIV_VERSION_1_13_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu =3D true;
+ cpu->cfg.vlenb =3D 256 >> 3;
+ cpu->cfg.elen =3D 64;
+ cpu->env.vext_ver =3D VEXT_VERSION_1_00_0;
+ cpu->cfg.rvv_ma_all_1s =3D true;
+ cpu->cfg.rvv_ta_all_1s =3D true;
+ cpu->cfg.misa_w =3D true;
+ cpu->cfg.pmp =3D true;
+ cpu->cfg.cbom_blocksize =3D 64;
+ cpu->cfg.cbop_blocksize =3D 64;
+ cpu->cfg.cboz_blocksize =3D 64;
+ cpu->cfg.ext_zic64b =3D true;
+ cpu->cfg.ext_zicbom =3D true;
+ cpu->cfg.ext_zicbop =3D true;
+ cpu->cfg.ext_zicboz =3D true;
+ cpu->cfg.ext_zicntr =3D true;
+ cpu->cfg.ext_zicond =3D true;
+ cpu->cfg.ext_zicsr =3D true;
+ cpu->cfg.ext_zifencei =3D true;
+ cpu->cfg.ext_zihintntl =3D true;
+ cpu->cfg.ext_zihintpause =3D true;
+ cpu->cfg.ext_zihpm =3D true;
+ cpu->cfg.ext_zimop =3D true;
+ cpu->cfg.ext_zawrs =3D true;
+ cpu->cfg.ext_zfa =3D true;
+ cpu->cfg.ext_zfbfmin =3D true;
+ cpu->cfg.ext_zfh =3D true;
+ cpu->cfg.ext_zfhmin =3D true;
+ cpu->cfg.ext_zcb =3D true;
+ cpu->cfg.ext_zcmop =3D true;
+ cpu->cfg.ext_zba =3D true;
+ cpu->cfg.ext_zbb =3D true;
+ cpu->cfg.ext_zbs =3D true;
+ cpu->cfg.ext_zkt =3D true;
+ cpu->cfg.ext_zvbb =3D true;
+ cpu->cfg.ext_zvbc =3D true;
+ cpu->cfg.ext_zvfbfmin =3D true;
+ cpu->cfg.ext_zvfbfwma =3D true;
+ cpu->cfg.ext_zvfh =3D true;
+ cpu->cfg.ext_zvfhmin =3D true;
+ cpu->cfg.ext_zvkng =3D true;
+ cpu->cfg.ext_smaia =3D true;
+ cpu->cfg.ext_smstateen =3D true;
+ cpu->cfg.ext_ssaia =3D true;
+ cpu->cfg.ext_sscofpmf =3D true;
+ cpu->cfg.ext_sstc =3D true;
+ cpu->cfg.ext_svade =3D true;
+ cpu->cfg.ext_svinval =3D true;
+ cpu->cfg.ext_svnapot =3D true;
+ cpu->cfg.ext_svpbmt =3D true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -2984,6 +3050,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_=
cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_=
cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90=
6_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo=
n_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1=
_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu=
_init),
--=20
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From: Alistair Francis <alistair23@gmail.com>
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 11/39] hw/intc/riscv_aplic: rename is_kvm_aia()
Date: Thu, 19 Dec 2024 08:29:41 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=3Daplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.
Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.
Make the helper public because the 'virt' machine will use it as well.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/riscv_aplic.h | 1 +
hw/intc/riscv_aplic.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index de8532fbc3..fd0e6427d9 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -71,6 +71,7 @@ struct RISCVAPLICState {
};
=20
void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
=20
DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 3edab64b97..9f9814a40b 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -154,7 +154,7 @@
* KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want =
to use
* APLIC Wired.
*/
-static bool is_kvm_aia(bool msimode)
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
{
return kvm_irqchip_in_kernel() && msimode;
}
@@ -857,7 +857,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error=
**errp)
uint32_t i;
RISCVAPLICState *aplic =3D RISCV_APLIC(dev);
=20
- if (!is_kvm_aia(aplic->msimode)) {
+ if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs);
aplic->state =3D g_new0(uint32_t, aplic->num_irqs);
@@ -881,7 +881,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error=
**errp)
* have IRQ lines delegated by their parent APLIC.
*/
if (!aplic->parent) {
- if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
+ if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode))=
{
qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq=
s);
} else {
qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
@@ -1025,7 +1025,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s=
ize,
=20
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
=20
- if (!is_kvm_aia(msimode)) {
+ if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
}
=20
--=20
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
Date: Thu, 19 Dec 2024 08:29:42 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
In create_fdt_sockets() we have the following pattern:
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do stuff ...)
} else {
(... do other stuff ...)
}
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do more stuff ...)
} else {
(... do more other stuff)
}
Do everything in a single if/else clause to reduce the usage of
virt_use_kvm_aia() helper and to make the code a bit less repetitive.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5d058511be..e54e1257c0 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -783,6 +783,10 @@ static void create_fdt_sockets(RISCVVirtState *s, cons=
t MemMapEntry *memmap,
msi_m_phandle, msi_s_phandle, phandle,
&intc_phandles[0], xplic_phandles,
ms->smp.cpus);
+
+ *irq_mmio_phandle =3D xplic_phandles[0];
+ *irq_virtio_phandle =3D xplic_phandles[0];
+ *irq_pcie_phandle =3D xplic_phandles[0];
} else {
phandle_pos =3D ms->smp.cpus;
for (socket =3D (socket_count - 1); socket >=3D 0; socket--) {
@@ -800,13 +804,7 @@ static void create_fdt_sockets(RISCVVirtState *s, cons=
t MemMapEntry *memmap,
s->soc[socket].num_harts);
}
}
- }
=20
- if (kvm_enabled() && virt_use_kvm_aia(s)) {
- *irq_mmio_phandle =3D xplic_phandles[0];
- *irq_virtio_phandle =3D xplic_phandles[0];
- *irq_pcie_phandle =3D xplic_phandles[0];
- } else {
for (socket =3D 0; socket < socket_count; socket++) {
if (socket =3D=3D 0) {
*irq_mmio_phandle =3D xplic_phandles[socket];
--=20
2.47.1
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Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 13/39] hw/riscv/virt.c: rename helper to
virt_use_kvm_aia_aplic_imsic()
Date: Thu, 19 Dec 2024 08:29:43 +1000
Message-ID: <20241218223010.1931245-14-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
the existing virt_use_kvm_aia() is testing for KVM aia=3Daplic-imsic with
in-kernel irqchip enabled. It is not checking for a generic AIA support.
Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the
helper is doing, and use the existing riscv_is_kvm_aia_aplic_imsic() to
obscure details such as the presence of the in-kernel irqchip.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e54e1257c0..a67ab80b16 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -59,9 +59,11 @@
#include "hw/virtio/virtio-iommu.h"
=20
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU=
. */
-static bool virt_use_kvm_aia(RISCVVirtState *s)
+static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
{
- return kvm_irqchip_in_kernel() && s->aia_type =3D=3D VIRT_AIA_TYPE_APL=
IC_IMSIC;
+ bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC;
+
+ return riscv_is_kvm_aia_aplic_imsic(msimode);
}
=20
static bool virt_aclint_allowed(void)
@@ -777,8 +779,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const=
MemMapEntry *memmap,
*msi_pcie_phandle =3D msi_s_phandle;
}
=20
- /* KVM AIA only has one APLIC instance */
- if (kvm_enabled() && virt_use_kvm_aia(s)) {
+ /* KVM AIA aplic-imsic only has one APLIC instance */
+ if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
create_fdt_socket_aplic(s, memmap, 0,
msi_m_phandle, msi_s_phandle, phandle,
&intc_phandles[0], xplic_phandles,
@@ -1619,7 +1621,7 @@ static void virt_machine_init(MachineState *machine)
}
}
=20
- if (kvm_enabled() && virt_use_kvm_aia(s)) {
+ if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MS=
IS,
memmap[VIRT_APLIC_S].base,
--=20
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 14/39] target/riscv/kvm: consider irqchip_split() in
aia_create()
Date: Thu, 19 Dec 2024 08:29:44 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Before adding support to kernel-irqchip=3Dsplit when using KVM AIA we need
to change how we create the in-kernel AIA device.
In the use case we have so far, i.e. in-kernel irqchip without split
mode, both the s-mode APLIC and IMSIC controllers are provided by the
irqchip. In irqchip_split() mode we'll emulate the s-mode APLIC
controller, which will send MSIs to the in-kernel IMSIC controller. To
do that we need to change kvm_riscv_aia_create() to not create the
in-kernel s-mode APLIC controller.
In the kernel source arch/riscv/kvm/aia_aplic.c, function
kvm_riscv_aia_aplic_init(), we verify that the APLIC controller won't be
instantiated by KVM if we do not set 'nr_sources', which is set via
KVM_DEV_RISCV_AIA_CONFIG_SRCS. For QEMU this means that we should not
set 'aia_irq_num' during kvm_riscv_aia_create() in irqchip_split() mode.
In this same condition, skip KVM_DEV_RISCV_AIA_ADDR_APLIC as well since
it is used to set the base address for the in-kernel APLIC controller.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 38 +++++++++++++++++++++++---------------
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index c53ca1f76b..a9680f2447 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1734,13 +1734,29 @@ void kvm_riscv_aia_create(MachineState *machine, ui=
nt64_t group_shift,
}
}
=20
- ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
- KVM_DEV_RISCV_AIA_CONFIG_SRCS,
- &aia_irq_num, true, NULL);
- if (ret < 0) {
- error_report("KVM AIA: failed to set number of input irq lines");
- exit(1);
- }
+ /*
+ * Skip APLIC creation in KVM if we're running split mode.
+ * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS
+ * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC
+ * since KVM won't be using it.
+ */
+ if (!kvm_kernel_irqchip_split()) {
+ ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+ KVM_DEV_RISCV_AIA_CONFIG_SRCS,
+ &aia_irq_num, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: failed to set number of input irq lines=
");
+ exit(1);
+ }
+
+ ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+ KVM_DEV_RISCV_AIA_ADDR_APLIC,
+ &aplic_base, true, NULL);
+ if (ret < 0) {
+ error_report("KVM AIA: failed to set the base address of APLIC=
");
+ exit(1);
+ }
+ }
=20
ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
KVM_DEV_RISCV_AIA_CONFIG_IDS,
@@ -1781,14 +1797,6 @@ void kvm_riscv_aia_create(MachineState *machine, uin=
t64_t group_shift,
exit(1);
}
=20
- ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
- KVM_DEV_RISCV_AIA_ADDR_APLIC,
- &aplic_base, true, NULL);
- if (ret < 0) {
- error_report("KVM AIA: failed to set the base address of APLIC");
- exit(1);
- }
-
for (socket =3D 0; socket < socket_count; socket++) {
socket_imsic_base =3D imsic_base + socket * (1U << group_shift);
hart_count =3D riscv_socket_hart_count(machine, socket);
--=20
2.47.1
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 15/39] hw/riscv/virt.c,
riscv_aplic.c: add 'emulated_aplic' helpers
Date: Thu, 19 Dec 2024 08:29:45 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The current logic to determine if we don't need an emulated APLIC
controller, i.e. KVM will provide for us, is to determine if we're
running KVM, with in-kernel irqchip support, and running
aia=3Daplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
virt_use_kvm_aia_aplic_imsic().
This won't suffice to support irqchip_split() mode: it will match
exactly the same conditions as the one above, but setting the irqchip to
'split' mode will now require us to emulate an APLIC s-mode controller,
like we're doing with 'aia=3Daplic'.
Create a new riscv_use_emulated_aplic() helper that will encapsulate
this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with
this helper every time we're taking a decision on emulate an APLIC
controller or not. Do the same in virt.c with virt_use_emulated_aplic().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/riscv_aplic.h | 1 +
hw/intc/riscv_aplic.c | 24 +++++++++++++++++++++---
hw/riscv/virt.c | 14 ++++++++++++--
3 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index fd0e6427d9..74ae5d87b5 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -72,6 +72,7 @@ struct RISCVAPLICState {
=20
void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
+bool riscv_use_emulated_aplic(bool msimode);
=20
DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 9f9814a40b..ba4e802888 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -32,6 +32,7 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "kvm/kvm_riscv.h"
#include "migration/vmstate.h"
=20
@@ -159,6 +160,23 @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
return kvm_irqchip_in_kernel() && msimode;
}
=20
+bool riscv_use_emulated_aplic(bool msimode)
+{
+#ifdef CONFIG_KVM
+ if (tcg_enabled()) {
+ return true;
+ }
+
+ if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
+ return true;
+ }
+
+ return kvm_kernel_irqchip_split();
+#else
+ return true;
+#endif
+}
+
static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
uint32_t irq)
{
@@ -857,7 +875,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error=
**errp)
uint32_t i;
RISCVAPLICState *aplic =3D RISCV_APLIC(dev);
=20
- if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
+ if (riscv_use_emulated_aplic(aplic->msimode)) {
aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs);
aplic->state =3D g_new0(uint32_t, aplic->num_irqs);
@@ -881,7 +899,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error=
**errp)
* have IRQ lines delegated by their parent APLIC.
*/
if (!aplic->parent) {
- if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode))=
{
+ if (kvm_enabled() && !riscv_use_emulated_aplic(aplic->msimode)) {
qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq=
s);
} else {
qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
@@ -1025,7 +1043,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s=
ize,
=20
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
=20
- if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
+ if (riscv_use_emulated_aplic(msimode)) {
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
}
=20
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a67ab80b16..937dfd1ef2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -66,6 +66,13 @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIATyp=
e aia_type)
return riscv_is_kvm_aia_aplic_imsic(msimode);
}
=20
+static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
+{
+ bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC;
+
+ return riscv_use_emulated_aplic(msimode);
+}
+
static bool virt_aclint_allowed(void)
{
return tcg_enabled() || qtest_enabled();
@@ -779,8 +786,11 @@ static void create_fdt_sockets(RISCVVirtState *s, cons=
t MemMapEntry *memmap,
*msi_pcie_phandle =3D msi_s_phandle;
}
=20
- /* KVM AIA aplic-imsic only has one APLIC instance */
- if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
+ /*
+ * With KVM AIA aplic-imsic, using an irqchip without split
+ * mode, we'll use only one APLIC instance.
+ */
+ if (!virt_use_emulated_aplic(s->aia_type)) {
create_fdt_socket_aplic(s, memmap, 0,
msi_m_phandle, msi_s_phandle, phandle,
&intc_phandles[0], xplic_phandles,
--=20
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode
aplic-imsic
Date: Thu, 19 Dec 2024 08:29:46 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The last step to enable KVM AIA aplic-imsic with irqchip in split mode
is to deal with how MSIs are going to be sent. In our current design we
don't allow an APLIC controller to send MSIs unless it's on m-mode. And
we also do not allow Supervisor MSI address configuration via the
'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode
APLIC controller.
Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This
attribute represents the base configuration address for MSIs, in our
case the base addr of the IMSIC controller. This attribute is being set
only when running irqchip_split() mode with aia=3Daplic-imsic.
During riscv_aplic_msi_send() we'll check if the attribute was set to
skip the check for a m-mode APLIC controller and to change the resulting
MSI addr by adding kvm_msicfgaddr right before address_space_stl_le().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/intc/riscv_aplic.h | 6 +++++
hw/intc/riscv_aplic.c | 42 +++++++++++++++++++++++++++--------
hw/riscv/virt.c | 6 ++++-
3 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index 74ae5d87b5..489b9133c2 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -68,11 +68,17 @@ struct RISCVAPLICState {
uint32_t num_irqs;
bool msimode;
bool mmode;
+
+ /* To support KVM aia=3Daplic-imsic with irqchip split mode */
+ bool kvm_splitmode;
+ uint32_t kvm_msicfgaddr;
+ uint32_t kvm_msicfgaddrH;
};
=20
void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
bool riscv_use_emulated_aplic(bool msimode);
+void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr);
=20
DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index ba4e802888..1e4cdb500c 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -177,6 +177,16 @@ bool riscv_use_emulated_aplic(bool msimode)
#endif
}
=20
+void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
+{
+#ifdef CONFIG_KVM
+ if (riscv_use_emulated_aplic(aplic->msimode)) {
+ aplic->kvm_msicfgaddr =3D extract64(addr, 0, 32);
+ aplic->kvm_msicfgaddrH =3D extract64(addr, 32, 32);
+ }
+#endif
+}
+
static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
uint32_t irq)
{
@@ -381,13 +391,16 @@ static void riscv_aplic_msi_send(RISCVAPLICState *apl=
ic,
uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
=20
aplic_m =3D aplic;
- while (aplic_m && !aplic_m->mmode) {
- aplic_m =3D aplic_m->parent;
- }
- if (!aplic_m) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
- __func__);
- return;
+
+ if (!aplic->kvm_splitmode) {
+ while (aplic_m && !aplic_m->mmode) {
+ aplic_m =3D aplic_m->parent;
+ }
+ if (!aplic_m) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
+ __func__);
+ return;
+ }
}
=20
if (aplic->mmode) {
@@ -419,6 +432,11 @@ static void riscv_aplic_msi_send(RISCVAPLICState *apli=
c,
addr |=3D (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
addr <<=3D APLIC_xMSICFGADDR_PPN_SHIFT;
=20
+ if (aplic->kvm_splitmode) {
+ addr |=3D aplic->kvm_msicfgaddr;
+ addr |=3D ((uint64_t)aplic->kvm_msicfgaddrH << 32);
+ }
+
address_space_stl_le(&address_space_memory, addr,
eiid, MEMTXATTRS_UNSPECIFIED, &result);
if (result !=3D MEMTX_OK) {
@@ -892,6 +910,10 @@ static void riscv_aplic_realize(DeviceState *dev, Erro=
r **errp)
memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
aplic, TYPE_RISCV_APLIC, aplic->aperture_siz=
e);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+
+ if (kvm_enabled()) {
+ aplic->kvm_splitmode =3D true;
+ }
}
=20
/*
@@ -939,8 +961,8 @@ static const Property riscv_aplic_properties[] =3D {
=20
static const VMStateDescription vmstate_riscv_aplic =3D {
.name =3D "riscv_aplic",
- .version_id =3D 1,
- .minimum_version_id =3D 1,
+ .version_id =3D 2,
+ .minimum_version_id =3D 2,
.fields =3D (const VMStateField[]) {
VMSTATE_UINT32(domaincfg, RISCVAPLICState),
VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
@@ -948,6 +970,8 @@ static const VMStateDescription vmstate_riscv_aplic =3D=
{
VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
VMSTATE_UINT32(genmsi, RISCVAPLICState),
+ VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState),
+ VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState),
VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
num_irqs, 0,
vmstate_info_uint32, uint32_t),
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 937dfd1ef2..43a1c86c33 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1300,7 +1300,7 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType =
aia_type, int aia_guests,
int base_hartid, int hart_count)
{
int i;
- hwaddr addr;
+ hwaddr addr =3D 0;
uint32_t guest_bits;
DeviceState *aplic_s =3D NULL;
DeviceState *aplic_m =3D NULL;
@@ -1350,6 +1350,10 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType=
aia_type, int aia_guests,
VIRT_IRQCHIP_NUM_PRIO_BITS,
msimode, false, aplic_m);
=20
+ if (kvm_enabled() && msimode) {
+ riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
+ }
+
return kvm_enabled() ? aplic_s : aplic_m;
}
=20
--=20
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction
Date: Thu, 19 Dec 2024 08:29:47 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
we have support for "-accel kvm,kernel-irqchip=3Dsplit".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index a9680f2447..aaff4a0f42 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1408,11 +1408,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
=20
int kvm_arch_irqchip_create(KVMState *s)
{
- if (kvm_kernel_irqchip_split()) {
- error_report("-machine kernel_irqchip=3Dsplit is not supported on =
RISC-V.");
- exit(1);
- }
-
/*
* We can create the VAIA using the newer device control API.
*/
--=20
2.47.1
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split
support
Date: Thu, 19 Dec 2024 08:29:48 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
the state of AIA support in QEMU w.r.t the controllers being emulated or
not depending on the AIA and accelerator settings.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/specs/index.rst | 1 +
docs/specs/riscv-aia.rst | 83 ++++++++++++++++++++++++++++++++++++++
docs/system/riscv/virt.rst | 7 ++++
3 files changed, 91 insertions(+)
create mode 100644 docs/specs/riscv-aia.rst
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
index ff5a1f03da..d7675cebc2 100644
--- a/docs/specs/index.rst
+++ b/docs/specs/index.rst
@@ -37,3 +37,4 @@ guest hardware that is specific to QEMU.
rapl-msr
rocker
riscv-iommu
+ riscv-aia
diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst
new file mode 100644
index 0000000000..8097e2f897
--- /dev/null
+++ b/docs/specs/riscv-aia.rst
@@ -0,0 +1,83 @@
+.. _riscv-aia:
+
+RISC-V AIA support for RISC-V machines
+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+
+AIA (Advanced Interrupt Architecture) support is implemented in the ``virt=
``
+RISC-V machine for TCG and KVM accelerators.
+
+The support consists of two main modes:
+
+- "aia=3Daplic": adds one or more APLIC (Advanced Platform Level Interrupt=
Controller)
+ devices
+- "aia=3Daplic-imsic": adds one or more APLIC device and an IMSIC (Incomin=
g MSI
+ Controller) device for each CPU
+
+From an user standpoint, these modes will behave the same regardless of th=
e accelerator
+used. From a developer standpoint the accelerator settings will change wh=
at it being
+emulated in userspace versus what is being emulated by an in-kernel irqchi=
p.
+
+When running TCG, all controllers are emulated in userspace, including mac=
hine mode
+(m-mode) APLIC and IMSIC (when applicable).
+
+When running KVM:
+
+- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation re=
gardless of
+ the AIA mode chosen
+- with "aia=3Daplic", s-mode APLIC will be emulated by userspace
+- with "aia=3Daplic-imsic" there are two possibilities. If no additional =
KVM option
+ is provided there will be no APLIC or IMSIC emulation in userspace, and =
the virtual
+ machine will use the provided in-kernel APLIC and IMSIC controllers. If=
the user
+ chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=
=3Dsplit",
+ s-mode APLIC will be emulated while using the s-mode IMSIC from the irqc=
hip
+
+The following table summarizes how the AIA and accelerator options defines=
what
+we will emulate in userspace:
+
+
+.. list-table:: How AIA and accel options changes controller emulation
+ :widths: 25 25 25 25 25 25 25
+ :header-rows: 1
+
+ * - Accel
+ - Accel props
+ - AIA type
+ - APLIC m-mode
+ - IMSIC m-mode
+ - APLIC s-mode
+ - IMSIC s-mode
+ * - tcg
+ - ---
+ - aplic
+ - emul
+ - n/a
+ - emul
+ - n/a
+ * - tcg
+ - ---
+ - aplic-imsic
+ - emul
+ - emul
+ - emul
+ - emul
+ * - kvm
+ - ---
+ - aplic
+ - n/a
+ - n/a
+ - emul
+ - n/a
+ * - kvm
+ - none
+ - aplic-imsic
+ - n/a
+ - n/a
+ - in-kernel
+ - in-kernel
+ * - kvm
+ - irqchip=3Dsplit
+ - aplic-imsic
+ - n/a
+ - n/a
+ - emul
+ - in-kernel
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 537aac0340..60850970ce 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -129,6 +129,13 @@ The following machine-specific options are supported:
MSIs. When not specified, this option is assumed to be "none" which sele=
cts
SiFive PLIC to handle wired interrupts.
=20
+ This option also interacts with '-accel kvm'. When using "aia=3Daplic-i=
msic"
+ with KVM, it is possible to set the use of the kernel irqchip in split m=
ode
+ by using "-accel kvm,kernel-irqchip=3Dsplit". In this case the ``virt``=
machine
+ will emulate the APLIC controller instead of using the APLIC controller =
from
+ the irqchip. See :ref:`riscv-aia` for more details on all available AIA
+ modes.
+
- aia-guests=3Dnnn
=20
The number of per-HART VS-level AIA IMSIC pages to be emulated for a gue=
st
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Sai Pavan Boddu <sai.pavan.boddu@amd.com>,
Michal Simek <michal.simek@amd.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 19/39] hw/riscv: Add Microblaze V generic board
Date: Thu, 19 Dec 2024 08:29:49 +1000
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From: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial configuration is going beyond what it is
configured by default because validation should be done on other
configurations too. That's why wire also additional uart16500, axi
ethernet(with axi dma).
GPIOs, i2c and qspi is also listed for completeness.
IRQ map is: (addr)
0 - timer (0x41c00000)
1 - uartlite (0x40600000)
2 - i2c (0x40800000)
3 - qspi (0x44a00000)
4 - uart16550 (0x44a10000)
5 - emaclite (0x40e00000)
6 - timer2 (0x41c10000)
7 - axi emac (0x40c00000)
8 - axi dma (0x41e00000)
9 - axi dma
10 - gpio (0x40000000)
11 - gpio2 (0x40010000)
12 - gpio3 (0x40020000)
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 6 +
docs/system/riscv/microblaze-v-generic.rst | 42 +++++
docs/system/target-riscv.rst | 1 +
hw/riscv/microblaze-v-generic.c | 184 +++++++++++++++++++++
hw/riscv/Kconfig | 8 +
hw/riscv/meson.build | 1 +
6 files changed, 242 insertions(+)
create mode 100644 docs/system/riscv/microblaze-v-generic.rst
create mode 100644 hw/riscv/microblaze-v-generic.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 822f34344b..27c21cd578 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1625,6 +1625,12 @@ F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
=20
+AMD Microblaze-V Generic Board
+M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
+S: Maintained
+F: hw/riscv/microblaze-v-generic.c
+F: docs/system/riscv/microblaze-v-generic.rst
+
RX Machines
-----------
rx-gdbsim
diff --git a/docs/system/riscv/microblaze-v-generic.rst b/docs/system/riscv=
/microblaze-v-generic.rst
new file mode 100644
index 0000000000..5606f88d57
--- /dev/null
+++ b/docs/system/riscv/microblaze-v-generic.rst
@@ -0,0 +1,42 @@
+Microblaze-V generic board (``amd-microblaze-v-generic``)
+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D
+The AMD MicroBlaze=E2=84=A2 V processor is a soft-core RISC-V processor IP=
for AMD
+adaptive SoCs and FPGAs. The MicroBlaze=E2=84=A2 V processor is based on t=
he 32-bit (or
+64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
+compatible with the classic MicroBlaze=E2=84=A2 V processor (i.e it is a d=
rop in
+replacement for the classic MicroBlaze=E2=84=A2 processor in existing RTL =
designs).
+More information can be found in below document.
+
+https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-A=
rchitecture
+
+The MicroBlaze=E2=84=A2 V generic board in QEMU has following supported de=
vices:
+
+ - timer
+ - uartlite
+ - uart16550
+ - emaclite
+ - timer2
+ - axi emac
+ - axi dma
+
+The MicroBlaze=E2=84=A2 V core in QEMU has the following configuration:
+
+ - RV32I base integer instruction set
+ - "Zicsr" Control and Status register instructions
+ - "Zifencei" instruction-fetch
+ - Extensions: m, a, f, c
+
+Running
+"""""""
+Below is an example command line for launching mainline U-boot
+(xilinx_mbv32_defconfig) on the Microblaze-V generic board.
+
+.. code-block:: bash
+
+ $ qemu-system-riscv32 -M amd-microblaze-v-generic \
+ -display none \
+ -device loader,addr=3D0x80000000,file=3Du-boot-spl.bin,cpu-num=3D0 \
+ -device loader,addr=3D0x80200000,file=3Du-boot.img \
+ -serial mon:stdio \
+ -device loader,addr=3D0x83000000,file=3Dsystem.dtb \
+ -m 2g
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index ba195f1518..95457af130 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -66,6 +66,7 @@ undocumented; you can get a complete list by running
.. toctree::
:maxdepth: 1
=20
+ riscv/microblaze-v-generic
riscv/microchip-icicle-kit
riscv/shakti-c
riscv/sifive_u
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi=
c.c
new file mode 100644
index 0000000000..427e3baca7
--- /dev/null
+++ b/hw/riscv/microblaze-v-generic.c
@@ -0,0 +1,184 @@
+/*
+ * QEMU model of Microblaze V generic board.
+ *
+ * based on hw/microblaze/petalogix_ml605_mmu.c
+ *
+ * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (c) 2011 PetaLogix
+ * Copyright (c) 2009 Edgar E. Iglesias.
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com
+ * and by Michal Simek <michal.simek@amd.com>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "net/net.h"
+#include "hw/boards.h"
+#include "hw/char/serial-mm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/xilinx_uartlite.h"
+#include "hw/misc/unimp.h"
+
+#define LMB_BRAM_SIZE (128 * KiB)
+#define MEMORY_BASEADDR 0x80000000
+#define INTC_BASEADDR 0x41200000
+#define TIMER_BASEADDR 0x41c00000
+#define TIMER_BASEADDR2 0x41c10000
+#define UARTLITE_BASEADDR 0x40600000
+#define ETHLITE_BASEADDR 0x40e00000
+#define UART16550_BASEADDR 0x44a10000
+#define AXIENET_BASEADDR 0x40c00000
+#define AXIDMA_BASEADDR 0x41e00000
+#define GPIO_BASEADDR 0x40000000
+#define GPIO_BASEADDR2 0x40010000
+#define GPIO_BASEADDR3 0x40020000
+#define I2C_BASEADDR 0x40800000
+#define QSPI_BASEADDR 0x44a00000
+
+#define TIMER_IRQ 0
+#define UARTLITE_IRQ 1
+#define UART16550_IRQ 4
+#define ETHLITE_IRQ 5
+#define TIMER_IRQ2 6
+#define AXIENET_IRQ 7
+#define AXIDMA_IRQ1 8
+#define AXIDMA_IRQ0 9
+
+static void mb_v_generic_init(MachineState *machine)
+{
+ ram_addr_t ram_size =3D machine->ram_size;
+ DeviceState *dev, *dma, *eth0;
+ Object *ds, *cs;
+ int i;
+ RISCVCPU *cpu;
+ hwaddr ddr_base =3D MEMORY_BASEADDR;
+ MemoryRegion *phys_lmb_bram =3D g_new(MemoryRegion, 1);
+ MemoryRegion *phys_ram =3D g_new(MemoryRegion, 1);
+ qemu_irq irq[32];
+ MemoryRegion *sysmem =3D get_system_memory();
+
+ cpu =3D RISCV_CPU(object_new(machine->cpu_type));
+ object_property_set_bool(OBJECT(cpu), "h", false, NULL);
+ object_property_set_bool(OBJECT(cpu), "d", false, NULL);
+ qdev_realize(DEVICE(cpu), NULL, &error_abort);
+ /* Attach emulated BRAM through the LMB. */
+ memory_region_init_ram(phys_lmb_bram, NULL,
+ "mb_v.lmb_bram", LMB_BRAM_SIZE,
+ &error_fatal);
+ memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
+
+ memory_region_init_ram(phys_ram, NULL, "mb_v.ram",
+ ram_size, &error_fatal);
+ memory_region_add_subregion(sysmem, ddr_base, phys_ram);
+
+ dev =3D qdev_new("xlnx.xps-intc");
+ qdev_prop_set_uint32(dev, "kind-of-intr",
+ 1 << UARTLITE_IRQ);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+ qdev_get_gpio_in(DEVICE(cpu), 11));
+ for (i =3D 0; i < 32; i++) {
+ irq[i] =3D qdev_get_gpio_in(dev, i);
+ }
+
+ /* Uartlite */
+ dev =3D qdev_new(TYPE_XILINX_UARTLITE);
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
+
+ /* Full uart */
+ serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,
+ irq[UART16550_IRQ], 115200, serial_hd(1),
+ DEVICE_LITTLE_ENDIAN);
+
+ /* 2 timers at irq 0 @ 100 Mhz. */
+ dev =3D qdev_new("xlnx.xps-timer");
+ qdev_prop_set_uint32(dev, "one-timer-only", 0);
+ qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
+
+ /* 2 timers at irq 3 @ 100 Mhz. */
+ dev =3D qdev_new("xlnx.xps-timer");
+ qdev_prop_set_uint32(dev, "one-timer-only", 0);
+ qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);
+
+ /* Emaclite */
+ dev =3D qdev_new("xlnx.xps-ethernetlite");
+ qemu_configure_nic_device(dev, true, NULL);
+ qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
+ qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
+
+ /* axi ethernet and dma initialization. */
+ eth0 =3D qdev_new("xlnx.axi-ethernet");
+ dma =3D qdev_new("xlnx.axi-dma");
+
+ /* FIXME: attach to the sysbus instead */
+ object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth=
0));
+ object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma=
));
+
+ ds =3D object_property_get_link(OBJECT(dma),
+ "axistream-connected-target", NULL);
+ cs =3D object_property_get_link(OBJECT(dma),
+ "axistream-control-connected-target", NU=
LL);
+ qemu_configure_nic_device(eth0, true, NULL);
+ qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
+ qdev_prop_set_uint32(eth0, "txmem", 0x1000);
+ object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
+ &error_abort);
+ object_property_set_link(OBJECT(eth0), "axistream-control-connected", =
cs,
+ &error_abort);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
+
+ ds =3D object_property_get_link(OBJECT(eth0),
+ "axistream-connected-target", NULL);
+ cs =3D object_property_get_link(OBJECT(eth0),
+ "axistream-control-connected-target", NU=
LL);
+ qdev_prop_set_uint32(dma, "freqhz", 100000000);
+ object_property_set_link(OBJECT(dma), "axistream-connected", ds,
+ &error_abort);
+ object_property_set_link(OBJECT(dma), "axistream-control-connected", c=
s,
+ &error_abort);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
+
+ /* unimplemented devices */
+ create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
+ create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);
+ create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);
+ create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);
+ create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);
+}
+
+static void mb_v_generic_machine_init(MachineClass *mc)
+{
+ mc->desc =3D "AMD Microblaze-V generic platform";
+ mc->init =3D mb_v_generic_init;
+ mc->min_cpus =3D 1;
+ mc->max_cpus =3D 1;
+ mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE;
+ mc->default_cpus =3D 1;
+}
+
+DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2e88467c4a..e6a0ac1fa1 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -25,6 +25,14 @@ config MICROCHIP_PFSOC
select SIFIVE_PLIC
select UNIMP
=20
+config MICROBLAZE_V
+ bool
+ default y
+ depends on RISCV32 || RISCV64
+ select XILINX
+ select XILINX_AXI
+ select XILINX_ETHLITE
+
config OPENTITAN
bool
default y
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 3be13d7774..3c7e083aca 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -11,5 +11,6 @@ riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.=
c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs=
oc.c'))
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', '=
riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
+riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen=
eric.c'))
=20
hw_arch +=3D {'riscv': riscv_ss}
--=20
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Sunil V L <sunilvl@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 20/39] qtest: allow SPCR acpi table changes
Date: Thu, 19 Dec 2024 08:29:50 +1000
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---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios=
-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/SPCR",
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Sunil V L <sunilvl@ventanamicro.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
Alistair Francis <alistair.francis@wdc.com>, Bibo Mao <maobibo@loongson.cn>
Subject: [PULL 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table
revision 4 format
Date: Thu, 19 Dec 2024 08:29:51 +1000
Message-ID: <20241218223010.1931245-22-alistair.francis@wdc.com>
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From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/se=
rial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20241028015744.624943-3-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/acpi/acpi-defs.h | 7 +++++--
include/hw/acpi/aml-build.h | 2 +-
hw/acpi/aml-build.c | 20 ++++++++++++++++----
hw/arm/virt-acpi-build.c | 8 ++++++--
hw/loongarch/acpi-build.c | 6 +++++-
hw/riscv/virt-acpi-build.c | 12 +++++++++---
6 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 0e6e82b339..2e6e341998 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -112,7 +112,6 @@ typedef struct AcpiSpcrData {
uint8_t flow_control;
uint8_t terminal_type;
uint8_t language;
- uint8_t reserved1;
uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
uint8_t pci_bus;
@@ -120,7 +119,11 @@ typedef struct AcpiSpcrData {
uint8_t pci_function;
uint32_t pci_flags;
uint8_t pci_segment;
- uint32_t reserved2;
+ uint32_t uart_clk_freq;
+ uint32_t precise_baudrate;
+ uint32_t namespace_string_length;
+ uint32_t namespace_string_offset;
+ char namespace_string[];
} AcpiSpcrData;
=20
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 4fd5da49e7..c18f681342 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -507,5 +507,5 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker,=
GArray *tcpalog,
=20
void build_spcr(GArray *table_data, BIOSLinker *linker,
const AcpiSpcrData *f, const uint8_t rev,
- const char *oem_id, const char *oem_table_id);
+ const char *oem_id, const char *oem_table_id, const char *=
name);
#endif
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 72282b173e..e4d58d7051 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -2078,7 +2078,7 @@ static void build_processor_hierarchy_node(GArray *tb=
l, uint32_t flags,
=20
void build_spcr(GArray *table_data, BIOSLinker *linker,
const AcpiSpcrData *f, const uint8_t rev,
- const char *oem_id, const char *oem_table_id)
+ const char *oem_id, const char *oem_table_id, const char *=
name)
{
AcpiTable table =3D { .sig =3D "SPCR", .rev =3D rev, .oem_id =3D oem_i=
d,
.oem_table_id =3D oem_table_id };
@@ -2124,9 +2124,21 @@ void build_spcr(GArray *table_data, BIOSLinker *link=
er,
build_append_int_noprefix(table_data, f->pci_flags, 4);
/* PCI Segment */
build_append_int_noprefix(table_data, f->pci_segment, 1);
- /* Reserved */
- build_append_int_noprefix(table_data, 0, 4);
-
+ if (rev < 4) {
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ } else {
+ /* UartClkFreq */
+ build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
+ /* PreciseBaudrate */
+ build_append_int_noprefix(table_data, f->precise_baudrate, 4);
+ /* NameSpaceStringLength */
+ build_append_int_noprefix(table_data, f->namespace_string_length, =
2);
+ /* NameSpaceStringOffset */
+ build_append_int_noprefix(table_data, f->namespace_string_offset, =
2);
+ /* NamespaceString[] */
+ g_array_append_vals(table_data, name, f->namespace_string_length);
+ }
acpi_table_end(linker, &table);
}
/*
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 620992c92c..e92d3bddc8 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -463,8 +463,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, Vir=
tMachineState *vms)
.pci_flags =3D 0,
.pci_segment =3D 0,
};
-
- build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table=
_id);
+ /*
+ * Passing NULL as the SPCR Table for Revision 2 doesn't support
+ * NameSpaceString.
+ */
+ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table=
_id,
+ NULL);
}
=20
/*
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index 50709bda0f..4e04f7b6c1 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -276,8 +276,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, Mac=
hineState *machine)
};
=20
lvms =3D LOONGARCH_VIRT_MACHINE(machine);
+ /*
+ * Passing NULL as the SPCR Table for Revision 2 doesn't support
+ * NameSpaceString.
+ */
build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
- lvms->oem_table_id);
+ lvms->oem_table_id, NULL);
}
=20
typedef
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 36d6a3a412..68ef15acac 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -200,14 +200,15 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uar=
t_memmap,
=20
/*
* Serial Port Console Redirection Table (SPCR)
- * Rev: 1.07
+ * Rev: 1.10
*/
=20
static void
spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
{
+ const char name[] =3D ".";
AcpiSpcrData serial =3D {
- .interface_type =3D 0, /* 16550 compatible */
+ .interface_type =3D 0x12, /* 16550 compatible */
.base_addr.id =3D AML_AS_SYSTEM_MEMORY,
.base_addr.width =3D 32,
.base_addr.offset =3D 0,
@@ -229,9 +230,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RIS=
CVVirtState *s)
.pci_function =3D 0,
.pci_flags =3D 0,
.pci_segment =3D 0,
+ .uart_clk_freq =3D 0,
+ .precise_baudrate =3D 0,
+ .namespace_string_length =3D sizeof(name),
+ .namespace_string_offset =3D 88,
};
=20
- build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
+ build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
+ name);
}
=20
/* RHCT Node[N] starts at offset 56 */
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
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Sunil V L <sunilvl@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden
reference for RISC-V
Date: Thu, 19 Dec 2024 08:29:52 +1000
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From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/se=
rial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Diffs from iasl:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Wed Aug 28 18:28:19 2=
024
+ * Disassembly of /tmp/aml-MN0NS2, Wed Aug 28 18:28:19 2024
*
* ACPI Data Table [SPCR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "SPCR" [Serial Port Cons=
ole Redirection table]
-[004h 0004 4] Table Length : 00000050
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : B9
+[004h 0004 4] Table Length : 0000005A
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 13
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 1] Interface Type : 00
+[024h 0036 1] Interface Type : 12
[025h 0037 3] Reserved : 000000
[028h 0040 12] Serial Port Register : [Generic Address Structure]
[028h 0040 1] Space ID : 00 [SystemMemory]
[029h 0041 1] Bit Width : 20
[02Ah 0042 1] Bit Offset : 00
[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
[02Ch 0044 8] Address : 0000000010000000
[034h 0052 1] Interrupt Type : 10
[035h 0053 1] PCAT-compatible IRQ : 00
[036h 0054 4] Interrupt : 0000000A
[03Ah 0058 1] Baud Rate : 07
[03Bh 0059 1] Parity : 00
[03Ch 0060 1] Stop Bits : 01
[03Dh 0061 1] Flow Control : 00
[03Eh 0062 1] Terminal Type : 00
[04Ch 0076 1] Reserved : 00
[040h 0064 2] PCI Device ID : FFFF
[042h 0066 2] PCI Vendor ID : FFFF
[044h 0068 1] PCI Bus : 00
[045h 0069 1] PCI Device : 00
[046h 0070 1] PCI Function : 00
[047h 0071 4] PCI Flags : 00000000
[04Bh 0075 1] PCI Segment : 00
-[04Ch 0076 4] Reserved : 00000000
+[04Ch 0076 004h] Uart Clock Freq : 00000000
+[050h 0080 004h] Precise Baud rate : 00000000
+[054h 0084 002h] NameSpaceStringLength : 0002
+[056h 0086 002h] NameSpaceStringOffset : 0058
+[058h 0088 002h] NamespaceString : "."
-Raw Table Data: Length 80 (0x50)
+Raw Table Data: Length 90 (0x5A)
- 0000: 53 50 43 52 50 00 00 00 02 B9 42 4F 43 48 53 20 // SPCRP.....BO=
CHS
+ 0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20 // SPCRZ.....BO=
CHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....=
BXPC
- 0020: 01 00 00 00 00 00 00 00 00 20 00 01 00 00 00 10 // ......... ..=
....
+ 0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10 // ......... ..=
....
0030: 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 00 03 // ............=
....
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ............=
....
+ 0050: 00 00 00 00 02 00 58 00 2E 00 // ......X...
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Message-ID: <20241028015744.624943-4-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios=
-tables-test-allowed-diff.h
index aae973048a..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/SPCR",
diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/vi=
rt/SPCR
index 4da9daf65f..09617f8793 100644
Binary files a/tests/data/acpi/riscv64/virt/SPCR and b/tests/data/acpi/risc=
v64/virt/SPCR differ
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface
Date: Thu, 19 Dec 2024 08:29:53 +1000
Message-ID: <20241218223010.1931245-24-alistair.francis@wdc.com>
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 27c21cd578..3bba2efbc1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -324,8 +324,10 @@ S: Supported
F: configs/targets/riscv*
F: docs/system/target-riscv.rst
F: target/riscv/
+F: hw/char/riscv_htif.c
F: hw/riscv/
F: hw/intc/riscv*
+F: include/hw/char/riscv_htif.h
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 24/39] hw/char/riscv_htif: Explicit little-endian
implementation
Date: Thu, 19 Dec 2024 08:29:54 +1000
Message-ID: <20241218223010.1931245-25-alistair.francis@wdc.com>
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.
In that case tswap64() is equivalent to le64_to_cpu(), as in
"convert this 64-bit little-endian value into host cpu order".
Replace to simplify.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 0345088e8b..3f84d8d673 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -29,7 +29,7 @@
#include "qemu/timer.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
-#include "exec/tswap.h"
+#include "qemu/bswap.h"
#include "sysemu/dma.h"
#include "sysemu/runstate.h"
=20
@@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, ui=
nt64_t val_written)
} else {
uint64_t syscall[8];
cpu_physical_memory_read(payload, syscall, sizeof(syscall)=
);
- if (tswap64(syscall[0]) =3D=3D PK_SYS_WRITE &&
- tswap64(syscall[1]) =3D=3D HTIF_DEV_CONSOLE &&
- tswap64(syscall[3]) =3D=3D HTIF_CONSOLE_CMD_PUTC) {
+ if (le64_to_cpu(syscall[0]) =3D=3D PK_SYS_WRITE &&
+ le64_to_cpu(syscall[1]) =3D=3D HTIF_DEV_CONSOLE &&
+ le64_to_cpu(syscall[3]) =3D=3D HTIF_CONSOLE_CMD_PUTC) {
uint8_t ch;
- cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
+ cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch,=
1);
/*
* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks
@@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps htif_mm_ops =3D {
.read =3D htif_mm_read,
.write =3D htif_mm_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
};
=20
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect
32-bit accesses
Date: Thu, 19 Dec 2024 08:29:55 +1000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-4-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/riscv_htif.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index 3f84d8d673..db69b5e3ca 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops =3D {
.read =3D htif_mm_read,
.write =3D htif_mm_write,
.endianness =3D DEVICE_LITTLE_ENDIAN,
+ .impl =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
};
=20
HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Jim Shu <jim.shu@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit
system.
Date: Thu, 19 Dec 2024 08:29:56 +1000
Message-ID: <20241218223010.1931245-27-alistair.francis@wdc.com>
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From: Jim Shu <jim.shu@sifive.com>
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-2-jim.shu@sifive.com>
[ Changes by AF
- Store fdt_load_addr_hi32 in the reset vector
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 2 +-
hw/riscv/boot.c | 14 +++++++++-----
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifive_u.c | 8 +++++---
hw/riscv/spike.c | 4 ++--
hw/riscv/virt.c | 2 +-
6 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f778b560de..34a80c5ff4 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -49,7 +49,7 @@ target_ulong riscv_load_kernel(MachineState *machine,
bool load_initrd,
symbol_fn_t sym_cb);
uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
- MachineState *ms);
+ MachineState *ms, RISCVHartArrayState *har=
ts);
void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState =
*harts,
hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2e319168db..d36d3a7104 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -293,7 +293,7 @@ out:
* The FDT is fdt_packed() during the calculation.
*/
uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
- MachineState *ms)
+ MachineState *ms, RISCVHartArrayState *har=
ts)
{
int ret =3D fdt_pack(ms->fdt);
hwaddr dram_end, temp;
@@ -317,11 +317,15 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwa=
ddr dram_size,
=20
/*
* We should put fdt as far as possible to avoid kernel/initrd overwri=
ting
- * its content. But it should be addressable by 32 bit system as well.
- * Thus, put it at an 2MB aligned address that less than fdt size from=
the
- * end of dram or 3GB whichever is lesser.
+ * its content. But it should be addressable by 32 bit system as well =
in RV32.
+ * Thus, put it near to the end of dram in RV64, and put it near to th=
e end
+ * of dram or 3GB whichever is lesser in RV32.
*/
- temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_e=
nd;
+ if (!riscv_is_32bit(harts)) {
+ temp =3D dram_end;
+ } else {
+ temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr=
am_end;
+ }
=20
return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
}
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index f9a3b43d2e..ba8b0a2c26 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -519,7 +519,7 @@ static void microchip_icicle_kit_machine_init(MachineSt=
ate *machine)
bool kernel_as_payload =3D false;
target_ulong firmware_end_addr, kernel_start_addr;
uint64_t kernel_entry;
- uint32_t fdt_load_addr;
+ uint64_t fdt_load_addr;
DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0);
=20
/* Sanity check on RAM size */
@@ -625,7 +625,7 @@ static void microchip_icicle_kit_machine_init(MachineSt=
ate *machine)
/* Compute the fdt load address in dram */
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR=
AM_LO].base,
memmap[MICROCHIP_PFSOC_DRAM=
_LO].size,
- machine);
+ machine, &s->soc.u_cpus);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* Load the reset vector */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 124ffd4842..fd59124500 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -518,8 +518,9 @@ static void sifive_u_machine_init(MachineState *machine)
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name;
uint32_t start_addr_hi32 =3D 0x00000000;
+ uint32_t fdt_load_addr_hi32 =3D 0x00000000;
int i;
- uint32_t fdt_load_addr;
+ uint64_t fdt_load_addr;
uint64_t kernel_entry;
DriveInfo *dinfo;
BlockBackend *blk;
@@ -606,11 +607,12 @@ static void sifive_u_machine_init(MachineState *machi=
ne)
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].bas=
e,
memmap[SIFIVE_U_DEV_DRAM].size,
- machine);
+ machine, &s->soc.u_cpus);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 =3D (uint64_t)start_addr >> 32;
+ fdt_load_addr_hi32 =3D fdt_load_addr >> 32;
}
=20
/* reset vector */
@@ -625,7 +627,7 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr, /* start: .dword */
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
- 0x00000000,
+ fdt_load_addr_hi32,
0x00000000,
/* fw_dyn: */
};
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index fceb91d946..acd7ab1ae1 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -201,7 +201,7 @@ static void spike_board_init(MachineState *machine)
hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base;
target_ulong kernel_start_addr;
char *firmware_name;
- uint32_t fdt_load_addr;
+ uint64_t fdt_load_addr;
uint64_t kernel_entry;
char *soc_name;
int i, base_hartid, hart_count;
@@ -317,7 +317,7 @@ static void spike_board_init(MachineState *machine)
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
memmap[SPIKE_DRAM].size,
- machine);
+ machine, &s->soc[0]);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* load the reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 43a1c86c33..98da79a5be 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1492,7 +1492,7 @@ static void virt_machine_done(Notifier *notifier, voi=
d *data)
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
memmap[VIRT_DRAM].size,
- machine);
+ machine, &s->soc[0]);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* load the reset vector */
--=20
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Wed, 18 Dec 2024 14:31:37 -0800 (PST)
From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Jim Shu <jim.shu@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo
Date: Thu, 19 Dec 2024 08:29:57 +1000
Message-ID: <20241218223010.1931245-28-alistair.francis@wdc.com>
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From: Jim Shu <jim.shu@sifive.com>
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 25 ++++++++++-----
hw/riscv/boot.c | 65 ++++++++++++++++++++++----------------
hw/riscv/microchip_pfsoc.c | 11 ++++---
hw/riscv/opentitan.c | 4 ++-
hw/riscv/sifive_e.c | 4 ++-
hw/riscv/sifive_u.c | 12 ++++---
hw/riscv/spike.c | 12 ++++---
hw/riscv/virt.c | 13 +++++---
8 files changed, 90 insertions(+), 56 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 34a80c5ff4..06b51ed086 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -27,11 +27,20 @@
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
=20
+typedef struct RISCVBootInfo {
+ ssize_t kernel_size;
+ hwaddr image_low_addr;
+ hwaddr image_high_addr;
+
+ bool is_32bit;
+} RISCVBootInfo;
+
bool riscv_is_32bit(RISCVHartArrayState *harts);
=20
char *riscv_plic_hart_config_string(int hart_count);
=20
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
+target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firm=
ware,
@@ -43,13 +52,13 @@ char *riscv_find_firmware(const char *firmware_filename,
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
-target_ulong riscv_load_kernel(MachineState *machine,
- RISCVHartArrayState *harts,
- target_ulong firmware_end_addr,
- bool load_initrd,
- symbol_fn_t sym_cb);
-uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
- MachineState *ms, RISCVHartArrayState *har=
ts);
+void riscv_load_kernel(MachineState *machine,
+ RISCVBootInfo *info,
+ target_ulong kernel_start_addr,
+ bool load_initrd,
+ symbol_fn_t sym_cb);
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
+ MachineState *ms, RISCVBootInfo *info);
void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState =
*harts,
hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d36d3a7104..81d27f935e 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -67,9 +67,15 @@ char *riscv_plic_hart_config_string(int hart_count)
return g_strjoinv(",", (char **)vals);
}
=20
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
+{
+ info->kernel_size =3D 0;
+ info->is_32bit =3D riscv_is_32bit(harts);
+}
+
+target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
target_ulong firmware_end_addr) {
- if (riscv_is_32bit(harts)) {
+ if (info->is_32bit) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
} else {
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
@@ -175,7 +181,7 @@ target_ulong riscv_load_firmware(const char *firmware_f=
ilename,
exit(1);
}
=20
-static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
{
const char *filename =3D machine->initrd_filename;
uint64_t mem_size =3D machine->ram_size;
@@ -196,7 +202,7 @@ static void riscv_load_initrd(MachineState *machine, ui=
nt64_t kernel_entry)
* halfway into RAM, and for boards with 1GB of RAM or more we put
* the initrd at 512MB.
*/
- start =3D kernel_entry + MIN(mem_size / 2, 512 * MiB);
+ start =3D info->image_low_addr + MIN(mem_size / 2, 512 * MiB);
=20
size =3D load_ramdisk(filename, start, mem_size - start);
if (size =3D=3D -1) {
@@ -215,14 +221,14 @@ static void riscv_load_initrd(MachineState *machine, =
uint64_t kernel_entry)
}
}
=20
-target_ulong riscv_load_kernel(MachineState *machine,
- RISCVHartArrayState *harts,
- target_ulong kernel_start_addr,
- bool load_initrd,
- symbol_fn_t sym_cb)
+void riscv_load_kernel(MachineState *machine,
+ RISCVBootInfo *info,
+ target_ulong kernel_start_addr,
+ bool load_initrd,
+ symbol_fn_t sym_cb)
{
const char *kernel_filename =3D machine->kernel_filename;
- uint64_t kernel_load_base, kernel_entry;
+ ssize_t kernel_size;
void *fdt =3D machine->fdt;
=20
g_assert(kernel_filename !=3D NULL);
@@ -234,21 +240,28 @@ target_ulong riscv_load_kernel(MachineState *machine,
* the (expected) load address load address. This allows kernels to ha=
ve
* separate SBI and ELF entry points (used by FreeBSD, for example).
*/
- if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
- NULL, &kernel_load_base, NULL, NULL, 0,
- EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
- kernel_entry =3D kernel_load_base;
+ kernel_size =3D load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NU=
LL,
+ &info->image_low_addr, &info->image_hig=
h_addr,
+ NULL, 0, EM_RISCV, 1, 0, NULL, true, sy=
m_cb);
+ if (kernel_size > 0) {
+ info->kernel_size =3D kernel_size;
goto out;
}
=20
- if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
- NULL, NULL, NULL) > 0) {
+ kernel_size =3D load_uimage_as(kernel_filename, &info->image_low_addr,
+ NULL, NULL, NULL, NULL, NULL);
+ if (kernel_size > 0) {
+ info->kernel_size =3D kernel_size;
+ info->image_high_addr =3D info->image_low_addr + kernel_size;
goto out;
}
=20
- if (load_image_targphys_as(kernel_filename, kernel_start_addr,
- current_machine->ram_size, NULL) > 0) {
- kernel_entry =3D kernel_start_addr;
+ kernel_size =3D load_image_targphys_as(kernel_filename, kernel_start_a=
ddr,
+ current_machine->ram_size, NULL);
+ if (kernel_size > 0) {
+ info->kernel_size =3D kernel_size;
+ info->image_low_addr =3D kernel_start_addr;
+ info->image_high_addr =3D info->image_low_addr + kernel_size;
goto out;
}
=20
@@ -257,23 +270,21 @@ target_ulong riscv_load_kernel(MachineState *machine,
=20
out:
/*
- * For 32 bit CPUs 'kernel_entry' can be sign-extended by
+ * For 32 bit CPUs 'image_low_addr' can be sign-extended by
* load_elf_ram_sym().
*/
- if (riscv_is_32bit(harts)) {
- kernel_entry =3D extract64(kernel_entry, 0, 32);
+ if (info->is_32bit) {
+ info->image_low_addr =3D extract64(info->image_low_addr, 0, 32);
}
=20
if (load_initrd && machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
+ riscv_load_initrd(machine, info);
}
=20
if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
machine->kernel_cmdline);
}
-
- return kernel_entry;
}
=20
/*
@@ -293,7 +304,7 @@ out:
* The FDT is fdt_packed() during the calculation.
*/
uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
- MachineState *ms, RISCVHartArrayState *har=
ts)
+ MachineState *ms, RISCVBootInfo *info)
{
int ret =3D fdt_pack(ms->fdt);
hwaddr dram_end, temp;
@@ -321,7 +332,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd=
r dram_size,
* Thus, put it near to the end of dram in RV64, and put it near to th=
e end
* of dram or 3GB whichever is lesser in RV32.
*/
- if (!riscv_is_32bit(harts)) {
+ if (!info->is_32bit) {
temp =3D dram_end;
} else {
temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr=
am_end;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index ba8b0a2c26..a302965b6d 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -521,6 +521,7 @@ static void microchip_icicle_kit_machine_init(MachineSt=
ate *machine)
uint64_t kernel_entry;
uint64_t fdt_load_addr;
DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0);
+ RISCVBootInfo boot_info;
=20
/* Sanity check on RAM size */
if (machine->ram_size < mc->default_ram_size) {
@@ -615,17 +616,19 @@ static void microchip_icicle_kit_machine_init(Machine=
State *machine)
firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n=
ame,
&firmware_load_addr, =
NULL);
=20
+ riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (kernel_as_payload) {
- kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+ kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr=
);
=20
- kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus,
- kernel_start_addr, true, NULL);
+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+ true, NULL);
+ kernel_entry =3D boot_info.image_low_addr;
=20
/* Compute the fdt load address in dram */
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR=
AM_LO].base,
memmap[MICROCHIP_PFSOC_DRAM=
_LO].size,
- machine, &s->soc.u_cpus);
+ machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* Load the reset vector */
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 8ce85ea9f7..87ad9c8f34 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -81,6 +81,7 @@ static void opentitan_machine_init(MachineState *machine)
OpenTitanState *s =3D OPENTITAN_MACHINE(machine);
const MemMapEntry *memmap =3D ibex_memmap;
MemoryRegion *sys_mem =3D get_system_memory();
+ RISCVBootInfo boot_info;
=20
if (machine->ram_size !=3D mc->default_ram_size) {
char *sz =3D size_to_str(mc->default_ram_size);
@@ -102,8 +103,9 @@ static void opentitan_machine_init(MachineState *machin=
e)
riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
}
=20
+ riscv_boot_info_init(&boot_info, &s->soc.cpus);
if (machine->kernel_filename) {
- riscv_load_kernel(machine, &s->soc.cpus,
+ riscv_load_kernel(machine, &boot_info,
memmap[IBEX_DEV_RAM].base,
false, NULL);
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 5a1959f2a9..ebcd33ab95 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -78,6 +78,7 @@ static void sifive_e_machine_init(MachineState *machine)
SiFiveEState *s =3D RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem =3D get_system_memory();
int i;
+ RISCVBootInfo boot_info;
=20
if (machine->ram_size !=3D mc->default_ram_size) {
char *sz =3D size_to_str(mc->default_ram_size);
@@ -113,8 +114,9 @@ static void sifive_e_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_E_DEV_MROM].base, &address_space_m=
emory);
=20
+ riscv_boot_info_init(&boot_info, &s->soc.cpus);
if (machine->kernel_filename) {
- riscv_load_kernel(machine, &s->soc.cpus,
+ riscv_load_kernel(machine, &boot_info,
memmap[SIFIVE_E_DEV_DTIM].base,
false, NULL);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fd59124500..6270e1ccec 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -526,6 +526,7 @@ static void sifive_u_machine_init(MachineState *machine)
BlockBackend *blk;
DeviceState *flash_dev, *sd_dev, *card_dev;
qemu_irq flash_cs, sd_cs;
+ RISCVBootInfo boot_info;
=20
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_=
SOC);
@@ -591,12 +592,13 @@ static void sifive_u_machine_init(MachineState *machi=
ne)
firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n=
ame,
&start_addr, NULL);
=20
+ riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (machine->kernel_filename) {
- kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+ kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr=
);
-
- kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus,
- kernel_start_addr, true, NULL);
+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+ true, NULL);
+ kernel_entry =3D boot_info.image_low_addr;
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next m=
ode
@@ -607,7 +609,7 @@ static void sifive_u_machine_init(MachineState *machine)
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].bas=
e,
memmap[SIFIVE_U_DEV_DRAM].size,
- machine, &s->soc.u_cpus);
+ machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
if (!riscv_is_32bit(&s->soc.u_cpus)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index acd7ab1ae1..c3ad16d316 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -206,6 +206,7 @@ static void spike_board_init(MachineState *machine)
char *soc_name;
int i, base_hartid, hart_count;
bool htif_custom_base =3D false;
+ RISCVBootInfo boot_info;
=20
/* Check socket count limit */
if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@@ -300,13 +301,14 @@ static void spike_board_init(MachineState *machine)
create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
=20
/* Load kernel */
+ riscv_boot_info_init(&boot_info, &s->soc[0]);
if (machine->kernel_filename) {
- kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0],
+ kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr=
);
=20
- kernel_entry =3D riscv_load_kernel(machine, &s->soc[0],
- kernel_start_addr,
- true, htif_symbol_callback);
+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+ true, htif_symbol_callback);
+ kernel_entry =3D boot_info.image_low_addr;
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next m=
ode
@@ -317,7 +319,7 @@ static void spike_board_init(MachineState *machine)
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
memmap[SPIKE_DRAM].size,
- machine, &s->soc[0]);
+ machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* load the reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 98da79a5be..d2bfdec56a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1434,6 +1434,7 @@ static void virt_machine_done(Notifier *notifier, voi=
d *data)
uint64_t fdt_load_addr;
uint64_t kernel_entry =3D 0;
BlockBackend *pflash_blk0;
+ RISCVBootInfo boot_info;
=20
/*
* An user provided dtb must include everything, including
@@ -1482,17 +1483,19 @@ static void virt_machine_done(Notifier *notifier, v=
oid *data)
}
}
=20
+ riscv_boot_info_init(&boot_info, &s->soc[0]);
+
if (machine->kernel_filename && !kernel_entry) {
- kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0],
+ kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr=
);
-
- kernel_entry =3D riscv_load_kernel(machine, &s->soc[0],
- kernel_start_addr, true, NULL);
+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+ true, NULL);
+ kernel_entry =3D boot_info.image_low_addr;
}
=20
fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
memmap[VIRT_DRAM].size,
- machine, &s->soc[0]);
+ machine, &boot_info);
riscv_load_fdt(fdt_load_addr, machine->fdt);
=20
/* load the reset vector */
--=20
2.47.1
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Jim Shu <jim.shu@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or
initrd
Date: Thu, 19 Dec 2024 08:29:58 +1000
Message-ID: <20241218223010.1931245-29-alistair.francis@wdc.com>
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From: Jim Shu <jim.shu@sifive.com>
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-4-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 3 +++
hw/riscv/boot.c | 25 ++++++++++++++++++++++++-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 06b51ed086..7d59b2e6c6 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -32,6 +32,9 @@ typedef struct RISCVBootInfo {
hwaddr image_low_addr;
hwaddr image_high_addr;
=20
+ hwaddr initrd_start;
+ ssize_t initrd_size;
+
bool is_32bit;
} RISCVBootInfo;
=20
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 81d27f935e..bc8074fec8 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -70,6 +70,7 @@ char *riscv_plic_hart_config_string(int hart_count)
void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
{
info->kernel_size =3D 0;
+ info->initrd_size =3D 0;
info->is_32bit =3D riscv_is_32bit(harts);
}
=20
@@ -213,6 +214,9 @@ static void riscv_load_initrd(MachineState *machine, RI=
SCVBootInfo *info)
}
}
=20
+ info->initrd_start =3D start;
+ info->initrd_size =3D size;
+
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
if (fdt) {
end =3D start + size;
@@ -309,6 +313,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd=
r dram_size,
int ret =3D fdt_pack(ms->fdt);
hwaddr dram_end, temp;
int fdtsize;
+ uint64_t dtb_start, dtb_start_limit;
=20
/* Should only fail if we've built a corrupted tree */
g_assert(ret =3D=3D 0);
@@ -319,6 +324,17 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad=
dr dram_size,
exit(1);
}
=20
+ if (info->initrd_size) {
+ /* If initrd is successfully loaded, place DTB after it. */
+ dtb_start_limit =3D info->initrd_start + info->initrd_size;
+ } else if (info->kernel_size) {
+ /* If only kernel is successfully loaded, place DTB after it. */
+ dtb_start_limit =3D info->image_high_addr;
+ } else {
+ /* Otherwise, do not check DTB overlapping */
+ dtb_start_limit =3D 0;
+ }
+
/*
* A dram_size =3D=3D 0, usually from a MemMapEntry[].size element,
* means that the DRAM block goes all the way to ms->ram_size.
@@ -338,7 +354,14 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad=
dr dram_size,
temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr=
am_end;
}
=20
- return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+ dtb_start =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+
+ if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
+ error_report("No enough memory to place DTB after kernel/initrd");
+ exit(1);
+ }
+
+ return dtb_start;
}
=20
/*
--=20
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Subject: [PULL 29/39] target/riscv: Add svukte extension capability variable
Date: Thu, 19 Dec 2024 08:29:59 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-2-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..d8771ca641 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
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Frank Chang <frank.chang@sifive.com>, Jim Shu <jim.shu@sifive.com>,
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte
extension is enabled
Date: Thu, 19 Dec 2024 08:30:00 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-3-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 385a2c67c2..4b9f899217 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -785,6 +785,7 @@ typedef enum RISCVException {
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
+#define SENVCFG_UKTE BIT(8)
=20
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_LPE MENVCFG_LPE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9846770820..1936a6f32a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *e=
nv, int csrno,
mask |=3D SENVCFG_SSE;
}
=20
+ if (env_archcpu(env)->cfg.ext_svukte) {
+ mask |=3D SENVCFG_UKTE;
+ }
+
env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Fea.Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>, Jim Shu <jim.shu@sifive.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte
extension is enabled
Date: Thu, 19 Dec 2024 08:30:01 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-4-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4b9f899217..fe4e34c64a 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -604,6 +604,7 @@ typedef enum {
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTW 0x00200000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HUKTE 0x01000000
#define HSTATUS_VSXL 0x300000000
=20
#define HSTATUS32_WPRI 0xFF8FF87E
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1936a6f32a..b6fa8ae53f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env=
, int csrno,
static RISCVException write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
+ if (!env_archcpu(env)->cfg.ext_svukte) {
+ val =3D val & (~HSTATUS_HUKTE);
+ }
env->hstatus =3D val;
if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) !=
=3D 2) {
qemu_log_mask(LOG_UNIMP,
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Fea.Wang" <fea.wang@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Jim Shu <jim.shu@sifive.com>, Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 32/39] target/riscv: Check memory access to meet svukte rule
Date: Thu, 19 Dec 2024 08:30:02 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.
Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-5-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 45806f5ab0..750c0537ca 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -857,6 +857,55 @@ static int get_physical_address_pmp(CPURISCVState *env=
, int *prot, hwaddr addr,
return TRANSLATE_SUCCESS;
}
=20
+/* Returns 'true' if a svukte address check is needed */
+static bool do_svukte_check(CPURISCVState *env, bool first_stage,
+ int mode, bool virt)
+{
+ /* Svukte extension depends on Sv39. */
+ if (!(env_archcpu(env)->cfg.ext_svukte ||
+ !first_stage ||
+ VM_1_10_SV39 !=3D get_field(env->satp, SATP64_MODE))) {
+ return false;
+ }
+
+ /*
+ * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
+ * executing HLV/HLVX/HSV in U-mode.
+ * For other cases, check senvcfg.UKTE.
+ */
+ if (env->priv =3D=3D PRV_U && !env->virt_enabled && virt) {
+ if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
+ return false;
+ }
+ } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
+ return false;
+ }
+
+ /*
+ * Svukte extension is qualified only in U or VU-mode.
+ *
+ * Effective mode can be switched to U or VU-mode by:
+ * - M-mode + mstatus.MPRV=3D1 + mstatus.MPP=3DU-mode.
+ * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=3D0.
+ * - U-mode.
+ * - VU-mode.
+ * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=3D1.
+ */
+ if (mode !=3D PRV_U) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
+{
+ /* svukte extension excludes RV32 */
+ uint32_t sxlen =3D 32 * riscv_cpu_sxl(env);
+ uint64_t high_bit =3D addr & (1UL << (sxlen - 1));
+ return !high_bit;
+}
+
/*
* get_physical_address - get the physical address for this virtual address
*
@@ -894,6 +943,7 @@ static int get_physical_address(CPURISCVState *env, hwa=
ddr *physical,
MemTxResult res;
MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED;
int mode =3D mmuidx_priv(mmu_idx);
+ bool virt =3D mmuidx_2stage(mmu_idx);
bool use_background =3D false;
hwaddr ppn;
int napot_bits =3D 0;
@@ -901,6 +951,11 @@ static int get_physical_address(CPURISCVState *env, hw=
addr *physical,
bool is_sstack_idx =3D ((mmu_idx & MMU_IDX_SS_WRITE) =3D=3D MMU_IDX_SS=
_WRITE);
bool sstack_page =3D false;
=20
+ if (do_svukte_check(env, first_stage, mode, virt) &&
+ !check_svukte_addr(env, addr)) {
+ return TRANSLATE_FAIL;
+ }
+
/*
* Check if we should use the background registers for the two
* stage translation. We don't need to check if we actually need
--=20
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Frank Chang <frank.chang@sifive.com>, Jim Shu <jim.shu@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 33/39] target/riscv: Expose svukte ISA extension
Date: Thu, 19 Dec 2024 08:30:03 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66e00ed260..18f4d94b6e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -1663,6 +1664,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =
=3D {
=20
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D {
+ MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
DEFINE_PROP_END_OF_LIST(),
};
=20
--=20
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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
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Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 34/39] target/riscv: Check svukte is not enabled in RV32
Date: Thu, 19 Dec 2024 08:30:04 +1000
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From: "Fea.Wang" <fea.wang@sifive.com>
The spec explicitly says svukte doesn't support RV32. So check that it
is not enabled in RV32.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-7-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c221696..3b99c8c9e3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, =
Error **errp)
return;
}
=20
+ if (mcc->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) {
+ error_setg(errp, "svukte is not supported for RV32");
+ return;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
--=20
2.47.1
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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 35/39] target/riscv: Include missing headers in
'vector_internals.h'
Date: Thu, 19 Dec 2024 08:30:05 +1000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/vector_internals.h:36:12: error: call to undeclared function=
'FIELD_EX32'; ISO C99 and later do not support implicit function declarati=
ons [-Wimplicit-function-declaration]
36 | return FIELD_EX32(simd_data(desc), VDATA, NF);
| ^
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_internals.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal=
s.h
index 9e1e15b575..a11cc8366d 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -20,6 +20,7 @@
#define TARGET_RISCV_VECTOR_INTERNALS_H
=20
#include "qemu/bitops.h"
+#include "hw/registerfields.h"
#include "cpu.h"
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
--=20
2.47.1
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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
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Subject: [PULL 36/39] target/riscv: Include missing headers in 'internals.h'
Date: Thu, 19 Dec 2024 08:30:06 +1000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_=
S'
49 | ret =3D PRV_S;
| ^
target/riscv/internals.h:93:9: error: call to undeclared function 'env_ar=
chcpu'; ISO C99 and later do not support implicit function declarations [-W=
implicit-function-declaration]
93 | if (env_archcpu(env)->cfg.ext_zfinx) {
| ^
target/riscv/internals.h:101:15: error: unknown type name 'float32'; did =
you mean 'float'?
101 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t=
f)
| ^~~~~~~
| float
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ddbdee885b..76934eaa7b 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -19,7 +19,10 @@
#ifndef RISCV_CPU_INTERNALS_H
#define RISCV_CPU_INTERNALS_H
=20
+#include "exec/cpu-common.h"
#include "hw/registerfields.h"
+#include "fpu/softfloat-types.h"
+#include "target/riscv/cpu_bits.h"
=20
/*
* The current MMU Modes are:
--=20
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 37/39] target/riscv/tcg: hide warn for named feats when
disabling via priv_ver
Date: Thu, 19 Dec 2024 08:30:07 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to disable zic64b
manually in riscv_cpu_update_named_features().
This solution won't scale well when adding more named features, and can
eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().
Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
disabling a named feature. This will accomplish the same thing we're
doing today while avoiding having two points where we're disabling
exts via priv_ver mismatch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241113171755.978109-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 3b99c8c9e3..48a55ba1d8 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -304,6 +304,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV=
CPU *cpu)
}
=20
isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+
+ /*
+ * Do not show user warnings for named features that users
+ * can't enable/disable in the command line. See commit
+ * 68c9e54bea for more info.
+ */
+ if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) {
+ continue;
+ }
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
@@ -331,11 +340,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *=
cpu)
cpu->cfg.has_priv_1_13 =3D true;
}
=20
- /* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 &&
cpu->cfg.cbop_blocksize =3D=3D 64 &&
- cpu->cfg.cboz_blocksize =3D=3D 64 &&
- cpu->cfg.has_priv_1_12;
+ cpu->cfg.cboz_blocksize =3D=3D 64;
}
=20
static void riscv_cpu_validate_g(RISCVCPU *cpu)
--=20
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To: qemu-devel@nongnu.org
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Alistair Francis <alistair.francis@wdc.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PULL 38/39] target/riscv: add ssstateen
Date: Thu, 19 Dec 2024 08:30:08 +1000
Message-ID: <20241218223010.1931245-39-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
ssstateen is defined in RVA22 as:
"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."
Add ssstateen as a named feature that is available if we also have
smstateen.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
target/riscv/tcg/tcg-cpu.c | 9 ++++++++-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index d8771ca641..a1457ab4f4 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -140,6 +140,7 @@ struct RISCVCPUConfig {
/* Named features */
bool ext_svade;
bool ext_zic64b;
+ bool ext_ssstateen;
=20
/*
* Always 'true' booleans for named features
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18f4d94b6e..d7b830d489 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D {
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -1677,6 +1678,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e=
xts[] =3D {
*/
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
+ MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
=20
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 48a55ba1d8..cbf2cf1963 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -204,10 +204,15 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu=
, uint32_t feat_offset)
* All other named features are already enabled
* in riscv_tcg_cpu_instance_init().
*/
- if (feat_offset =3D=3D CPU_CFG_OFFSET(ext_zic64b)) {
+ switch (feat_offset) {
+ case CPU_CFG_OFFSET(ext_zic64b):
cpu->cfg.cbom_blocksize =3D 64;
cpu->cfg.cbop_blocksize =3D 64;
cpu->cfg.cboz_blocksize =3D 64;
+ break;
+ case CPU_CFG_OFFSET(ext_ssstateen):
+ cpu->cfg.ext_smstateen =3D true;
+ break;
}
}
=20
@@ -343,6 +348,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *c=
pu)
cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 &&
cpu->cfg.cbop_blocksize =3D=3D 64 &&
cpu->cfg.cboz_blocksize =3D=3D 64;
+
+ cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen;
}
=20
static void riscv_cpu_validate_g(RISCVCPU *cpu)
--=20
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Subject: [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU
Date: Thu, 19 Dec 2024 08:30:09 +1000
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From: MollyChen <xiaoou@iscas.ac.cn>
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen <xiaoou@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn>
[ Changes by AF
- Fixup code formatting
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 6547642287..d56b067bf2 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -50,6 +50,7 @@
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
+#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nan=
hu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
=20
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d7b830d489..58bb5196a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,34 @@ static void rv64_tt_ascalon_cpu_init(Object *obj)
#endif
}
=20
+static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
+{
+ CPURISCVState *env =3D &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu =3D RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
+ env->priv_ver =3D PRIV_VERSION_1_12_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.ext_zbc =3D true;
+ cpu->cfg.ext_zbkb =3D true;
+ cpu->cfg.ext_zbkc =3D true;
+ cpu->cfg.ext_zbkx =3D true;
+ cpu->cfg.ext_zknd =3D true;
+ cpu->cfg.ext_zkne =3D true;
+ cpu->cfg.ext_zknh =3D true;
+ cpu->cfg.ext_zksed =3D true;
+ cpu->cfg.ext_zksh =3D true;
+ cpu->cfg.ext_svinval =3D true;
+
+ cpu->cfg.mmu =3D true;
+ cpu->cfg.pmp =3D true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -3056,6 +3084,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90=
6_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo=
n_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1=
_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
+ MXL_RV64, rv64_xiangshan_=
nanhu_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu=
_init),
#endif /* CONFIG_TCG */
--=20
2.47.1