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Wed, 18 Dec 2024 10:15:15 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Leif Lindholm , Leif Lindholm , Marcin Juszkiewicz , Peter Maydell , Radoslaw Biernacki , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-stable@nongnu.org Subject: [PATCH v2 2/5] target/arm: ensure cntvoff_el2 also used for EL2 virt timer Date: Wed, 18 Dec 2024 18:15:08 +0000 Message-Id: <20241218181511.3575613-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241218181511.3575613-1-alex.bennee@linaro.org> References: <20241218181511.3575613-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734545824403116600 We were missing this case and will shortly be adding another. Re-arrange the code and use a switch statement to group the virtual timers. Signed-off-by: Alex Benn=C3=A9e Cc: qemu-stable@nongnu.org --- target/arm/helper.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 910ae62c47..5a1b416e18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2465,16 +2465,27 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeri= dx) ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; =20 if (gt->ctl & 1) { + uint64_t count =3D gt_get_countervalue(&cpu->env); + uint64_t offset; + uint64_t nexttick; + int istatus; + /* * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env); - uint64_t count =3D gt_get_countervalue(&cpu->env); + switch (timeridx) { + case GTIMER_VIRT: + case GTIMER_HYPVIRT: + offset =3D cpu->env.cp15.cntvoff_el2; + break; + default: + offset =3Dgt_phys_raw_cnt_offset(&cpu->env); + break; + } + /* Note that this must be unsigned 64 bit arithmetic: */ - int istatus =3D count - offset >=3D gt->cval; - uint64_t nexttick; + istatus =3D count - offset >=3D gt->cval; =20 gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); =20 --=20 2.39.5