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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 6/9] target/riscv: add shvstvecd
Date: Wed, 18 Dec 2024 08:40:23 -0300
Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com>
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shvstvecd is defined in RVA22 as:
"vstvec.MODE must be capable of holding the value 0 (Direct).
When vstvec.MODE=3DDirect, vstvec.BASE must be capable of holding any
valid four-byte-aligned address."
This is always true for TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 364 -> 374 bytes
2 files changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 70301def20..7aa8a136d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -186,6 +186,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D {
ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/vi=
rt/RHCT
index 065f894010272e7f27834b2c8d5d5fb0c21066a1..2c7dc6c9ab8d8da9c30ad34294e=
f28427a4f8f1a 100644
GIT binary patch
delta 49
zcmaFE^o@xt$iq3LjFEwX@#91;16C16Mh5PQ_9r<q%8E<MQj=3D3AvoXeT_%JdsgfTKO
F002~G3@88q
delta 40
vcmeyy^oEHm$iq1#hmnDSF=3Dir{0V@|HBLm|^`;(J}7-Kk`7#SFR7#SD<#!?6T
--=20
2.47.1