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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 1/9] target/riscv/tcg: hide warn for named feats when
disabling via priv_ver
Date: Wed, 18 Dec 2024 08:40:18 -0300
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Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to disable zic64b
manually in riscv_cpu_update_named_features().
This solution won't scale well when adding more named features, and can
eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().
Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
disabling a named feature. This will accomplish the same thing we're
doing today while avoiding having two points where we're disabling
exts via priv_ver mismatch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 3b99c8c9e3..48a55ba1d8 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -304,6 +304,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV=
CPU *cpu)
}
=20
isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+
+ /*
+ * Do not show user warnings for named features that users
+ * can't enable/disable in the command line. See commit
+ * 68c9e54bea for more info.
+ */
+ if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) {
+ continue;
+ }
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
@@ -331,11 +340,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *=
cpu)
cpu->cfg.has_priv_1_13 =3D true;
}
=20
- /* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 &&
cpu->cfg.cbop_blocksize =3D=3D 64 &&
- cpu->cfg.cboz_blocksize =3D=3D 64 &&
- cpu->cfg.has_priv_1_12;
+ cpu->cfg.cboz_blocksize =3D=3D 64;
}
=20
static void riscv_cpu_validate_g(RISCVCPU *cpu)
--=20
2.47.1