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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c8046c46sm10704122f8f.71.2024.12.17.01.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 01:07:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1734426435; x=1735031235; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ku01Gl3oK1QHidwQXXPkKJb4Kx7C9rCbPxgQWVg1Frw=; b=OBmpZirkXCghkoRdP6CbFqfS7qimetT5lI/HKpOmG76TUWocOgdbyAi7JykzIitu6P jA5QPnESomWz+c7gTbsD1MQD7i3XsK1Y5W23kbDRwWCsxEx5KPY4P4f2K83Rkw/OEak1 NiJvUQh8SEraSIQeZzD0T8XN13yZ/hPZokN2MOlNi964Xa7iWgj8NyQeOOhVFBw+ioti z4MD36eOFbvA9D7jf+9UV9/dG8hKufQBcpQ+RveF79HmbH5JprF7v0bVNcswhf/z2Zqg G+ePGbsUdsY8Ui5w72z5iiUwIG5C56ZUQ3aK5YPA57KEBIHGj5t7CowkvqBifjGUTaC8 e5Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734426435; x=1735031235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ku01Gl3oK1QHidwQXXPkKJb4Kx7C9rCbPxgQWVg1Frw=; b=XqxC/d+7mv2FMVdV8fk3zPqUigy7Ka+RPSE5KbKTdQvuhZv+q5/EBN/6a7RCVJ5OaF RQO2TPM2f9YX2q7BXEJY1+5KcZPTfJ+Q8Q1SuBUmNFlcwFG/NwIDOCKd9na+72DxnGC+ GLclI4IEB/bK7Gd9tZh3eTfmnr5fOvcnLvS9TUennBILTbsYck/wkl4wleUZ/A+6n26w 7hTHpq3Cx9rYykQ+p3EcJHJaN7Ojlfr52nuF64fLYumtmBkMGpdt1V8ZfQfNf/+7TwAX V3SMXi42r173SZBQGb/eBk2wphkUtIYAu2TeuqWauba/LbNqAsDGWG0UM8Dt3jCLMXD3 76Pg== X-Forwarded-Encrypted: i=1; AJvYcCWMaoty/7C03+SbIRkkdnXVGxMACUXOWqY6+jqzOJXeso74keL1E2ykQ1nlbfIbRIvQ/6GxuNrCJuRy@nongnu.org X-Gm-Message-State: AOJu0Yw5D2/ApPTCaC9pEKeOqympF9GTeF5tFhmNr1N9Dm3JnGjh9qg1 K9RH/g1r4C0DJzxGhHsZEqQrte5lhvNhs0Rt7o58ixUsbEkcH4L65J/LjX5eADA= X-Gm-Gg: ASbGncviy2/H+geSBTjwQ+/14Gu811MjqapdUFBDcbVDphxDZbZUrd4E2n7YzTBF0ta +Ud4n/zGfZKCrwxg++ZAdGcTOVazhnn1zisuGZuRrDN7EfNfFP/N0JFpwgz8UpKv2b2IwnbprB6 4jUpnWD0ib0LhpzgYtXyb9n53LIGGBfYZbmtIGmHtibr/0CfIv10zgJeusV9v3FMxM67ADdntM0 7aegO/Yy5gw/PjZP87XXQwwUqV/EoQ1GGYDwSaHGaOisqIsO4CDHXNJsw== X-Google-Smtp-Source: AGHT+IHb++ky95JtqXq4a51KHbnaYMgLyAIy0nzqxPaxoYBDr39phpHDw28FfTU34NLRwxqK3eAP1Q== X-Received: by 2002:adf:a3cd:0:b0:388:c61d:4415 with SMTP id ffacd0b85a97d-388db243d8fmr1573453f8f.18.1734426435454; Tue, 17 Dec 2024 01:07:15 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v7 4/9] target/riscv: Implement Ssdbltrp exception handling Date: Tue, 17 Dec 2024 10:07:00 +0100 Message-ID: <20241217090707.3511160-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241217090707.3511160-1-cleger@rivosinc.com> References: <20241217090707.3511160-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1734426510665116600 When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7a4aa235ce..cfb95eab14 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -296,7 +296,7 @@ static const char * const riscv_excp_names[] =3D { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b8acc11e65..e1244004b2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -707,6 +707,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP =3D 0x10, RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f284f94a04..06d5dc6a3d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1903,6 +1903,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt =3D env->virt_enabled; bool write_gva =3D false; bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); + bool vsmode_exc; uint64_t s; int mode; =20 @@ -1917,6 +1918,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1ULL << cause)); bool vs_injected =3D env->hvip & (1ULL << cause) & env->hvien && !(env->mip & (1ULL << cause)); + bool smode_double_trap =3D false; + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -2040,6 +2043,30 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; =20 + vsmode_exc =3D env->virt_enabled && (((hdeleg >> cause) & 1) || vs_inj= ected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv =3D=3D PRV_S && mode =3D=3D PRV= _S) { + bool dte =3D (env->menvcfg & MENVCFG_DTE) !=3D 0; + bool sdt =3D (env->mstatus & MSTATUS_SDT) !=3D 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte =3D (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt =3D (env->mstatus_hs & MSTATUS_SDT) !=3D 0; + } + } + smode_double_trap =3D dte && sdt; + if (smode_double_trap) { + mode =3D PRV_M; + } + } + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ /* save elp status */ @@ -2048,10 +2075,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -2084,6 +2108,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s =3D set_field(s, MSTATUS_SDT, 1); + } env->mstatus =3D s; sxlen =3D 16 << riscv_cpu_sxl(env); env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); @@ -2137,9 +2164,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 =3D env->mcause; + env->mcause =3D RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 =3D mtval2; + } env->mepc =3D env->pc; env->mtval =3D tval; - env->mtval2 =3D mtval2; env->mtinst =3D tinst; =20 /* --=20 2.45.2