From nobody Wed May 14 17:35:05 2025
Delivered-To: importer@patchew.org
Authentication-Results: mx.zohomail.com;
dkim=pass;
spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as
permitted sender)
smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=pass(p=reject dis=none) header.from=sifive.com
ARC-Seal: i=1; a=rsa-sha256; t=1734416782; cv=none;
d=zohomail.com; s=zohoarc;
b=Vp4ideuNwhVRyWgSXQC78K0chpdfw+CnXgjvBRtuInStWwAzpcARu4jb9XYC53RquAc7mD374CmNxBAuoFKyx4iz23h/EyryWlH3kwRqMDznwHHEmapl8IfSS/kdDMNAjdf5AjAhUt7VdrReFm+w6B9XcdSMM4qAYzjDBxThuyU=
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com;
s=zohoarc;
t=1734416782;
h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To;
bh=XGSNn9ae/MPwYaGPrUgG0bzpmz+FrdagSkhwlUWUTKY=;
b=Ak6YlqSPu4sDRWvlPcAIi0lFb0V7PK/ZfUbPIDydjJjDwR3gmo1azH/DMgpcuSv1Udo2DY0LZMFfnWv/54r5ug3u942jibe8Kcrz64RiwambN4hfx5e5WjNUnhTBg1HNBFKeN0xNoOtVu9SRwbH82VKZ9gM9xRm+bJip4Rz+47Q=
ARC-Authentication-Results: i=1; mx.zohomail.com;
dkim=pass;
spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as
permitted sender)
smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=pass header.from=<frank.chang@sifive.com> (p=reject dis=none)
Return-Path: <qemu-devel-bounces+importer=patchew.org@nongnu.org>
Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by
mx.zohomail.com
with SMTPS id 1734416782094552.4553469800375;
Mon, 16 Dec 2024 22:26:22 -0800 (PST)
Received: from localhost ([::1] helo=lists1p.gnu.org)
by lists.gnu.org with esmtp (Exim 4.90_1)
(envelope-from <qemu-devel-bounces@nongnu.org>)
id 1tNR1I-00031T-1b; Tue, 17 Dec 2024 01:25:26 -0500
Received: from eggs.gnu.org ([2001:470:142:3::10])
by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)
(Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)
id 1tNR1A-0002zE-P6
for qemu-devel@nongnu.org; Tue, 17 Dec 2024 01:25:16 -0500
Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429])
by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)
(Exim 4.90_1) (envelope-from <frank.chang@sifive.com>)
id 1tNR16-000545-MW
for qemu-devel@nongnu.org; Tue, 17 Dec 2024 01:25:16 -0500
Received: by mail-pf1-x429.google.com with SMTP id
d2e1a72fcca58-728f28744c5so4465295b3a.1
for <qemu-devel@nongnu.org>; Mon, 16 Dec 2024 22:25:11 -0800 (PST)
Received: from fchang-1826.internal.sifive.com ([210.176.154.33])
by smtp.gmail.com with ESMTPSA id
d2e1a72fcca58-72925e6e8b1sm4354301b3a.139.2024.12.16.22.25.06
(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
Mon, 16 Dec 2024 22:25:08 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=sifive.com; s=google; t=1734416709; x=1735021509; darn=nongnu.org;
h=content-transfer-encoding:mime-version:references:in-reply-to
:message-id:date:subject:cc:to:from:from:to:cc:subject:date
:message-id:reply-to;
bh=XGSNn9ae/MPwYaGPrUgG0bzpmz+FrdagSkhwlUWUTKY=;
b=ZBT0mxnrVEDV+XpQ/YeGrINmSQQdLIkCI2CWerxddPdraiVW10Hvaxy/Sf6z53zucm
57fLo7F5Eq3JMcAverCWBnwsVKdfpvLsK5ve0Hg+48t6uriksp9cKcR6flXlFe5mwBww
JfdxNLNnuukYxQgDmMVuV6Ka83a4DqPqinUzW9Ajiz179k+IULAn+Cecjthtum/hGB0z
3JCo6vTCwcBmLY3BksuEOnptnwuxq0kUTmudf1fxbDaWIw6S6sbntufqpd3Rm/vpQp5o
abEZpY3nIFmVNW35N+m8wKI3p+piAACGmaFZzyJsAzrYDX95OzQNz9Wu9NhZ2rdJnyrL
j7TQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1734416709; x=1735021509;
h=content-transfer-encoding:mime-version:references:in-reply-to
:message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc
:subject:date:message-id:reply-to;
bh=XGSNn9ae/MPwYaGPrUgG0bzpmz+FrdagSkhwlUWUTKY=;
b=MmUWdUp8cIfqClYfmFAH8smJgoxPbKXODitUDg3rNjGak1QCRasG/9jCDWNBH1E4Yh
TdtifjXvzQR+BdsBMpRNVveXoTUPoDiANJKPzKkpoAImbRFBq+H5+aUs8Xwm7V3RNB90
2veIZz/aFpgELmUym2fAwpuC8eNeTyEPf2GYtCzln2MNQmReCxDhAPdYLys47ttRrXCR
pB75Sd/zy3ESRGUsP/lNzCxVtZG5gIa2IpJGPiPWM+6BMRfDSlGKww0LNdnBSPsX6NAv
mF+RIW+5SBBI9kajNq7VxHOATi39xqkB8uajDv29YSRnhtLj60A2hE90ixLCGVBfxHX1
pC1A==
X-Gm-Message-State: AOJu0YzDsrShhPUyk7QxQvMDiuLTynW5iS0AKqO02f83iO30bbuISpaX
Hbv+X0pk71+nA6zop2xw46uU1mDrXDqIFwSig2ZGVvW8o6m72m6QlCBFuNJaSk/fNdKmMg3lSsI
18dJO6H3yyGiR44bdPe/4UpolUfz1UDHnnx0BCiEOGETxDoJtI4pDVOBgIx4SXxqTXM+BSxupx/
bekKcG1BJbWxG1UwBB61g9BJ52xPyRFn2MU+ZxQ/9zbg==
X-Gm-Gg: ASbGnctwKNh49vQovTlIHoKqI8QRia7tBZk9RZfFfz0FXUwzXODuztE4Ym5gYb5x7ar
xPsuXd42zQfydnfOQyn2MPd1qwPWGQCwfdGjutKbbM1ypdOrFIe+j3kCBlcZ5dZTqj9udPiv0+M
a0wEv2q55F96ZlHoAGLHiSU+smfgn9goXedydwrC0/onPbI1BmWx4xjg47Jg0S81A5ykbcfdWAk
Z94/bK1Zoxqi+IuZVWIX3zPNBh6dzxRW42ElHnRpl2eyahzcQ3OTNR7Snrk+ES3kzaFgSQTc/VG
oHcdHDlvGQM=
X-Google-Smtp-Source:
AGHT+IFa9cjaNPdYOPMTatzEJWZM3W2ox30ZAjQfiJgEGub3xN4rRBvT/5fD4DH5PGDNmszaHsks0Q==
X-Received: by 2002:a05:6a00:3d4b:b0:725:df1a:288 with SMTP id
d2e1a72fcca58-7290c27461emr23067465b3a.24.1734416709068;
Mon, 16 Dec 2024 22:25:09 -0800 (PST)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Tommy Wu <tommy.wu@sifive.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception
Date: Tue, 17 Dec 2024 14:24:36 +0800
Message-Id: <20241217062440.884261-4-frank.chang@sifive.com>
X-Mailer: git-send-email 2.34.1
In-Reply-To: <20241217062440.884261-1-frank.chang@sifive.com>
References: <20241217062440.884261-1-frank.chang@sifive.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: quoted-printable
Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17
as permitted sender) client-ip=209.51.188.17;
envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org;
helo=lists.gnu.org;
Received-SPF: pass client-ip=2607:f8b0:4864:20::429;
envelope-from=frank.chang@sifive.com; helo=mail-pf1-x429.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,
SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org
Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org
X-ZohoMail-DKIM: pass (identity @sifive.com)
X-ZM-MESSAGEID: 1734416784062116600
From: Tommy Wu <tommy.wu@sifive.com>
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the prope=
rty
of the harts. It=E2=80=99s very easy for users to set the address based on =
their
expectation. This patch also adds the functionality to handle the RNMI sign=
als.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/riscv_hart.c | 40 +++++++++++++++++
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c | 11 +++++
target/riscv/cpu.h | 3 ++
target/riscv/cpu_bits.h | 12 +++++
target/riscv/cpu_helper.c | 85 ++++++++++++++++++++++++++++++++---
6 files changed, 150 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 0df454772f..f5e40e608d 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -26,6 +26,7 @@
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
#include "hw/riscv/riscv_hart.h"
+#include "qemu/error-report.h"
=20
static const Property riscv_harts_props[] =3D {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
@@ -33,6 +34,22 @@ static const Property riscv_harts_props[] =3D {
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
DEFAULT_RSTVEC),
+ /*
+ * Smrnmi implementation-defined interrupt and exception trap handlers.
+ *
+ * When an RNMI interrupt is detected, the hart then enters M-mode and
+ * jumps to the address defined by "rnmi-interrupt-vector".
+ *
+ * When the hart encounters an exception while executing in M-mode with
+ * the mnstatus.NMIE bit clear, the hart then jumps to the address
+ * defined by "rnmi-exception-vector".
+ */
+ DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState,
+ num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64,
+ uint64_t),
+ DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState,
+ num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64,
+ uint64_t),
DEFINE_PROP_END_OF_LIST(),
};
=20
@@ -47,6 +64,29 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, i=
nt idx,
{
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ=
e);
qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
+
+ if (s->harts[idx].cfg.ext_smrnmi) {
+ if (idx < s->num_rnmi_irqvec) {
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
+ "rnmi-interrupt-vector", s->rnmi_irqvec[i=
dx]);
+ }
+
+ if (idx < s->num_rnmi_excpvec) {
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
+ "rnmi-exception-vector", s->rnmi_excpvec[=
idx]);
+ }
+ } else {
+ if (s->num_rnmi_irqvec > 0) {
+ warn_report_once("rnmi-interrupt-vector property is ignored "
+ "because Smrnmi extension is not enabled.");
+ }
+
+ if (s->num_rnmi_excpvec > 0) {
+ warn_report_once("rnmi-exception-vector property is ignored "
+ "because Smrnmi extension is not enabled.");
+ }
+ }
+
s->harts[idx].env.mhartid =3D s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 912b4a2682..a6ed73a195 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -38,6 +38,10 @@ struct RISCVHartArrayState {
uint32_t hartid_base;
char *cpu_type;
uint64_t resetvec;
+ uint32_t num_rnmi_irqvec;
+ uint64_t *rnmi_irqvec;
+ uint32_t num_rnmi_excpvec;
+ uint64_t *rnmi_excpvec;
RISCVCPU *harts;
};
=20
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ade9e6e190..e6988f44c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1419,6 +1419,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq,=
int level)
g_assert_not_reached();
}
}
+
+static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
+{
+ riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
+}
#endif /* CONFIG_USER_ONLY */
=20
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
@@ -1442,6 +1447,8 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
+ qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi,
+ "riscv.cpu.rnmi", RNMI_MAX);
#endif /* CONFIG_USER_ONLY */
=20
general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal);
@@ -2797,6 +2804,10 @@ static const Property riscv_cpu_properties[] =3D {
=20
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
+ DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec,
+ DEFAULT_RNMI_IRQVEC),
+ DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec,
+ DEFAULT_RNMI_EXCPVEC),
#endif
=20
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f=
alse),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a2cb471b3c..8dc5b4d002 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -493,6 +493,8 @@ struct CPUArchState {
target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */
target_ulong mnstatus;
target_ulong rnmip;
+ uint64_t rnmi_irqvec;
+ uint64_t rnmi_excpvec;
};
=20
/*
@@ -591,6 +593,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
uint64_t value);
+void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value =
*/
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 9e9637263d..17787fd693 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -680,6 +680,12 @@ typedef enum {
/* Default Reset Vector address */
#define DEFAULT_RSTVEC 0x1000
=20
+/* Default RNMI Interrupt Vector address */
+#define DEFAULT_RNMI_IRQVEC 0x0
+
+/* Default RNMI Exception Vector address */
+#define DEFAULT_RNMI_EXCPVEC 0x0
+
/* Exception causes */
typedef enum RISCVException {
RISCV_EXCP_NONE =3D -1, /* sentinel value */
@@ -734,6 +740,9 @@ typedef enum RISCVException {
/* -1 is due to bit zero of hgeip and hgeie being ROZ. */
#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
=20
+/* RNMI causes */
+#define RNMI_MAX 16
+
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
#define MIP_SSIP (1 << IRQ_S_SOFT)
@@ -972,6 +981,9 @@ typedef enum RISCVException {
#define MHPMEVENT_IDX_MASK 0xFFFFF
#define MHPMEVENT_SSCOF_RESVD 16
=20
+/* RISC-V-specific interrupt pending bits. */
+#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
+
/* JVT CSR bits */
#define JVT_MODE 0x3F
#define JVT_BASE (~0x3F)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 750c0537ca..e5ffbbbd83 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -505,6 +505,18 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *=
env)
uint64_t vsbits, irq_delegated;
int virq;
=20
+ /* Priority: RNMI > Other interrupt. */
+ if (riscv_cpu_cfg(env)->ext_smrnmi) {
+ /* If mnstatus.NMIE =3D=3D 0, all interrupts are disabled. */
+ if (!get_field(env->mnstatus, MNSTATUS_NMIE)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (env->rnmip) {
+ return ctz64(env->rnmip); /* since non-zero */
+ }
+ }
+
/* Determine interrupt enable state of all privilege modes */
if (env->virt_enabled) {
mie =3D 1;
@@ -567,7 +579,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e=
nv)
=20
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- if (interrupt_request & CPU_INTERRUPT_HARD) {
+ uint32_t mask =3D CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI;
+
+ if (interrupt_request & mask) {
RISCVCPU *cpu =3D RISCV_CPU(cs);
CPURISCVState *env =3D &cpu->env;
int interruptno =3D riscv_cpu_local_irq_pending(env);
@@ -699,6 +713,30 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u=
long geilen)
env->geilen =3D geilen;
}
=20
+void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level)
+{
+ CPURISCVState *env =3D &cpu->env;
+ CPUState *cs =3D CPU(cpu);
+ bool release_lock =3D false;
+
+ if (!bql_locked()) {
+ release_lock =3D true;
+ bql_lock();
+ }
+
+ if (level) {
+ env->rnmip |=3D 1 << irq;
+ cpu_interrupt(cs, CPU_INTERRUPT_RNMI);
+ } else {
+ env->rnmip &=3D ~(1 << irq);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI);
+ }
+
+ if (release_lock) {
+ bql_unlock();
+ }
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env =3D &cpu->env;
@@ -1849,6 +1887,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool write_gva =3D false;
bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO);
uint64_t s;
+ int mode;
=20
/*
* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
@@ -1867,6 +1906,23 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong mtval2 =3D 0;
int sxlen =3D 0;
int mxlen =3D 0;
+ bool nnmi_excep =3D false;
+
+ if (cpu->cfg.ext_smrnmi && env->rnmip && async) {
+ env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false);
+ env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV,
+ env->virt_enabled);
+ env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP,
+ env->priv);
+ env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - =
1));
+ env->mnepc =3D env->pc;
+ env->pc =3D env->rnmi_irqvec;
+
+ /* Trapping to M mode, virt is disabled */
+ riscv_cpu_set_mode(env, PRV_M, false);
+
+ return;
+ }
=20
if (!async) {
/* set tval to badaddr for traps with address information */
@@ -1960,8 +2016,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
__func__, env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
=20
- if (env->priv <=3D PRV_S && cause < 64 &&
- (((deleg >> cause) & 1) || s_injected || vs_injected)) {
+ mode =3D env->priv <=3D PRV_S && cause < 64 &&
+ (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR=
V_M;
+
+ if (mode =3D=3D PRV_S) {
/* handle the trap in S-mode */
/* save elp status */
if (cpu_get_fcfien(env)) {
@@ -2016,6 +2074,14 @@ void riscv_cpu_do_interrupt(CPUState *cs)
((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0);
riscv_cpu_set_mode(env, PRV_S, virt);
} else {
+ /*
+ * If the hart encounters an exception while executing in M-mode
+ * with the mnstatus.NMIE bit clear, the exception is an RNMI exce=
ption.
+ */
+ nnmi_excep =3D cpu->cfg.ext_smrnmi &&
+ !get_field(env->mnstatus, MNSTATUS_NMIE) &&
+ !async;
+
/* handle the trap in M-mode */
/* save elp status */
if (cpu_get_fcfien(env)) {
@@ -2049,8 +2115,17 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->mtval =3D tval;
env->mtval2 =3D mtval2;
env->mtinst =3D tinst;
- env->pc =3D (env->mtvec >> 2 << 2) +
- ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0);
+
+ /*
+ * For RNMI exception, program counter is set to the RNMI exception
+ * trap handler address.
+ */
+ if (nnmi_excep) {
+ env->pc =3D env->rnmi_excpvec;
+ } else {
+ env->pc =3D (env->mtvec >> 2 << 2) +
+ ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : =
0);
+ }
riscv_cpu_set_mode(env, PRV_M, virt);
}
=20
--=20
2.34.1