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From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Tommy Wu <tommy.wu@sifive.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v10 2/7] target/riscv: Add Smrnmi CSRs
Date: Tue, 17 Dec 2024 14:24:35 +0800
Message-Id: <20241217062440.884261-3-frank.chang@sifive.com>
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From: Tommy Wu <tommy.wu@sifive.com>
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 7 ++++
target/riscv/cpu_bits.h | 11 ++++++
target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 105 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6748185206..ade9e6e190 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1134,6 +1134,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT=
ype type)
riscv_trigger_reset_hold(env);
}
=20
+ if (cpu->cfg.ext_smrnmi) {
+ env->rnmip =3D 0;
+ env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false);
+ }
+
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..a2cb471b3c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -486,6 +486,13 @@ struct CPUArchState {
uint64_t kvm_timer_state;
uint64_t kvm_timer_frequency;
#endif /* CONFIG_KVM */
+
+ /* RNMI */
+ target_ulong mnscratch;
+ target_ulong mnepc;
+ target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */
+ target_ulong mnstatus;
+ target_ulong rnmip;
};
=20
/*
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fe4e34c64a..9e9637263d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -353,6 +353,12 @@
#define CSR_PMPADDR14 0x3be
#define CSR_PMPADDR15 0x3bf
=20
+/* RNMI */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
+
/* Debug/Trace Registers (shared with Debug Mode) */
#define CSR_TSELECT 0x7a0
#define CSR_TDATA1 0x7a1
@@ -634,6 +640,11 @@ typedef enum {
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
=20
+/* RNMI mnstatus CSR mask */
+#define MNSTATUS_NMIE 0x00000008
+#define MNSTATUS_MNPV 0x00000080
+#define MNSTATUS_MNPP 0x00001800
+
/* VM modes (satp.mode) privileged ISA 1.10 */
#define VM_1_10_MBARE 0
#define VM_1_10_SV32 1
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b6fa8ae53f..65daf6d138 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -597,6 +597,17 @@ static RISCVException debug(CPURISCVState *env, int cs=
rno)
=20
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException rnmi(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu =3D env_archcpu(env);
+
+ if (cpu->cfg.ext_smrnmi) {
+ return RISCV_EXCP_NONE;
+ }
+
+ return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
=20
static RISCVException seed(CPURISCVState *env, int csrno)
@@ -4654,6 +4665,67 @@ static RISCVException write_upmbase(CPURISCVState *e=
nv, int csrno,
return RISCV_EXCP_NONE;
}
=20
+static RISCVException read_mnscratch(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val =3D env->mnscratch;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mnscratch =3D val;
+ return RISCV_EXCP_NONE;
+}
+
+static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val =3D env->mnepc;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mnepc =3D val;
+ return RISCV_EXCP_NONE;
+}
+
+static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val =3D env->mncause;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mncause(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mncause =3D val;
+ return RISCV_EXCP_NONE;
+}
+
+static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val =3D env->mnstatus;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP);
+
+ if (riscv_has_ext(env, RVH)) {
+ /* Flush tlb on mnstatus fields that affect VM. */
+ if ((val ^ env->mnstatus) & MNSTATUS_MNPV) {
+ tlb_flush(env_cpu(env));
+ }
+
+ mask |=3D MNSTATUS_MNPV;
+ }
+
+ /* mnstatus.mnie can only be cleared by hardware. */
+ env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask);
+ return RISCV_EXCP_NONE;
+}
+
#endif
=20
/* Crypto Extension */
@@ -5161,6 +5233,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
write_sstateen_1_3,
.min_priv_ver =3D PRIV_VERSION_1_12_0 },
=20
+ /* RNMI */
+ [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat=
ch,
+ .min_priv_ver =3D PRIV_VERSION_1_12_0 =
},
+ [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc,
+ .min_priv_ver =3D PRIV_VERSION_1_12_0 =
},
+ [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause,
+ .min_priv_ver =3D PRIV_VERSION_1_12_0 =
},
+ [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu=
s,
+ .min_priv_ver =3D PRIV_VERSION_1_12_0 =
},
+
/* Supervisor Trap Setup */
[CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst=
atus,
NULL, read_sstatus_i128 =
},
--=20
2.34.1