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Subject: [PATCH v4 2/7] target/arm/tcg: increase cache level for cpu=max
Date: Mon, 16 Dec 2024 17:54:09 +0000
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Reply-to: Alireza Sanaee <alireza.sanaee@huawei.com>
From: Alireza Sanaee via <qemu-devel@nongnu.org>
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This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=3Dmax. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
target/arm/tcg/cpu64.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 904a7e90b4..47d8c9c9ae 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj)
uint64_t t;
uint32_t u;
=20
+ /*
+ * Expanded cache set
+ */
+ cpu->clidr =3D 0x8200123; /* 4 4 3 in 3 bit fields */
+ /* 64KB L1 dcache */
+ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, =
7);
+ /* 64KB L1 icache */
+ cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, =
2);
+ /* 1MB L2 unified cache */
+ cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7=
);
+ /* 2MB L3 unified cache */
+ cpu->ccsidr[4] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7=
);
+
/*
* Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise defau=
lt
* to because we started with aarch64_a57_initfn(). A 'max' CPU might
--=20
2.34.1