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From: baturo.alexey@gmail.com
To: 
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
 zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
 liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com,
 palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
 kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
 qemu-riscv@nongnu.org
Subject: [PATCH v13 6/7] target/riscv: Apply pointer masking for virtualized
 memory accesses
Date: Mon, 16 Dec 2024 15:19:06 +0300
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Content-Type: text/plain; charset="utf-8"

From: Alexey Baturo <baturo.alexey@gmail.com>

Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.h           |  1 +
 target/riscv/cpu_helper.c    | 18 +++++++++++++++
 target/riscv/internals.h     | 44 ++++++++++++++++++++++++++++++++++++
 target/riscv/op_helper.c     | 16 ++++++-------
 target/riscv/vector_helper.c | 21 -----------------
 5 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 38231fe21e..536ad20fdd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -773,6 +773,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
=20
 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);
 RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env);
 uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
=20
 RISCVException riscv_csrr(CPURISCVState *env, int csrno,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 480d2c2c8b..471d8d40a1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,24 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
     return pmm;
 }
=20
+RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env)
+{
+    RISCVPmPmm pmm =3D PMM_FIELD_DISABLED;
+#ifndef CONFIG_USER_ONLY
+    int priv_mode =3D cpu_address_mode(env);
+    if (priv_mode =3D=3D PRV_U) {
+        pmm =3D get_field(env->hstatus, HSTATUS_HUPMM);
+    } else {
+        if (get_field(env->hstatus, HSTATUS_SPVP)) {
+            pmm =3D get_field(env->henvcfg, HENVCFG_PMM);
+        } else {
+            pmm =3D get_field(env->senvcfg, SENVCFG_PMM);
+        }
+    }
+#endif
+    return pmm;
+}
+
 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
 {
     bool virt_mem_en =3D false;
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ddbdee885b..017f33af1f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -142,4 +142,48 @@ static inline float16 check_nanbox_h(CPURISCVState *en=
v, uint64_t f)
 /* Our implementation of CPUClass::has_work */
 bool riscv_cpu_has_work(CPUState *cs);
=20
+/* Zjpm addr masking routine */
+static inline target_ulong adjust_addr_body(CPURISCVState *env,
+                                            target_ulong addr,
+                                            bool is_virt)
+{
+    if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) {
+        return addr;
+    }
+    RISCVPmPmm pmm =3D PMM_FIELD_DISABLED;
+    if (is_virt) {
+        pmm =3D riscv_pm_get_virt_pmm(env);
+    } else {
+        pmm =3D riscv_pm_get_pmm(env);
+    }
+    if (pmm =3D=3D PMM_FIELD_DISABLED) {
+        return addr;
+    }
+    uint32_t pmlen =3D riscv_pm_get_pmlen(pmm);
+    bool signext =3D false;
+    if (!is_virt) {
+        signext =3D riscv_cpu_virt_mem_enabled(env);
+    }
+    addr =3D addr << pmlen;
+    /* sign/zero extend masked address by N-1 bit */
+    if (signext) {
+        addr =3D (target_long)addr >> pmlen;
+    } else {
+        addr =3D addr >> pmlen;
+    }
+    return addr;
+}
+
+static inline target_ulong adjust_addr(CPURISCVState *env,
+                                       target_ulong addr)
+{
+    return adjust_addr_body(env, addr, false);
+}
+
+static inline target_ulong adjust_addr_virt(CPURISCVState *env,
+                                            target_ulong addr)
+{
+    return adjust_addr_body(env, addr, true);
+}
+
 #endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index eddedacf4b..20e5bd5088 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -472,7 +472,7 @@ target_ulong helper_hyp_hlv_bu(CPURISCVState *env, targ=
et_ulong addr)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx);
=20
-    return cpu_ldb_mmu(env, addr, oi, ra);
+    return cpu_ldb_mmu(env, adjust_addr_virt(env, addr), oi, ra);
 }
=20
 target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr)
@@ -481,7 +481,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, targ=
et_ulong addr)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx);
=20
-    return cpu_ldw_mmu(env, addr, oi, ra);
+    return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra);
 }
=20
 target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr)
@@ -490,7 +490,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, targ=
et_ulong addr)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx);
=20
-    return cpu_ldl_mmu(env, addr, oi, ra);
+    return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra);
 }
=20
 target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr)
@@ -499,7 +499,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, targe=
t_ulong addr)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx);
=20
-    return cpu_ldq_mmu(env, addr, oi, ra);
+    return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra);
 }
=20
 void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong =
val)
@@ -508,7 +508,7 @@ void helper_hyp_hsv_b(CPURISCVState *env, target_ulong =
addr, target_ulong val)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx);
=20
-    cpu_stb_mmu(env, addr, val, oi, ra);
+    cpu_stb_mmu(env, adjust_addr_virt(env, addr), val, oi, ra);
 }
=20
 void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong =
val)
@@ -517,7 +517,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong =
addr, target_ulong val)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx);
=20
-    cpu_stw_mmu(env, addr, val, oi, ra);
+    cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra);
 }
=20
 void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong =
val)
@@ -526,7 +526,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong =
addr, target_ulong val)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx);
=20
-    cpu_stl_mmu(env, addr, val, oi, ra);
+    cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra);
 }
=20
 void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong =
val)
@@ -535,7 +535,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong =
addr, target_ulong val)
     int mmu_idx =3D check_access_hlsv(env, false, ra);
     MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx);
=20
-    cpu_stq_mmu(env, addr, val, oi, ra);
+    cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra);
 }
=20
 /*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 37c6c198a5..a0093bcc9c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -105,27 +105,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, u=
int32_t log2_esz)
     return scale < 0 ? vlenb >> -scale : vlenb << scale;
 }
=20
-static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad=
dr)
-{
-    if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) {
-        return addr;
-    }
-    RISCVPmPmm pmm =3D riscv_pm_get_pmm(env);
-    if (pmm =3D=3D PMM_FIELD_DISABLED) {
-        return addr;
-    }
-    int pmlen =3D riscv_pm_get_pmlen(pmm);
-    bool signext =3D riscv_cpu_virt_mem_enabled(env);
-    addr =3D addr << pmlen;
-    /* sign/zero extend masked address by N-1 bit */
-    if (signext) {
-        addr =3D (target_long)addr >> pmlen;
-    } else {
-        addr =3D addr >> pmlen;
-    }
-    return addr;
-}
-
 /*
  * This function checks watchpoint before real load operation.
  *
--=20
2.39.5