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From: baturo.alexey@gmail.com
To:
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com,
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kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v13 4/7] target/riscv: Add pointer masking tb flags
Date: Mon, 16 Dec 2024 15:19:04 +0300
Message-Id: <20241216121907.660504-5-baturo.alexey@gmail.com>
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Content-Type: text/plain; charset="utf-8"
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +++++
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e7f346ff6b..38231fe21e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -631,6 +631,9 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1)
FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1)
/* zicfiss needs a TB flag so that correct TB is located based on tb flags=
*/
FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
+/* If pointer masking should be applied and address sign extended */
+FIELD(TB_FLAGS, PM_PMM, 29, 2)
+FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)
=20
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ed0d275e84..480d2c2c8b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -126,6 +126,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
RISCVCPU *cpu =3D env_archcpu(env);
RISCVExtStatus fs, vs;
uint32_t flags =3D 0;
+ bool pm_signext =3D riscv_cpu_virt_mem_enabled(env);
=20
*pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base =3D 0;
@@ -210,6 +211,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
+ flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
+ flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
=20
*pflags =3D flags;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 018be5504f..bb92f36ba1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -102,6 +102,9 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
+ /* actual address width */
+ uint8_t addr_xl;
+ bool addr_signed;
/* Ztso */
bool ztso;
/* Use icount trigger for native debug */
@@ -1230,6 +1233,8 @@ static void riscv_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cs)
ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs =3D cs;
+ ctx->addr_xl =3D 0;
+ ctx->addr_signed =3D false;
ctx->ztso =3D cpu->cfg.ext_ztso;
ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED);
--=20
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