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From: baturo.alexey@gmail.com
To:
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: [PATCH v13 3/7] target/riscv: Add helper functions to calculate
current number of masked bits for pointer masking
Date: Mon, 16 Dec 2024 15:19:03 +0300
Message-Id: <20241216121907.660504-4-baturo.alexey@gmail.com>
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Content-Type: text/plain; charset="utf-8"
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.h | 5 +++
target/riscv/cpu_helper.c | 73 +++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 417ff45544..e7f346ff6b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -768,8 +768,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p=
c,
=20
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
=20
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
+
RISCVException riscv_csrr(CPURISCVState *env, int csrno,
target_ulong *ret_value);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask=
);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index dba04851d5..ed0d275e84 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -214,6 +214,79 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p=
c,
*pflags =3D flags;
}
=20
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+{
+ RISCVPmPmm pmm =3D PMM_FIELD_DISABLED;
+#ifndef CONFIG_USER_ONLY
+ if (get_field(env->mstatus, MSTATUS_MPRV) &&
+ get_field(env->mstatus, MSTATUS_MXR)) {
+ return pmm;
+ }
+ int priv_mode =3D cpu_address_mode(env);
+ /* Get current PMM field */
+ switch (priv_mode) {
+ case PRV_M:
+ if (riscv_cpu_cfg(env)->ext_smmpm) {
+ pmm =3D get_field(env->mseccfg, MSECCFG_PMM);
+ }
+ break;
+ case PRV_S:
+ if (riscv_cpu_cfg(env)->ext_smnpm) {
+ if (get_field(env->mstatus, MSTATUS_MPV)) {
+ pmm =3D get_field(env->henvcfg, HENVCFG_PMM);
+ } else {
+ pmm =3D get_field(env->menvcfg, MENVCFG_PMM);
+ }
+ }
+ break;
+ case PRV_U:
+ if (riscv_has_ext(env, RVS)) {
+ if (riscv_cpu_cfg(env)->ext_ssnpm) {
+ pmm =3D get_field(env->senvcfg, SENVCFG_PMM);
+ }
+ } else {
+ if (riscv_cpu_cfg(env)->ext_smnpm) {
+ pmm =3D get_field(env->menvcfg, MENVCFG_PMM);
+ }
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+ return pmm;
+}
+
+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
+{
+ bool virt_mem_en =3D false;
+#ifndef CONFIG_USER_ONLY
+ int satp_mode =3D 0;
+ int priv_mode =3D cpu_address_mode(env);
+ if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) {
+ satp_mode =3D get_field(env->satp, SATP32_MODE);
+ } else {
+ satp_mode =3D get_field(env->satp, SATP64_MODE);
+ }
+ virt_mem_en =3D ((satp_mode !=3D VM_1_10_MBARE) && (priv_mode !=3D PRV=
_M));
+#endif
+ return virt_mem_en;
+}
+
+uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm)
+{
+ switch (pmm) {
+ case PMM_FIELD_DISABLED:
+ return 0;
+ case PMM_FIELD_PMLEN7:
+ return 7;
+ case PMM_FIELD_PMLEN16:
+ return 16;
+ default:
+ g_assert_not_reached();
+ }
+}
+
#ifndef CONFIG_USER_ONLY
=20
/*
--=20
2.39.5