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From: baturo.alexey@gmail.com
To:
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v13 1/7] target/riscv: Remove obsolete pointer masking
extension code.
Date: Mon, 16 Dec 2024 15:19:01 +0300
Message-Id: <20241216121907.660504-2-baturo.alexey@gmail.com>
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From: Alexey Baturo <baturo.alexey@gmail.com>
Zjpm extension is finally ratified. And it's much simplier compared to the =
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer =
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 13 +-
target/riscv/cpu.h | 33 +---
target/riscv/cpu_bits.h | 87 ----------
target/riscv/cpu_helper.c | 52 ------
target/riscv/csr.c | 326 -----------------------------------
target/riscv/machine.c | 17 +-
target/riscv/tcg/tcg-cpu.c | 5 +-
target/riscv/translate.c | 28 +--
target/riscv/vector_helper.c | 2 +-
9 files changed, 19 insertions(+), 544 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 80b09952e7..8dea26e214 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -42,7 +42,7 @@
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH";
const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
- RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
+ RVC, RVS, RVU, RVH, RVG, RVB, 0};
=20
/*
* From vector_helper.c
@@ -793,13 +793,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f=
, int flags)
CSR_MSCRATCH,
CSR_SSCRATCH,
CSR_SATP,
- CSR_MMTE,
- CSR_UPMBASE,
- CSR_UPMMASK,
- CSR_SPMBASE,
- CSR_SPMMASK,
- CSR_MPMBASE,
- CSR_MPMMASK,
};
=20
for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) {
@@ -985,8 +978,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType=
type)
}
i++;
}
- /* mmte is supposed to have pm.current hardwired to 1 */
- env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
=20
/*
* Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor
@@ -1018,7 +1009,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy=
pe type)
env->ssp =3D 0;
=20
env->xl =3D riscv_cpu_mxl(env);
- riscv_cpu_update_mask(env);
cs->exception_index =3D RISCV_EXCP_NONE;
env->load_res =3D -1;
set_default_nan_mode(1, &env->fp_status);
@@ -1408,7 +1398,6 @@ static const MISAExtInfo misa_ext_info_arr[] =3D {
MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
MISA_EXT_INFO(RVU, "u", "User-level instructions"),
MISA_EXT_INFO(RVH, "h", "Hypervisor"),
- MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
MISA_EXT_INFO(RVV, "v", "Vector operations"),
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..e11264231d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -71,7 +71,6 @@ typedef struct CPUArchState CPURISCVState;
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
-#define RVJ RV('J')
#define RVG RV('G')
#define RVB RV('B')
=20
@@ -451,24 +450,11 @@ struct CPUArchState {
/* True if in debugger mode. */
bool debugger;
=20
- /*
- * CSRs for PointerMasking extension
- */
- target_ulong mmte;
- target_ulong mpmmask;
- target_ulong mpmbase;
- target_ulong spmmask;
- target_ulong spmbase;
- target_ulong upmmask;
- target_ulong upmbase;
-
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
uint64_t henvcfg;
#endif
- target_ulong cur_pmmask;
- target_ulong cur_pmbase;
=20
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
@@ -624,19 +610,19 @@ FIELD(TB_FLAGS, XL, 16, 2)
/* If PointerMasking should be applied */
FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
-FIELD(TB_FLAGS, VTA, 20, 1)
-FIELD(TB_FLAGS, VMA, 21, 1)
+FIELD(TB_FLAGS, VTA, 18, 1)
+FIELD(TB_FLAGS, VMA, 19, 1)
/* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 22, 1)
+FIELD(TB_FLAGS, ITRIGGER, 20, 1)
/* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
-FIELD(TB_FLAGS, PRIV, 24, 2)
-FIELD(TB_FLAGS, AXL, 26, 2)
+FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
+FIELD(TB_FLAGS, PRIV, 22, 2)
+FIELD(TB_FLAGS, AXL, 24, 2)
/* zicfilp needs a TB flag to track indirect branches */
-FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1)
-FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1)
+FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1)
+FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1)
/* zicfiss needs a TB flag so that correct TB is located based on tb flags=
*/
-FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1)
+FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)
=20
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
@@ -772,7 +758,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u=
int32_t vsew,
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
=20
-void riscv_cpu_update_mask(CPURISCVState *env);
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
=20
RISCVException riscv_csrr(CPURISCVState *env, int csrno,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 385a2c67c2..2a6aff63ed 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -497,37 +497,6 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
=20
-/*
- * User PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_UMTE 0x4c0
-#define CSR_UPMMASK 0x4c1
-#define CSR_UPMBASE 0x4c2
-
-/*
- * Machine PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_MMTE 0x3c0
-#define CSR_MPMMASK 0x3c1
-#define CSR_MPMBASE 0x3c2
-
-/*
- * Supervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_SMTE 0x1c0
-#define CSR_SPMMASK 0x1c1
-#define CSR_SPMBASE 0x1c2
-
-/*
- * Hypervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_VSMTE 0x2c0
-#define CSR_VSPMMASK 0x2c1
-#define CSR_VSPMBASE 0x2c2
#define CSR_SCOUNTOVF 0xda0
=20
/* Crypto Extension */
@@ -758,11 +727,6 @@ typedef enum RISCVException {
#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
=20
-/* General PointerMasking CSR bits */
-#define PM_ENABLE 0x00000001ULL
-#define PM_CURRENT 0x00000002ULL
-#define PM_INSN 0x00000004ULL
-
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
#define MENVCFG_LPE BIT(2) /* zicfilp */
@@ -801,57 +765,6 @@ typedef enum RISCVException {
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
=20
-/* Offsets for every pair of control bits per each priv level */
-#define XS_OFFSET 0ULL
-#define U_OFFSET 2ULL
-#define S_OFFSET 5ULL
-#define M_OFFSET 8ULL
-
-#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
-#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
-#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
-#define U_PM_INSN (PM_INSN << U_OFFSET)
-#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
-#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
-#define S_PM_INSN (PM_INSN << S_OFFSET)
-#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
-#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
-#define M_PM_INSN (PM_INSN << M_OFFSET)
-
-/* mmte CSR bits */
-#define MMTE_PM_XS_BITS PM_XS_BITS
-#define MMTE_U_PM_ENABLE U_PM_ENABLE
-#define MMTE_U_PM_CURRENT U_PM_CURRENT
-#define MMTE_U_PM_INSN U_PM_INSN
-#define MMTE_S_PM_ENABLE S_PM_ENABLE
-#define MMTE_S_PM_CURRENT S_PM_CURRENT
-#define MMTE_S_PM_INSN S_PM_INSN
-#define MMTE_M_PM_ENABLE M_PM_ENABLE
-#define MMTE_M_PM_CURRENT M_PM_CURRENT
-#define MMTE_M_PM_INSN M_PM_INSN
-#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INS=
N | \
- MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INS=
N | \
- MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INS=
N | \
- MMTE_PM_XS_BITS)
-
-/* (v)smte CSR bits */
-#define SMTE_PM_XS_BITS PM_XS_BITS
-#define SMTE_U_PM_ENABLE U_PM_ENABLE
-#define SMTE_U_PM_CURRENT U_PM_CURRENT
-#define SMTE_U_PM_INSN U_PM_INSN
-#define SMTE_S_PM_ENABLE S_PM_ENABLE
-#define SMTE_S_PM_CURRENT S_PM_CURRENT
-#define SMTE_S_PM_INSN S_PM_INSN
-#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INS=
N | \
- SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INS=
N | \
- SMTE_PM_XS_BITS)
-
-/* umte CSR bits */
-#define UMTE_U_PM_ENABLE U_PM_ENABLE
-#define UMTE_U_PM_CURRENT U_PM_CURRENT
-#define UMTE_U_PM_INSN U_PM_INSN
-#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN=
SN)
-
/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
#define ISELECT_IPRIO0 0x30
#define ISELECT_IPRIO15 0x3f
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 45806f5ab0..dba04851d5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -210,61 +210,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *=
pc,
flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
- if (env->cur_pmmask !=3D 0) {
- flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
- }
- if (env->cur_pmbase !=3D 0) {
- flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
- }
=20
*pflags =3D flags;
}
=20
-void riscv_cpu_update_mask(CPURISCVState *env)
-{
- target_ulong mask =3D 0, base =3D 0;
- RISCVMXL xl =3D env->xl;
- /*
- * TODO: Current RVJ spec does not specify
- * how the extension interacts with XLEN.
- */
-#ifndef CONFIG_USER_ONLY
- int mode =3D cpu_address_mode(env);
- xl =3D cpu_get_xl(env, mode);
- if (riscv_has_ext(env, RVJ)) {
- switch (mode) {
- case PRV_M:
- if (env->mmte & M_PM_ENABLE) {
- mask =3D env->mpmmask;
- base =3D env->mpmbase;
- }
- break;
- case PRV_S:
- if (env->mmte & S_PM_ENABLE) {
- mask =3D env->spmmask;
- base =3D env->spmbase;
- }
- break;
- case PRV_U:
- if (env->mmte & U_PM_ENABLE) {
- mask =3D env->upmmask;
- base =3D env->upmbase;
- }
- break;
- default:
- g_assert_not_reached();
- }
- }
-#endif
- if (xl =3D=3D MXL_RV32) {
- env->cur_pmmask =3D mask & UINT32_MAX;
- env->cur_pmbase =3D base & UINT32_MAX;
- } else {
- env->cur_pmmask =3D mask;
- env->cur_pmbase =3D base;
- }
-}
-
#ifndef CONFIG_USER_ONLY
=20
/*
@@ -786,7 +735,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon=
g newpriv, bool virt_en)
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv =3D newpriv;
env->xl =3D cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
=20
/*
* Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9846770820..941c9691da 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -531,16 +531,6 @@ static RISCVException hgatp(CPURISCVState *env, int cs=
rno)
return hmode(env, csrno);
}
=20
-/* Checks if PointerMasking registers could be accessed */
-static RISCVException pointer_masking(CPURISCVState *env, int csrno)
-{
- /* Check if j-ext is present */
- if (riscv_has_ext(env, RVJ)) {
- return RISCV_EXCP_NONE;
- }
- return RISCV_EXCP_ILLEGAL_INST;
-}
-
static RISCVException aia_hmode(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_cfg(env)->ext_ssaia) {
@@ -1648,7 +1638,6 @@ static RISCVException write_mstatus(CPURISCVState *en=
v, int csrno,
env->xl =3D cpu_recompute_xl(env);
}
=20
- riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
=20
@@ -4351,302 +4340,6 @@ static RISCVException write_mcontext(CPURISCVState =
*env, int csrno,
return RISCV_EXCP_NONE;
}
=20
-/*
- * Functions to access Pointer Masking feature registers
- * We have to check if current priv lvl could modify
- * csr in given mode
- */
-static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
-{
- int csr_priv =3D get_field(csrno, 0x300);
- int pm_current;
-
- if (env->debugger) {
- return false;
- }
- /*
- * If priv lvls differ that means we're accessing csr from higher priv=
lvl,
- * so allow the access
- */
- if (env->priv !=3D csr_priv) {
- return false;
- }
- switch (env->priv) {
- case PRV_M:
- pm_current =3D get_field(env->mmte, M_PM_CURRENT);
- break;
- case PRV_S:
- pm_current =3D get_field(env->mmte, S_PM_CURRENT);
- break;
- case PRV_U:
- pm_current =3D get_field(env->mmte, U_PM_CURRENT);
- break;
- default:
- g_assert_not_reached();
- }
- /* It's same priv lvl, so we allow to modify csr only if pm.current=3D=
=3D1 */
- return !pm_current;
-}
-
-static RISCVException read_mmte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->mmte & MMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mmte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
- target_ulong wpri_val =3D val & MMTE_MASK;
-
- if (val !=3D wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x=
",
- val, "vs expected 0x", wpri_val);
- }
- /* for machine mode pm.current is hardwired to 1 */
- wpri_val |=3D MMTE_M_PM_CURRENT;
-
- /* hardwiring pm.instruction bit to 0, since it's not supported yet */
- wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
- env->mmte =3D wpri_val | EXT_STATUS_DIRTY;
- riscv_cpu_update_mask(env);
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_smte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->mmte & SMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_smte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val =3D val & SMTE_MASK;
-
- if (val !=3D wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x=
",
- val, "vs expected 0x", wpri_val);
- }
-
- /* if pm.current=3D=3D0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |=3D (env->mmte & ~SMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_umte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->mmte & UMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_umte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val =3D val & UMTE_MASK;
-
- if (val !=3D wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x=
",
- val, "vs expected 0x", wpri_val);
- }
-
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |=3D (env->mmte & ~UMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->mpmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmmask =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))=
{
- env->cur_pmmask =3D val;
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->spmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current=3D=3D0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmmask =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))=
{
- env->cur_pmmask =3D val;
- if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) {
- env->cur_pmmask &=3D UINT32_MAX;
- }
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->upmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current=3D=3D0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmmask =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))=
{
- env->cur_pmmask =3D val;
- if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) {
- env->cur_pmmask &=3D UINT32_MAX;
- }
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->mpmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmbase =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))=
{
- env->cur_pmbase =3D val;
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->spmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current=3D=3D0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmbase =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))=
{
- env->cur_pmbase =3D val;
- if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) {
- env->cur_pmbase &=3D UINT32_MAX;
- }
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val =3D env->upmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current=3D=3D0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmbase =3D val;
- if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))=
{
- env->cur_pmbase =3D val;
- if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) {
- env->cur_pmbase &=3D UINT32_MAX;
- }
- }
- env->mmte |=3D EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus =3D env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
#endif
=20
/* Crypto Extension */
@@ -5316,25 +5009,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
[CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore =
},
[CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex=
t },
=20
- /* User Pointer Masking */
- [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u=
mte },
- [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask,
- write_upmmask =
},
- [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase,
- write_upmbase =
},
- /* Machine Pointer Masking */
- [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m=
mte },
- [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask,
- write_mpmmask =
},
- [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase,
- write_mpmbase =
},
- /* Supervisor Pointer Masking */
- [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s=
mte },
- [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask,
- write_spmmask =
},
- [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase,
- write_spmbase =
},
-
/* Performance Counters */
[CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter },
[CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 99f0af5077..e40dc73994 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -152,25 +152,15 @@ static const VMStateDescription vmstate_vector =3D {
=20
static bool pointermasking_needed(void *opaque)
{
- RISCVCPU *cpu =3D opaque;
- CPURISCVState *env =3D &cpu->env;
-
- return riscv_has_ext(env, RVJ);
+ return false;
}
=20
static const VMStateDescription vmstate_pointermasking =3D {
.name =3D "cpu/pointer_masking",
- .version_id =3D 1,
- .minimum_version_id =3D 1,
+ .version_id =3D 2,
+ .minimum_version_id =3D 2,
.needed =3D pointermasking_needed,
.fields =3D (const VMStateField[]) {
- VMSTATE_UINTTL(env.mmte, RISCVCPU),
- VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
- VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
- VMSTATE_UINTTL(env.spmmask, RISCVCPU),
- VMSTATE_UINTTL(env.spmbase, RISCVCPU),
- VMSTATE_UINTTL(env.upmmask, RISCVCPU),
- VMSTATE_UINTTL(env.upmbase, RISCVCPU),
=20
VMSTATE_END_OF_LIST()
}
@@ -266,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int versio=
n_id)
CPURISCVState *env =3D &cpu->env;
=20
env->xl =3D cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
return 0;
}
=20
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c221696..179428f3f0 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1086,7 +1086,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =
=3D {
MISA_CFG(RVS, true),
MISA_CFG(RVU, true),
MISA_CFG(RVH, true),
- MISA_CFG(RVJ, false),
MISA_CFG(RVV, false),
MISA_CFG(RVG, false),
MISA_CFG(RVB, false),
@@ -1373,8 +1372,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
CPURISCVState *env =3D &cpu->env;
const RISCVCPUMultiExtConfig *prop;
=20
- /* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
+ /* Enable RVG and RVV that are disabled by default */
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV);
=20
for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bccaf8e89a..018be5504f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -41,9 +41,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cp=
u_vstart;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
-/* globals for PM CSRs */
-static TCGv pm_mask;
-static TCGv pm_base;
=20
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
@@ -105,9 +102,6 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
- /* PointerMasking extension */
- bool pm_mask_enabled;
- bool pm_base_enabled;
/* Ztso */
bool ztso;
/* Use icount trigger for native debug */
@@ -591,14 +585,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, in=
t imm)
TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE);
=20
tcg_gen_addi_tl(addr, src1, imm);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_address_xl(ctx) =3D=3D MXL_RV32) {
+ if (get_address_xl(ctx) =3D=3D MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
=20
return addr;
}
@@ -610,14 +599,10 @@ static TCGv get_address_indexed(DisasContext *ctx, in=
t rs1, TCGv offs)
TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE);
=20
tcg_gen_add_tl(addr, src1, offs);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_xl(ctx) =3D=3D MXL_RV32) {
+ if (get_xl(ctx) =3D=3D MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
+
return addr;
}
=20
@@ -1245,8 +1230,6 @@ static void riscv_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cs)
ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs =3D cs;
- ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE=
D);
- ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE=
D);
ctx->ztso =3D cpu->cfg.ext_ztso;
ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED);
@@ -1385,9 +1368,4 @@ void riscv_translate_init(void)
"load_res");
load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_=
val),
"load_val");
- /* Assign PM CSRs to tcg globals */
- pm_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm=
mask),
- "pmmask");
- pm_base =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm=
base),
- "pmbase");
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a85dd1d200..3589e3ef28 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -107,7 +107,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, ui=
nt32_t log2_esz)
=20
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad=
dr)
{
- return (addr & ~env->cur_pmmask) | env->cur_pmbase;
+ return addr;
}
=20
/*
--=20
2.39.5