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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 3/3] aspeed/soc: Support Timer for AST2700
Date: Mon, 16 Dec 2024 15:53:52 +0800
Message-ID: <20241216075353.1308043-4-jamin_lin@aspeedtech.com>
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
From: Jamin Lin via <qemu-devel@nongnu.org>
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Add Timer model for AST2700 Timer support. The Timer controller include 8 s=
ets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 =3D 0x12C1_0000
Base Address of Timer 1 =3D 0x12C1_0040
Base Address of Timer 2 =3D 0x12C1_0080
Base Address of Timer 3 =3D 0x12C1_00C0
Base Address of Timer 4 =3D 0x12C1_0100
Base Address of Timer 5 =3D 0x12C1_0140
Base Address of Timer 6 =3D 0x12C1_0180
Base Address of Timer 7 =3D 0x12C1_01C0
The interrupt of TIMER0 to TIMER7 as following.
GICINT16 =3D TIMER 0 interrupt
GICINT17 =3D TIMER 1 interrupt
GICINT18 =3D TIMER 2 interrupt
GICINT19 =3D TIMER 3 interrupt
GICINT20 =3D TIMER 4 interrupt
GICINT21 =3D TIMER 5 interrupt
GICINT22 =3D TIMER 6 interrupt
GICINT23 =3D TIMER 7 interrupt
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 23571584b2..292bb1c5b7 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -66,6 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
[ASPEED_DEV_GPIO] =3D 0x14C0B000,
[ASPEED_DEV_RTC] =3D 0x12C0F000,
[ASPEED_DEV_SDHCI] =3D 0x14080000,
+ [ASPEED_DEV_TIMER1] =3D 0x12C10000
};
=20
#define AST2700_MAX_IRQ 256
@@ -397,6 +398,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
=20
object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0=
],
TYPE_SYSBUS_SDHCI);
+
+ snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
}
=20
/*
@@ -716,6 +720,19 @@ static void aspeed_soc_ast2700_realize(DeviceState *de=
v, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
=20
+ /* Timer */
+ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ sc->memmap[ASPEED_DEV_TIMER1]);
+ for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
+ irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
+ }
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--=20
2.25.1