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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org
Subject: [PATCH 09/13] target/i386: do not use gen_op_jz_ecx for repeated
string operations
Date: Sun, 15 Dec 2024 10:06:08 +0100
Message-ID: <20241215090613.89588-10-pbonzini@redhat.com>
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Explicitly generate a TSTEQ branch (which is optimized to NE x,0 if possibl=
e).
This does not make much sense yet, but later we will add more checks and so=
me
will use a temporary to check on the decremented value of CX/ECX/RCX; it wi=
ll
be clearer for all checks to share the same logic using TSTEQ(reg, cx_mask).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4b53a47000e..8ef938372d5 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1336,6 +1336,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
bool is_repz_nz)
{
TCGLabel *done =3D gen_new_label();
+ target_ulong cx_mask =3D MAKE_64BIT_MASK(0, 8 << s->aflag);
bool had_rf =3D s->flags & HF_RF_MASK;
=20
/*
@@ -1358,7 +1359,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
tcg_set_insn_start_param(s->base.insn_start, 1, CC_OP_DYNAMIC);
=20
/* Any iteration at all? */
- gen_op_jz_ecx(s, done);
+ tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cpu_regs[R_ECX], cx_mask, done);
=20
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
--=20
2.47.1