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Tsirkin" , Marcel Apfelbaum Subject: [PATCH 45/71] hw/pci-bridge: Constify all Property Date: Fri, 13 Dec 2024 13:07:19 -0600 Message-ID: <20241213190750.2513964-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213190750.2513964-1-richard.henderson@linaro.org> References: <20241213190750.2513964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734117349386116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/cxl_root_port.c | 2 +- hw/pci-bridge/cxl_upstream.c | 2 +- hw/pci-bridge/gen_pcie_root_port.c | 2 +- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 4 ++-- hw/pci-bridge/pcie_pci_bridge.c | 2 +- hw/pci-bridge/pcie_root_port.c | 2 +- hw/pci-bridge/xio3130_downstream.c | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index c347ac06f3..cfe50e60e9 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -212,7 +212,7 @@ static void cxl_dsp_exitfn(PCIDevice *d) pci_bridge_exitfn(d); } =20 -static Property cxl_dsp_props[] =3D { +static const Property cxl_dsp_props[] =3D { DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 5e2156d7ba..5824ba3c75 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -199,7 +199,7 @@ static void cxl_rp_reset_hold(Object *obj, ResetType ty= pe) latch_registers(crp); } =20 -static Property gen_rp_props[] =3D { +static const Property gen_rp_props[] =3D { DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1), DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1), DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref,= -1), diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index 55f8b0053f..ef94aa3654 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -362,7 +362,7 @@ static void cxl_usp_exitfn(PCIDevice *d) pci_bridge_exitfn(d); } =20 -static Property cxl_upstream_props[] =3D { +static const Property cxl_upstream_props[] =3D { DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename), DEFINE_PROP_PCIE_LINK_SPEED("x-speed", CXLUpstreamPort, diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index 784507c826..c319ca8263 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -128,7 +128,7 @@ static const VMStateDescription vmstate_rp_dev =3D { } }; =20 -static Property gen_rp_props[] =3D { +static const Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true), DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 8e7f926621..35a37e056a 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -168,7 +168,7 @@ static void qdev_pci_bridge_dev_reset(DeviceState *qdev) } } =20 -static Property pci_bridge_dev_properties[] =3D { +static const Property pci_bridge_dev_properties[] =3D { /* Note: 0 is not a legal chassis number. */ DEFINE_PROP_UINT8(PCI_BRIDGE_DEV_PROP_CHASSIS_NR, PCIBridgeDev, chassi= s_nr, 0), diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 07d411cff5..01997c1ab3 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -420,7 +420,7 @@ static void pxb_dev_exitfn(PCIDevice *pci_dev) pxb_dev_list =3D g_list_remove(pxb_dev_list, pxb); } =20 -static Property pxb_dev_properties[] =3D { +static const Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), @@ -507,7 +507,7 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error *= *errp) pxb_cxl_dev_reset(DEVICE(dev)); } =20 -static Property pxb_cxl_dev_properties[] =3D { +static const Property pxb_cxl_dev_properties[] =3D { DEFINE_PROP_BOOL("hdm_for_passthrough", PXBCXLDev, hdm_for_passthrough= , false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index 6e8d7d9478..8834ff3dbf 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -124,7 +124,7 @@ static void pcie_pci_bridge_write_config(PCIDevice *d, shpc_cap_write_config(d, address, val, len); } =20 -static Property pcie_pci_bridge_dev_properties[] =3D { +static const Property pcie_pci_bridge_dev_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUT= O), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 09a34786bc..a7f87a1bc4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -148,7 +148,7 @@ static void rp_exit(PCIDevice *d) pci_bridge_exitfn(d); } =20 -static Property rp_props[] =3D { +static const Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 473e2dd950..92e5fb72ec 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -134,7 +134,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d) pci_bridge_exitfn(d); } =20 -static Property xio3130_downstream_props[] =3D { +static const Property xio3130_downstream_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_END_OF_LIST() --=20 2.43.0