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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c80162ddsm87026f8f.37.2024.12.13.09.33.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 09:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734111239; x=1734716039; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HbH6mKs94rPic6KcGRGG3fOmwu2HnUwrKyb75JHn04c=; b=SQIjs+L6YGrJHgAU1OQSx92ysQmyuSVUQ/Opwk6gylrFM5nQqrHTJtRTUGj/jsRWMR X3HgHrNloKaK76Tix/cgKxgCa6tdCJZL8RInjVVimSnJeIdQclzNdshoEW6xPvdrqjDD pKzd0iUNGYJhKe3tnhxW7aHN5d7VjcQsvJO4n+wFBEqDwWH0qqo/kAa0pqsyJZdWw0SD SnInlPxqx+IISuLHxFhtcHEL25qe6jgmvZOygsurtvGl55IfYHd3dxQurmA+z/98KYN0 b3qnfyvUTYeg2bT31/7uzCF+E8OFu4DB/5yc/c1M20dWMIR3jVcYJcoXKBsvmvfEdel1 3trA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734111239; x=1734716039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HbH6mKs94rPic6KcGRGG3fOmwu2HnUwrKyb75JHn04c=; b=AuJN6wM5d5Xoi0Mx/J3aybhdTmnJcHhPdNLiFJgk8Y+YV517tn09Q7rfF5FkMDjwV1 feEqdrTXHSQjgrxoKeednZSjmsITZpVJSuTEyVactj8aHuO4JrTckkmgTjZu9tX2ewrp tb6Y5g2ImG+QVyl0xYiX7sODLnsZVmsAfnJO1U2lSG6WB7fwbZv25VIiX8xLHmjXyLfV FyHGaa/vR/Ex87ChsiuRiKvLGxiaD5mi342V+/CjBT6ymwEVNohXkuEYFpN/k51eetH8 0/XNfEefCuoZRBHHQo2Ha4u0219hp2MUrq3BchVfIRnNjNLtZ9nlqj8PBuNL0qdvy6+x SGCw== X-Gm-Message-State: AOJu0YxiIE+GehLTd0XKbQLF9kTdIbhhoTepVd9sxJf/Xln3cp0tTv16 2gMGp0aA9LewvYmrbjksFzHckD0rGGLDrjRCRiQgXLv70QCLS2Aky4ybChuDVLQDYIwQjQYiefH J X-Gm-Gg: ASbGncvLVk48troUav6PP8B6wI2A6D9F3ut28RbF8d3MzB4BZNuocoXP0wwC7uALCxf TDZ7elwrW8oqpIQpZGswg88rqcnXBQNX3b5YqKeM0BBYQhYMJ+m0XMCGMVDB1Aukyt04E/nHbIo nyY81ydK09G/71tVQHxbBcezknNCS4A3HgWaNF2ALJtsfGXWfByvV3svuOOkeO6cyAgcbETgoLq KTnEfGepYd3dpLD7kLqCrFfrExckdcxV+wH36NZPubH7MnmUfk5lGHUa5v5Ug== X-Google-Smtp-Source: AGHT+IHm2zNGr3i1Wi1op9upFRSQLuzA/2qUVR+6/Kirg+w/2WeX8EdqiOQFnyOLL7Wge6KF+i5hMQ== X-Received: by 2002:a5d:588b:0:b0:385:f062:c2d4 with SMTP id ffacd0b85a97d-3888e0b87d6mr3065477f8f.37.1734111238730; Fri, 13 Dec 2024 09:33:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 82/85] target/arm: Move the TLBI OS insns to tlb-insns.c. Date: Fri, 13 Dec 2024 17:32:26 +0000 Message-Id: <20241213173229.3308926-83-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734111555819116600 Content-Type: text/plain; charset="utf-8" Move the TLBI OS insns across to tlb-insns.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241210160452.2427965-8-peter.maydell@linaro.org --- target/arm/helper.c | 80 -------------------------------------- target/arm/tcg/tlb-insns.c | 80 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 80 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 376aa9aecd5..3f7d56e809f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7116,83 +7116,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, }; =20 -static const ARMCPRegInfo tlbios_reginfo[] =3D { - { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .fgt =3D FGT_TLBIVMALLE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .fgt =3D FGT_TLBIVAE1OS, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .fgt =3D FGT_TLBIASIDE1OS, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .fgt =3D FGT_TLBIVAAE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .fgt =3D FGT_TLBIVALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, - .fgt =3D FGT_TLBIVAALE1OS, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, -}; - static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -9066,9 +8989,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } - if (cpu_isar_feature(aa64_tlbios, cpu)) { - define_arm_cp_regs(cpu, tlbios_reginfo); - } /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { define_one_arm_cp_reg(cpu, dcpop_reg); diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index a273c6f4b58..45ebfc512f9 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -884,6 +884,83 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_rvae3_write }, }; + +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVMALLE1OS, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, + .fgt =3D FGT_TLBIVAE1OS, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIASIDE1OS, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAAE1OS, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVALE1OS, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7, + .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_= RAW, + .fgt =3D FGT_TLBIVAALE1OS, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, + { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, +}; #endif =20 void define_tlb_insn_regs(ARMCPU *cpu) @@ -919,5 +996,8 @@ void define_tlb_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #endif } --=20 2.34.1