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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c80162ddsm87026f8f.37.2024.12.13.09.33.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 09:33:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734111236; x=1734716036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IXb1EyNQgSAc6Jv9qKhwJUtQcVIW/R0AFPQfAJk+WHA=; b=mJgSUrxah3PyldZzAeRCjzVEEX0UdEwRzGjj4lpWqx1YVxinOCVtLwVjlrdIkQb6GR pSYI0WIye6bZD+YYgzRGjuSyiW7jMDvlPvAUcP56FPBd0w0SpP1vCe3icKRvAwlo6cL1 h+J3lL7P0gQxxzoGaM/G96/0e8LnxZ7s0AJhwCGRH8NJdGb/3oWusfw7SwKgURpAWy2y YF/wXQq4qSPj17rV+sXwv4Oq/mtdWY3rXFWiNXtUT4aY1cTGHv2gi+B4vX4Lcq68c6W+ 1SWecXJ5E/tXzyAFMpoxRekdAsFoSagTxfZpeoMJUqzhZ4WbR0efoisi9PBsDO8bXAog JJAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734111236; x=1734716036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IXb1EyNQgSAc6Jv9qKhwJUtQcVIW/R0AFPQfAJk+WHA=; b=PRb+CCE3KBAyljrkosNBJ7gJA4hfls4NDEULrTWarOVeOOnG4TKtVRvcjB36rckwdD xZTS4pPQT9Z2k6mj+bo3Fe+Wz0PO5wZbH7a8rMNo9vkhNpyUa64kVX3VdhyQapoai8aT aMF9F9TOPyc8MYfqSn18BtiY+2e+6jIuqwWMWrVQWLxRCjSDXOuTvnyvCMEn5p5nGkFg DUUpjiEp0FvLKCgXXd1bMFrdWVGkEiednTDFjBvPZOfr7RxUr23i3w6WEi2qIPzDl/Gd pQJVWc5W4JLcQ82caLdLa4R89WOAsW6RLozErM9ysjVygPBJKFy+FfB3WOxMbXtaL3NA Y2MA== X-Gm-Message-State: AOJu0Yx22j/YFRUKlA/vlnxfG447sCT9yxEVmSOS8kWMrKxXaalZ8YHA IFhdphS5Zsz9tnEGJCg5FbSyoPBeyau/jKJ2nz90AAZIyo/iSR1A0YLGAE7R8y0xzteDZgc9vxZ 2 X-Gm-Gg: ASbGncta3grH+zbU9ID/IOCXBveLN/WyD/Vjb33Qlq+Z3ur+jTdMekpmzlY+XqtdQ8Z cuYML07dzSDUn6qj3R5G0esJA4SR+SNY1m18efW1Odh6qumRHpoHYE0CCIxvWlsqLeHMDXsnNWT 1/ijYGZrQ9k6kuvG047YWzJEOqEXF0SIW6Y63ygTpvtj2QgyQZBcX41CeXYHZXlo14eQ+MBN/Bu 8tVlEaB2yYCcC+/1Y02WV8TpJ9Isw2z9YgatUuFjw/M6PsTkI155UeCMHh/Bw== X-Google-Smtp-Source: AGHT+IGncxJurxxsGHHDefbTBbgDD9nMjfSz1VAywkL71pejKCVbBHfhMU3IRw01cPbakVvyktwFHg== X-Received: by 2002:a05:600c:1c09:b0:435:edb0:5d27 with SMTP id 5b1f17b1804b1-436230bfd93mr63250495e9.9.1734111235781; Fri, 13 Dec 2024 09:33:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 79/85] target/arm: Move the AArch64 EL2 TLBI insns Date: Fri, 13 Dec 2024 17:32:23 +0000 Message-Id: <20241213173229.3308926-80-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734111980227116600 Content-Type: text/plain; charset="utf-8" Move the AArch64 EL2 TLBI insn definitions that were in el2_cp_reginfo[] across to tlb-insns.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241210160452.2427965-5-peter.maydell@linaro.org --- target/arm/cpregs.h | 7 +++++ target/arm/helper.c | 61 ++++---------------------------------- target/arm/tcg/tlb-insns.c | 49 ++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 55 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index a14f5bb6c98..57446ae1b52 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1146,13 +1146,20 @@ bool tlb_force_broadcast(CPUARMState *env); int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr); int vae1_tlbbits(CPUARMState *env, uint64_t addr); +int vae2_tlbbits(CPUARMState *env, uint64_t addr); int vae1_tlbmask(CPUARMState *env); +int vae2_tlbmask(CPUARMState *env); int ipas2e1_tlbmask(CPUARMState *env, int64_t value); +int e2_tlbmask(CPUARMState *env); void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); +void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); +void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); =20 #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cc7da7f1159..6942d2f2fb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4705,7 +4705,7 @@ int vae1_tlbmask(CPUARMState *env) return mask; } =20 -static int vae2_tlbmask(CPUARMState *env) +int vae2_tlbmask(CPUARMState *env) { uint64_t hcr =3D arm_hcr_el2_eff(env); uint16_t mask; @@ -4748,7 +4748,7 @@ int vae1_tlbbits(CPUARMState *env, uint64_t addr) return tlbbits_for_regime(env, mmu_idx, addr); } =20 -static int vae2_tlbbits(CPUARMState *env, uint64_t addr) +int vae2_tlbbits(CPUARMState *env, uint64_t addr) { uint64_t hcr =3D arm_hcr_el2_eff(env); ARMMMUIdx mmu_idx; @@ -4776,7 +4776,7 @@ void tlbi_aa64_vmalle1is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 -static int e2_tlbmask(CPUARMState *env) +int e2_tlbmask(CPUARMState *env) { return (ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | @@ -4784,15 +4784,6 @@ static int e2_tlbmask(CPUARMState *env) ARMMMUIdxBit_E2); } =20 -static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D e2_tlbmask(env); - - tlb_flush_by_mmuidx(cs, mask); -} - static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4811,8 +4802,8 @@ void tlbi_aa64_alle1is_write(CPUARMState *env, const = ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } =20 -static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) +void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { CPUState *cs =3D env_cpu(env); int mask =3D e2_tlbmask(env); @@ -4828,22 +4819,6 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); } =20 -static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA, EL2 - * Currently handles both VAE2 and VALE2, since we don't support - * flush-last-level-only. - */ - CPUState *cs =3D env_cpu(env); - int mask =3D vae2_tlbmask(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D vae2_tlbbits(env, pageaddr); - - tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); -} - static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4870,7 +4845,7 @@ void tlbi_aa64_vae1is_write(CPUARMState *env, const A= RMCPRegInfo *ri, tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); } =20 -static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, +void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs =3D env_cpu(env); @@ -6036,30 +6011,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, - { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2_write }, - { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, - .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY /* * Unlike the other EL2-related AT operations, these must diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index ff7698e31b6..1eebb6055ce 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -191,6 +191,31 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, mask); } =20 +static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D e2_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + +static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA, EL2 + * Currently handles both VAE2 and VALE2, since we don't support + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae2_tlbmask(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + int bits =3D vae2_tlbbits(env, pageaddr); + + tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); +} + static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -460,6 +485,30 @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D { { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, .writefn =3D tlbimva_hyp_is_write }, + { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_alle2_write }, + { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2is_write }, + { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, + .writefn =3D tlbi_aa64_vae2is_write }, }; =20 void define_tlb_insn_regs(ARMCPU *cpu) --=20 2.34.1