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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/85] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree
Date: Fri, 13 Dec 2024 17:31:07 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/a64.decode | 4 +++
target/arm/tcg/translate-a64.c | 46 ++++++++++++++++------------------
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index c218f6afbcc..3db55b78a65 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -658,6 +658,10 @@ CPYE 00 011 1 01100 ..... .... 01 ..... ...=
.. @cpy
=20
UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
SDIV . 00 11010110 ..... 00001 1 ..... ..... @rrr_sf
+LSLV . 00 11010110 ..... 00100 0 ..... ..... @rrr_sf
+LSRV . 00 11010110 ..... 00100 1 ..... ..... @rrr_sf
+ASRV . 00 11010110 ..... 00101 0 ..... ..... @rrr_sf
+RORV . 00 11010110 ..... 00101 1 ..... ..... @rrr_sf
=20
# Data Processing (1-source)
# Logical (shifted reg)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9f687ba840a..8b7ca2c68ad 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7575,6 +7575,23 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src=
, int sf,
}
}
=20
+static bool do_shift_reg(DisasContext *s, arg_rrr_sf *a,
+ enum a64_shift_type shift_type)
+{
+ TCGv_i64 tcg_shift =3D tcg_temp_new_i64();
+ TCGv_i64 tcg_rd =3D cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rn =3D read_cpu_reg(s, a->rn, a->sf);
+
+ tcg_gen_andi_i64(tcg_shift, cpu_reg(s, a->rm), a->sf ? 63 : 31);
+ shift_reg(tcg_rd, tcg_rn, a->sf, shift_type, tcg_shift);
+ return true;
+}
+
+TRANS(LSLV, do_shift_reg, a, A64_SHIFT_TYPE_LSL)
+TRANS(LSRV, do_shift_reg, a, A64_SHIFT_TYPE_LSR)
+TRANS(ASRV, do_shift_reg, a, A64_SHIFT_TYPE_ASR)
+TRANS(RORV, do_shift_reg, a, A64_SHIFT_TYPE_ROR)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8456,19 +8473,6 @@ static void disas_data_proc_1src(DisasContext *s, ui=
nt32_t insn)
}
=20
=20
-/* LSLV, LSRV, ASRV, RORV */
-static void handle_shift_reg(DisasContext *s,
- enum a64_shift_type shift_type, unsigned int =
sf,
- unsigned int rm, unsigned int rn, unsigned in=
t rd)
-{
- TCGv_i64 tcg_shift =3D tcg_temp_new_i64();
- TCGv_i64 tcg_rd =3D cpu_reg(s, rd);
- TCGv_i64 tcg_rn =3D read_cpu_reg(s, rn, sf);
-
- tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
- shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
-}
-
/* CRC32[BHWX], CRC32C[BHWX] */
static void handle_crc32(DisasContext *s,
unsigned int sf, unsigned int sz, bool crc32c,
@@ -8579,18 +8583,6 @@ static void disas_data_proc_2src(DisasContext *s, ui=
nt32_t insn)
tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
}
break;
- case 8: /* LSLV */
- handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
- break;
- case 9: /* LSRV */
- handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
- break;
- case 10: /* ASRV */
- handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
- break;
- case 11: /* RORV */
- handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
- break;
case 12: /* PACGA */
if (sf =3D=3D 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
@@ -8616,6 +8608,10 @@ static void disas_data_proc_2src(DisasContext *s, ui=
nt32_t insn)
do_unallocated:
case 2: /* UDIV */
case 3: /* SDIV */
+ case 8: /* LSLV */
+ case 9: /* LSRV */
+ case 10: /* ASRV */
+ case 11: /* RORV */
unallocated_encoding(s);
break;
}
--=20
2.34.1