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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 36/85] target/arm: Convert ABS, NEG to decodetree
Date: Fri, 13 Dec 2024 17:31:40 +0000
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Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/a64.decode | 4 +++
target/arm/tcg/translate-a64.c | 46 +++++++++++++++++++++++-----------
2 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 17ecdac9dbd..f112951df72 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1632,8 +1632,12 @@ SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..=
... @shri_s
=20
SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
+ABS_s 0101 1110 111 00000 10111 0 ..... ..... @rr
+NEG_s 0111 1110 111 00000 10111 0 ..... ..... @rr
=20
# Advanced SIMD two-register miscellaneous
=20
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
+ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e
+NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9bb9668d111..c697f0e9441 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8889,6 +8889,33 @@ static const ENVScalar1 f_scalar_sqneg =3D {
TRANS(SQNEG_s, do_env_scalar1, a, &f_scalar_sqneg)
TRANS(SQNEG_v, do_env_vector1, a, &f_scalar_sqneg)
=20
+static bool do_scalar1_d(DisasContext *s, arg_rr *a, ArithOneOp *f)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 t =3D read_fp_dreg(s, a->rn);
+ f(t, t);
+ write_fp_dreg(s, a->rd, t);
+ }
+ return true;
+}
+
+TRANS(ABS_s, do_scalar1_d, a, tcg_gen_abs_i64)
+TRANS(NEG_s, do_scalar1_d, a, tcg_gen_neg_i64)
+
+static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
+{
+ if (!a->q && a->esz =3D=3D MO_64) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
+ }
+ return true;
+}
+
+TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
+TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9213,13 +9240,6 @@ static void handle_2misc_64(DisasContext *s, int opc=
ode, bool u,
case 0x9: /* CMEQ, CMLE */
cond =3D u ? TCG_COND_LE : TCG_COND_EQ;
goto do_cmop;
- case 0xb: /* ABS, NEG */
- if (u) {
- tcg_gen_neg_i64(tcg_rd, tcg_rn);
- } else {
- tcg_gen_abs_i64(tcg_rd, tcg_rn);
- }
- break;
case 0x2f: /* FABS */
gen_vfp_absd(tcg_rd, tcg_rn);
break;
@@ -9264,6 +9284,7 @@ static void handle_2misc_64(DisasContext *s, int opco=
de, bool u,
break;
default:
case 0x7: /* SQABS, SQNEG */
+ case 0xb: /* ABS, NEG */
g_assert_not_reached();
}
}
@@ -9614,7 +9635,6 @@ static void disas_simd_scalar_two_reg_misc(DisasConte=
xt *s, uint32_t insn)
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
- case 0xb: /* ABS, NEG */
if (size !=3D 3) {
unallocated_encoding(s);
return;
@@ -9705,6 +9725,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte=
xt *s, uint32_t insn)
default:
case 0x3: /* USQADD / SUQADD */
case 0x7: /* SQABS / SQNEG */
+ case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
}
@@ -10103,7 +10124,6 @@ static void disas_simd_two_reg_misc(DisasContext *s=
, uint32_t insn)
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
- case 0xb: /* ABS, NEG */
if (size =3D=3D 3 && !is_q) {
unallocated_encoding(s);
return;
@@ -10280,6 +10300,7 @@ static void disas_simd_two_reg_misc(DisasContext *s=
, uint32_t insn)
default:
case 0x3: /* SUQADD, USQADD */
case 0x7: /* SQABS, SQNEG */
+ case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
}
@@ -10324,12 +10345,7 @@ static void disas_simd_two_reg_misc(DisasContext *=
s, uint32_t insn)
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0xb:
- if (u) { /* ABS, NEG */
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
- }
- return;
+ g_assert_not_reached();
}
=20
if (size =3D=3D 3) {
--=20
2.34.1