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Fri, 13 Dec 2024 09:32:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/85] target/arm: Convert SETF8, SETF16 to decodetree Date: Fri, 13 Dec 2024 17:31:21 +0000 Message-Id: <20241213173229.3308926-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734111696608116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20241211163036.2297116-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 4 +++ target/arm/tcg/translate-a64.c | 48 +++++----------------------------- 2 files changed, 11 insertions(+), 41 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 454494742e6..ae2c6831d77 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -757,6 +757,10 @@ SBCS . 11 11010000 ..... 000000 ..... .....= @rrr_sf RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4 =20 # Evaluate into flags + +SETF8 0 01 11010000 00000 000010 rn:5 01101 +SETF16 0 01 11010000 00000 010010 rn:5 01101 + # Conditional compare (regster) # Conditional compare (immediate) # Conditional select diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1af41e22eb5..774689641d0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8077,38 +8077,21 @@ static bool trans_RMIF(DisasContext *s, arg_RMIF *a) return true; } =20 -/* - * Evaluate into flags - * 31 30 29 21 15 14 10 5 4 0 - * +--+--+--+-----------------+---------+----+---------+------+--+------+ - * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | - * +--+--+--+-----------------+---------+----+---------+------+--+------+ - */ -static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) +static bool do_setf(DisasContext *s, int rn, int shift) { - int o3_mask =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int o2 =3D extract32(insn, 15, 6); - int sz =3D extract32(insn, 14, 1); - int sf_op_s =3D extract32(insn, 29, 3); - TCGv_i32 tmp; - int shift; + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - if (sf_op_s !=3D 1 || o2 !=3D 0 || o3_mask !=3D 0xd || - !dc_isar_feature(aa64_condm_4, s)) { - unallocated_encoding(s); - return; - } - shift =3D sz ? 16 : 24; /* SETF16 or SETF8 */ - - tmp =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); tcg_gen_shli_i32(cpu_NF, tmp, shift); tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); tcg_gen_mov_i32(cpu_ZF, cpu_NF); tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); + return true; } =20 +TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24) +TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16) + /* Conditional compare (immediate / register) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 = 0 * +--+--+--+------------------------+--------+------+----+--+------+--+--= ---+ @@ -8277,30 +8260,12 @@ static void disas_data_proc_reg(DisasContext *s, ui= nt32_t insn) { int op1 =3D extract32(insn, 28, 1); int op2 =3D extract32(insn, 21, 4); - int op3 =3D extract32(insn, 10, 6); =20 if (!op1) { goto do_unallocated; } =20 switch (op2) { - case 0x0: - switch (op3) { - case 0x02: /* Evaluate into flags */ - case 0x12: - case 0x22: - case 0x32: - disas_evaluate_into_flags(s, insn); - break; - - default: - case 0x00: /* Add/subtract (with carry) */ - case 0x01: /* Rotate right into flags */ - case 0x21: - goto do_unallocated; - } - break; - case 0x2: /* Conditional compare */ disas_cc(s, insn); /* both imm and reg forms */ break; @@ -8311,6 +8276,7 @@ static void disas_data_proc_reg(DisasContext *s, uint= 32_t insn) =20 default: do_unallocated: + case 0x0: case 0x6: /* Data-processing */ case 0x8 ... 0xf: /* (3 source) */ unallocated_encoding(s); --=20 2.34.1