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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-388c80162ddsm87026f8f.37.2024.12.13.09.32.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 09:32:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734111165; x=1734715965; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sFYMlM2q6ifWyTSOYq7MTYvofuvINKuts8GiQDOUAdE=; b=ZR1R/NWGCiD9CdvH9FjKsWVd/EZ8nkkuPlcud5uDS9jzEu4gPUMMTOJUI+XTV63bXE HHane3TKZkp1sdE87i+JgwsZ64Rkk17S7vgm/Pb2nglPif2AcuXZwMWuF1NWizVvpdJl GepDoYSMLdxjUa5QCi3o16gbKASe3EoKHvDvpncsGQaL7L1/5+cGllv85o+UiAxoGCi4 sQJitD+/rOqDpJtXfoXecHb5IUTgStGabQuyifdD1I2xGFKqPCq+uKUHY64zrfhOF474 PExCaBbVirqAOE5SOVuFVvJSX1rpPhCMXLTdFgfQX0HSxIbiFhtB4s5mZ794GGgAs4fq FJSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734111165; x=1734715965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sFYMlM2q6ifWyTSOYq7MTYvofuvINKuts8GiQDOUAdE=; b=XORMF2JB4G1/R0pPNsQ3gu0Af99cG8v65QhcJ+YNdXbVKDiQr24I8Egu+XNrDcIZu+ 7jDohFjX9DlmsBNUua+wp69VzCBfVpkSpmIuobkg46e6a+FXP/bUe5kZhT+CdfPGKcgw nYuvH7vYkURv8aUAfMyuBkISPVjyN09AfknP3TkyHcegeQpRHXjosiAQGZABBAyomhHs RIDb3j/dGGk3GkxMgprkVtWxxaaOE3J6xQ1nMF9B76fDfL26DOdTQOZIkY06XRlDes9k cmYWEYtPpjyhf7OnffRy2G6YX7NZAQD3HetxnHXZjiSgxOQK7KG3MQoBJQtDx1psE5Ky 8ayA== X-Gm-Message-State: AOJu0Ywv6TJrPXjqo9wpEaNlElRJXTIYLHOmMmEdXn6Woa8V5xDWFmMt aM8FAGIQ2N97BwVWZ35kHDEEwFGV1L9SjBNBiChGQWULvcWcGdARaASKLqzOzBAcJjME5XEUe+X K X-Gm-Gg: ASbGncvDxRo7co2Z3ByYc8VU6rpX8RgCbCon/7cy/kobhJWWQK+RrW+FBiv8q9fZUi1 usrfCuHUyHi+PGOikPm3bjyCaip0cVDxeMzLabJtdeq07MDqHBwq8hAV8EzvoecaB6zNO+moAcI vrPVXnJoHiEVmTgsDFMm5YnYA6QX4E0QCRixdb2RLb2c0S184uB6FmQk3jLrH/WulCYqTJBs/Dx 59uGQuNZAstIV08j2BOkiZMqJ06z/v9Y1dUlvOOPKT87NMVFO2GXbG1fty3WQ== X-Google-Smtp-Source: AGHT+IGh3ZEvKj5Vnx+IQGYzvyX7clRbII6+w0ra5WWQTWw9AV4k2ehy0jBaL+gozVBXzr9c9fw/lw== X-Received: by 2002:a05:6000:1886:b0:385:fd31:ca23 with SMTP id ffacd0b85a97d-3888e0b877amr2941352f8f.40.1734111164694; Fri, 13 Dec 2024 09:32:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/85] target/arm: Convert disas_add_sub_ext_reg to decodetree Date: Fri, 13 Dec 2024 17:31:16 +0000 Message-Id: <20241213173229.3308926-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734111282417116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes ADD, SUB, ADDS, SUBS (extended register). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20241211163036.2297116-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 9 +++++ target/arm/tcg/translate-a64.c | 65 +++++++++++----------------------- 2 files changed, 29 insertions(+), 45 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8e2949d2361..05396945062 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -727,6 +727,15 @@ ANDS_r . 11 01010 .. . ..... ...... ..... ...= .. @logic_shift =20 # Add/subtract (shifted reg) # Add/subtract (extended reg) + +&addsub_ext rd rn rm sf sa st +@addsub_ext sf:1 .. ........ rm:5 st:3 sa:3 rn:5 rd:5 &addsub_ext + +ADD_ext . 00 01011001 ..... ... ... ..... ..... @addsub_ext +SUB_ext . 10 01011001 ..... ... ... ..... ..... @addsub_ext +ADDS_ext . 01 01011001 ..... ... ... ..... ..... @addsub_ext +SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext + # Add/subtract (carry) # Rotate right into flags # Evaluate into flags diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ecc8899dd84..8f777875fe0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -7864,57 +7864,27 @@ TRANS(AND_r, do_logic_reg, a, tcg_gen_and_i64, tcg_= gen_andc_i64, false) TRANS(ANDS_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, true) TRANS(EOR_r, do_logic_reg, a, tcg_gen_xor_i64, tcg_gen_eqv_i64, false) =20 -/* - * Add/subtract (extended register) - * - * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| - * +--+--+--+-----------+-----+--+-------+------+------+----+----+ - * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | - * +--+--+--+-----------+-----+--+-------+------+------+----+----+ - * - * sf: 0 -> 32bit, 1 -> 64bit - * op: 0 -> add , 1 -> sub - * S: 1 -> set flags - * opt: 00 - * option: extension type (see DecodeRegExtend) - * imm3: optional shift to Rm - * - * Rd =3D Rn + LSL(extend(Rm), amount) - */ -static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) +static bool do_addsub_ext(DisasContext *s, arg_addsub_ext *a, + bool sub_op, bool setflags) { - int rd =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int imm3 =3D extract32(insn, 10, 3); - int option =3D extract32(insn, 13, 3); - int rm =3D extract32(insn, 16, 5); - int opt =3D extract32(insn, 22, 2); - bool setflags =3D extract32(insn, 29, 1); - bool sub_op =3D extract32(insn, 30, 1); - bool sf =3D extract32(insn, 31, 1); + TCGv_i64 tcg_rm, tcg_rn, tcg_rd, tcg_result; =20 - TCGv_i64 tcg_rm, tcg_rn; /* temps */ - TCGv_i64 tcg_rd; - TCGv_i64 tcg_result; - - if (imm3 > 4 || opt !=3D 0) { - unallocated_encoding(s); - return; + if (a->sa > 4) { + return false; } =20 /* non-flag setting ops may use SP */ if (!setflags) { - tcg_rd =3D cpu_reg_sp(s, rd); + tcg_rd =3D cpu_reg_sp(s, a->rd); } else { - tcg_rd =3D cpu_reg(s, rd); + tcg_rd =3D cpu_reg(s, a->rd); } - tcg_rn =3D read_cpu_reg_sp(s, rn, sf); + tcg_rn =3D read_cpu_reg_sp(s, a->rn, a->sf); =20 - tcg_rm =3D read_cpu_reg(s, rm, sf); - ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); + tcg_rm =3D read_cpu_reg(s, a->rm, a->sf); + ext_and_shift_reg(tcg_rm, tcg_rm, a->st, a->sa); =20 tcg_result =3D tcg_temp_new_i64(); - if (!setflags) { if (sub_op) { tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); @@ -7923,19 +7893,25 @@ static void disas_add_sub_ext_reg(DisasContext *s, = uint32_t insn) } } else { if (sub_op) { - gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); + gen_sub_CC(a->sf, tcg_result, tcg_rn, tcg_rm); } else { - gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); + gen_add_CC(a->sf, tcg_result, tcg_rn, tcg_rm); } } =20 - if (sf) { + if (a->sf) { tcg_gen_mov_i64(tcg_rd, tcg_result); } else { tcg_gen_ext32u_i64(tcg_rd, tcg_result); } + return true; } =20 +TRANS(ADD_ext, do_addsub_ext, a, false, false) +TRANS(SUB_ext, do_addsub_ext, a, true, false) +TRANS(ADDS_ext, do_addsub_ext, a, false, true) +TRANS(SUBS_ext, do_addsub_ext, a, true, true) + /* * Add/subtract (shifted register) * @@ -8374,8 +8350,7 @@ static void disas_data_proc_reg(DisasContext *s, uint= 32_t insn) if (!op1) { if (op2 & 8) { if (op2 & 1) { - /* Add/sub (extended register) */ - disas_add_sub_ext_reg(s, insn); + goto do_unallocated; } else { /* Add/sub (shifted register) */ disas_add_sub_reg(s, insn); --=20 2.34.1