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Subject: [PATCH v5 1/8] i386: Add Intel RDT device and State to config.
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
zhao1.liu@intel.com, xiaoyao.li@intel.com
Cc: peternewman@google.com,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Change config to show RDT, add minimal code to the rdt.c module to make
sure things still compile.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
hw/i386/Kconfig | 4 ++
hw/i386/meson.build | 1 +
hw/i386/rdt.c | 99 +++++++++++++++++++++++++++++++++++++++++++
include/hw/i386/rdt.h | 25 +++++++++++
target/i386/cpu.h | 3 ++
5 files changed, 132 insertions(+)
create mode 100644 hw/i386/rdt.c
create mode 100644 include/hw/i386/rdt.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 32818480d2..0186b85c3e 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -10,6 +10,9 @@ config SGX
bool
depends on KVM
=20
+config RDT
+ bool
+
config PC
bool
imply APPLESMC
@@ -26,6 +29,7 @@ config PC
imply QXL
imply SEV
imply SGX
+ imply RDT
imply TEST_DEVICES
imply TPM_CRB
imply TPM_TIS_ISA
diff --git a/hw/i386/meson.build b/hw/i386/meson.build
index 10bdfde27c..3a697dcc03 100644
--- a/hw/i386/meson.build
+++ b/hw/i386/meson.build
@@ -22,6 +22,7 @@ i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport=
.c'))
i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c'))
i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'),
if_false: files('sgx-stub.c'))
+i386_ss.add(when: 'CONFIG_RDT', if_true: files('rdt.c'))
=20
i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c'))
i386_ss.add(when: 'CONFIG_PC', if_true: files(
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
new file mode 100644
index 0000000000..b2203197e3
--- /dev/null
+++ b/hw/i386/rdt.c
@@ -0,0 +1,99 @@
+/*
+ * Intel Resource Director Technology (RDT).
+ *
+ * Copyright 2024 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WIT=
HOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/i386/rdt.h"
+#include "qemu/osdep.h" /* Needs to be included before isa.h */
+#include "hw/isa/isa.h"
+#include "hw/qdev-properties.h"
+#include "qom/object.h"
+
+/* Max counts for allocation masks or CBMs. In other words, the size of
+ * respective MSRs.
+ * L3_MASK and L3_mask are architectural limitations. THRTL_COUNT is just
+ * the space left until the next MSR.
+ * */
+#define RDT_MAX_L3_MASK_COUNT 127
+#define RDT_MAX_L2_MASK_COUNT 63
+#define RDT_MAX_MBA_THRTL_COUNT 63
+
+#define TYPE_RDT "rdt"
+#define RDT_NUM_RMID_PROP "rmids"
+
+OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT);
+
+struct RDTMonitor {
+ uint64_t count_local;
+ uint64_t count_remote;
+ uint64_t count_l3;
+};
+
+struct RDTAllocation {
+ uint32_t active_cos;
+};
+
+struct RDTStatePerCore {
+ uint32_t active_rmid;
+ GArray *monitors;
+
+ /*Parent RDTState*/
+ RDTState *rdtstate;
+};
+
+/*One instance of RDT-internal state to be shared by all cores*/
+struct RDTState {
+ ISADevice parent;
+
+ /*Max amount of RMIDs*/
+ uint32_t rmids;
+
+ /*Per core state*/
+ RDTStatePerCore *rdtInstances;
+ RDTAllocation *allocations;
+
+ /*RDT Allocation bitmask MSRs*/
+ uint32_t msr_L3_ia32_mask_n[RDT_MAX_L3_MASK_COUNT];
+ uint32_t msr_L2_ia32_mask_n[RDT_MAX_L2_MASK_COUNT];
+ uint32_t ia32_L2_qos_ext_bw_thrtl_n[RDT_MAX_MBA_THRTL_COUNT];
+};
+
+struct RDTStateClass {
+};
+
+OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE);
+
+static Property rdt_properties[] =3D {
+ DEFINE_PROP_UINT32(RDT_NUM_RMID_PROP, RDTState, rmids, 256),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rdt_init(Object *obj)
+{
+}
+
+static void rdt_finalize(Object *obj)
+{
+}
+
+static void rdt_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->hotpluggable =3D false;
+ dc->desc =3D "RDT";
+ dc->user_creatable =3D true;
+
+ device_class_set_props(dc, rdt_properties);
+}
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
new file mode 100644
index 0000000000..a21d95b265
--- /dev/null
+++ b/include/hw/i386/rdt.h
@@ -0,0 +1,25 @@
+/*
+ * Intel Resource Director Technology (RDT).
+ *
+ * Copyright 2024 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WIT=
HOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef HW_RDT_H
+#define HW_RDT_H
+
+typedef struct RDTState RDTState;
+typedef struct RDTStatePerCore RDTStatePerCore;
+typedef struct RDTMonitor RDTMonitor;
+typedef struct RDTAllocation RDTAllocation;
+
+#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 4c239a6970..0f73c1244d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2213,6 +2213,9 @@ struct ArchCPU {
struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
Notifier machine_done;
=20
+ /* Help the RDT MSRs find the RDT device */
+ struct RDTStatePerCore *rdt;
+
struct kvm_msrs *kvm_msr_buf;
=20
int32_t node_id; /* NUMA node this CPU belongs to */
--=20
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Subject: [PATCH v5 2/8] i386: Add init and realize functionality for RDT
device.
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Add code to initialize all necessary state for the RDT device.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
hw/i386/rdt.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index b2203197e3..920e9c5dbe 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -19,6 +19,7 @@
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
+#include "target/i386/cpu.h"
=20
/* Max counts for allocation masks or CBMs. In other words, the size of
* respective MSRs.
@@ -83,8 +84,36 @@ static void rdt_init(Object *obj)
{
}
=20
+static void rdt_realize(DeviceState *dev, Error **errp)
+{
+ CPUState *cs =3D first_cpu;
+ RDTState *rdtDev =3D RDT(dev);
+
+ rdtDev->rdtInstances =3D g_malloc(sizeof(RDTStatePerCore) * cs->nr_cor=
es);
+ CPU_FOREACH(cs) {
+ RDTStatePerCore *rdt =3D &rdtDev->rdtInstances[cs->cpu_index];
+ X86CPU *cpu =3D X86_CPU(cs);
+
+ rdt->rdtstate =3D rdtDev;
+ cpu->rdt =3D rdt;
+
+ rdt->monitors =3D g_malloc(sizeof(RDTMonitor) * rdtDev->rmids);
+ rdt->rdtstate->allocations =3D g_malloc(sizeof(RDTAllocation) * rd=
tDev->rmids);
+ }
+}
+
static void rdt_finalize(Object *obj)
{
+ CPUState *cs;
+ RDTState *rdt =3D RDT(obj);
+
+ CPU_FOREACH(cs) {
+ RDTStatePerCore *rdtInstance =3D &rdt->rdtInstances[cs->cpu_index];
+ g_free(rdtInstance->monitors);
+ g_free(rdtInstance->rdtstate->allocations);
+ }
+
+ g_free(rdt->rdtInstances);
}
=20
static void rdt_class_init(ObjectClass *klass, void *data)
@@ -94,6 +123,7 @@ static void rdt_class_init(ObjectClass *klass, void *dat=
a)
dc->hotpluggable =3D false;
dc->desc =3D "RDT";
dc->user_creatable =3D true;
+ dc->realize =3D rdt_realize;
=20
device_class_set_props(dc, rdt_properties);
}
--=20
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Subject: [PATCH v5 3/8] i386: Add RDT functionality
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Add RDT code to Associate CLOSID with RMID / set RMID for monitoring,
write COS, and read monitoring data. This patch does not add code for
the guest to interact through these things with MSRs, only the actual
ability for the RDT device to do them.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
hw/i386/rdt.c | 123 ++++++++++++++++++++++++++++++++++++++++++
include/hw/i386/rdt.h | 16 ++++++
2 files changed, 139 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 920e9c5dbe..01bee79cbe 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -21,6 +21,11 @@
#include "qom/object.h"
#include "target/i386/cpu.h"
=20
+/* RDT Monitoring Event Codes */
+#define RDT_EVENT_L3_OCCUPANCY 1
+#define RDT_EVENT_L3_REMOTE_BW 2
+#define RDT_EVENT_L3_LOCAL_BW 3
+
/* Max counts for allocation masks or CBMs. In other words, the size of
* respective MSRs.
* L3_MASK and L3_mask are architectural limitations. THRTL_COUNT is just
@@ -33,6 +38,9 @@
#define TYPE_RDT "rdt"
#define RDT_NUM_RMID_PROP "rmids"
=20
+#define QM_CTR_ERROR (1ULL << 63)
+#define QM_CTR_UNAVAILABLE (1ULL << 62)
+
OBJECT_DECLARE_TYPE(RDTState, RDTStateClass, RDT);
=20
struct RDTMonitor {
@@ -73,6 +81,121 @@ struct RDTState {
struct RDTStateClass {
};
=20
+bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+ RDTAllocation *alloc;
+
+ uint32_t cos_id =3D (msr_ia32_pqr_assoc & 0xffff0000) >> 16;
+ uint32_t rmid =3D msr_ia32_pqr_assoc & 0xffff;
+
+ if (cos_id > RDT_MAX_L3_MASK_COUNT || cos_id > RDT_MAX_L2_MASK_COUNT ||
+ cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) {
+ return false;
+ }
+
+ rdt->active_rmid =3D rmid;
+
+ alloc =3D &rdt->rdtstate->allocations[rmid];
+
+ alloc->active_cos =3D cos_id;
+
+ return true;
+}
+
+uint32_t rdt_read_l3_mask(uint32_t pos)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ return rdt->rdtstate->msr_L3_ia32_mask_n[pos];
+}
+
+uint32_t rdt_read_l2_mask(uint32_t pos)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ return rdt->rdtstate->msr_L2_ia32_mask_n[pos];
+}
+
+uint32_t rdt_read_mba_thrtl(uint32_t pos)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ return rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos];
+}
+
+void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ rdt->rdtstate->msr_L3_ia32_mask_n[pos] =3D val;
+}
+
+void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ rdt->rdtstate->msr_L2_ia32_mask_n[pos] =3D val;
+}
+
+void rdt_write_mba_thrtl(uint32_t pos, uint32_t val)
+{
+ X86CPU *cpu =3D X86_CPU(current_cpu);
+ RDTStatePerCore *rdt =3D cpu->rdt;
+
+ rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos] =3D val;
+}
+
+uint32_t rdt_max_rmid(RDTStatePerCore *rdt)
+{
+ RDTState *rdtdev =3D rdt->rdtstate;
+ return rdtdev->rmids - 1;
+}
+
+uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance,
+ uint32_t rmid, uint32_t event_id)
+{
+ CPUState *cs;
+ RDTMonitor *mon;
+ RDTState *rdt =3D rdtInstance->rdtstate;
+
+ uint32_t count_l3 =3D 0;
+ uint32_t count_local =3D 0;
+ uint32_t count_remote =3D 0;
+
+ if (!rdt) {
+ return 0;
+ }
+
+ CPU_FOREACH(cs) {
+ rdtInstance =3D &rdt->rdtInstances[cs->cpu_index];
+ if (rmid >=3D rdtInstance->monitors->len) {
+ return QM_CTR_ERROR;
+ }
+ mon =3D &g_array_index(rdtInstance->monitors, RDTMonitor, rmid);
+ count_l3 +=3D mon->count_l3;
+ count_local +=3D mon->count_local;
+ count_remote +=3D mon->count_remote;
+ }
+
+ switch (event_id) {
+ case RDT_EVENT_L3_OCCUPANCY:
+ return count_l3 =3D=3D 0 ? QM_CTR_UNAVAILABLE : count_l3;
+ case RDT_EVENT_L3_REMOTE_BW:
+ return count_remote =3D=3D 0 ? QM_CTR_UNAVAILABLE : count_remote;
+ case RDT_EVENT_L3_LOCAL_BW:
+ return count_local =3D=3D 0 ? QM_CTR_UNAVAILABLE : count_local;
+ default:
+ return QM_CTR_ERROR;
+ }
+}
+
OBJECT_DEFINE_TYPE(RDTState, rdt, RDT, ISA_DEVICE);
=20
static Property rdt_properties[] =3D {
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index a21d95b265..14b1c64b72 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -17,9 +17,25 @@
#ifndef HW_RDT_H
#define HW_RDT_H
=20
+#include <stdbool.h>
+#include <stdint.h>
+
typedef struct RDTState RDTState;
typedef struct RDTStatePerCore RDTStatePerCore;
typedef struct RDTMonitor RDTMonitor;
typedef struct RDTAllocation RDTAllocation;
=20
+bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
+
+void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val);
+void rdt_write_msr_l2_mask(uint32_t pos, uint32_t val);
+void rdt_write_mba_thrtl(uint32_t pos, uint32_t val);
+
+uint32_t rdt_read_l3_mask(uint32_t pos);
+uint32_t rdt_read_l2_mask(uint32_t pos);
+uint32_t rdt_read_mba_thrtl(uint32_t pos);
+
+uint64_t rdt_read_event_count(RDTStatePerCore *rdt, uint32_t rmid, uint32_=
t event_id);
+uint32_t rdt_max_rmid(RDTStatePerCore *rdt);
+
#endif
--=20
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Subject: [PATCH v5 4/8] i386: Add RDT device interface through MSRs
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID / set an active RMID for
monitoring, read monitoring data, and set classes of service.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
hw/i386/rdt.c | 4 ++
include/hw/i386/rdt.h | 4 ++
target/i386/cpu.h | 14 +++++
target/i386/tcg/sysemu/misc_helper.c | 81 ++++++++++++++++++++++++++++
4 files changed, 103 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 01bee79cbe..3a37341bd6 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -81,6 +81,10 @@ struct RDTState {
struct RDTStateClass {
};
=20
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COU=
NT; }
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COU=
NT; }
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return RDT_MAX_MBA_THRTL_C=
OUNT; }
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc)
{
X86CPU *cpu =3D X86_CPU(current_cpu);
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index 14b1c64b72..ec82a149f2 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -25,6 +25,10 @@ typedef struct RDTStatePerCore RDTStatePerCore;
typedef struct RDTMonitor RDTMonitor;
typedef struct RDTAllocation RDTAllocation;
=20
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void);
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
=20
void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0f73c1244d..64a53efa30 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -576,6 +576,17 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
=20
+#define MSR_IA32_QM_EVTSEL 0x0c8d
+#define MSR_IA32_QM_CTR 0x0c8e
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+
+#define MSR_IA32_L3_CBM_BASE 0x0c90
+#define MSR_IA32_L3_MASKS_END 0x0d0f
+#define MSR_IA32_L2_CBM_BASE 0x0d10
+#define MSR_IA32_L2_CBM_END 0x0d4f
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd8f
+
#define MSR_APIC_START 0x00000800
#define MSR_APIC_END 0x000008ff
=20
@@ -1839,6 +1850,9 @@ typedef struct CPUArchState {
uint64_t msr_ia32_feature_control;
uint64_t msr_ia32_sgxlepubkeyhash[4];
=20
+ uint64_t msr_ia32_qm_evtsel;
+ uint64_t msr_ia32_pqr_assoc;
+
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;
uint64_t msr_global_status;
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/=
misc_helper.c
index 094aa56a20..a6c6b11a29 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -25,6 +25,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
+#include "hw/i386/rdt.h"
#include "hw/i386/apic.h"
=20
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
@@ -293,6 +294,45 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs =3D val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_QM_EVTSEL:
+ env->msr_ia32_qm_evtsel =3D val;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ env->msr_ia32_pqr_assoc =3D val;
+
+ if (!rdt_associate_rmid_cos(val))
+ goto error;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_1_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l3_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_2_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l2_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrt=
l_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_=
BW_Thrtl_BASE;
+
+ if (pos > rdt_get_cpuid_10_3_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_mba_thrtl(pos, val);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
@@ -472,6 +512,47 @@ void helper_rdmsr(CPUX86State *env)
val =3D (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
break;
}
+ case MSR_IA32_QM_CTR:
+ val =3D rdt_read_event_count(x86_cpu->rdt,
+ (env->msr_ia32_qm_evtsel >> 32) & 0xff,
+ env->msr_ia32_qm_evtsel & 0xff);
+ break;
+ case MSR_IA32_QM_EVTSEL:
+ val =3D env->msr_ia32_qm_evtsel;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ val =3D env->msr_ia32_pqr_assoc;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos >=3D rdt_get_cpuid_10_1_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val =3D rdt_read_l3_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos >=3D rdt_get_cpuid_10_2_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val =3D rdt_read_l2_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ... MSR_IA32_L2_QOS_Ext_BW_Thrt=
l_END:
+ {
+ uint32_t pos =3D (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_QOS_Ext_=
BW_Thrtl_BASE;
+
+ if (pos >=3D rdt_get_cpuid_10_3_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val =3D rdt_read_mba_thrtl(pos);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
--=20
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Subject: [PATCH v5 5/8] i386: Add CPUID enumeration for RDT
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
zhao1.liu@intel.com, xiaoyao.li@intel.com
Cc: peternewman@google.com,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Add CPUID enumeration for intel RDT monitoring and allocation, as well
as the flags used in the enumeration code.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
hw/i386/rdt.c | 30 ++++++++++++++++++
include/hw/i386/rdt.h | 31 +++++++++++++++++++
target/i386/cpu.c | 71 +++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 5 +++
4 files changed, 137 insertions(+)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 3a37341bd6..7c9170559d 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -35,6 +35,17 @@
#define RDT_MAX_L2_MASK_COUNT 63
#define RDT_MAX_MBA_THRTL_COUNT 63
=20
+/* RDT L3 Allocation features */
+#define CPUID_10_1_EAX_CBM_LENGTH 0xf
+#define CPUID_10_1_EBX_CBM 0x0
+#define CPUID_10_1_ECX_CDP 0x0 // to enable, it would be (1U =
<< 2)
+/* RDT L2 Allocation features*/
+#define CPUID_10_2_EAX_CBM_LENGTH 0xf
+#define CPUID_10_2_EBX_CBM 0x0
+/* RDT MBA features */
+#define CPUID_10_3_EAX_THRTL_MAX 89
+#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2)
+
#define TYPE_RDT "rdt"
#define RDT_NUM_RMID_PROP "rmids"
=20
@@ -81,8 +92,27 @@ struct RDTState {
struct RDTStateClass {
};
=20
+uint32_t rdt_get_cpuid_F_0_edx_l3(void) { return CPUID_F_1_EDX_L3_OCCUPANC=
Y | CPUID_F_1_EDX_L3_TOTAL_BW | CPUID_F_1_EDX_L3_LOCAL_BW; }
+
+uint32_t rdt_cpuid_F_1_edx_l3_total_bw_enabled(void) { return CPUID_F_1_ED=
X_L3_TOTAL_BW; }
+uint32_t rdt_cpuid_F_1_edx_l3_local_bw_enabled(void) { return CPUID_F_1_ED=
X_L3_LOCAL_BW; }
+uint32_t rdt_cpuid_F_1_edx_l3_occupancy_enabled(void) { return CPUID_F_1_E=
DX_L3_OCCUPANCY; }
+
+uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void) { return CPUID_10_0_EBX_L=
3_CAT; }
+uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void) { return CPUID_10_0_EBX_L=
2_CAT; }
+uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void) { return CPUID_10_0_EBX_M=
BA; }
+
+uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void) { return CPUID_10_1_EAX_C=
BM_LENGTH; }
+uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void) { return CPUID_10_1_EBX_CBM;=
}
+uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void) { return CPUID_10_1_ECX_CDP;=
}
uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COU=
NT; }
+
+uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void) { return CPUID_10_2_EAX_C=
BM_LENGTH; }
+uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void) { return CPUID_10_2_EBX_CBM;=
}
uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COU=
NT; }
+
+uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void) { return CPUID_10_3_EAX_TH=
RTL_MAX; }
+uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void) { return CPUID_1=
0_3_ECX_LINEAR_RESPONSE; }
uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return RDT_MAX_MBA_THRTL_C=
OUNT; }
=20
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc)
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index ec82a149f2..859fb4871c 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -20,13 +20,44 @@
#include <stdbool.h>
#include <stdint.h>
=20
+/* RDT L3 Cache Monitoring Technology */
+#define CPUID_F_0_EDX_L3 (1U << 1)
+#define CPUID_F_1_EDX_L3_OCCUPANCY (1U << 0)
+#define CPUID_F_1_EDX_L3_TOTAL_BW (1U << 1)
+#define CPUID_F_1_EDX_L3_LOCAL_BW (1U << 2)
+
+/* RDT Cache Allocation Technology */
+#define CPUID_10_0_EBX_L3_CAT (1U << 1)
+#define CPUID_10_0_EBX_L2_CAT (1U << 2)
+#define CPUID_10_0_EBX_MBA (1U << 3)
+#define CPUID_10_0_EDX CPUID_10_0_EBX_L3_CAT | CPUID_10_0_EBX_L2_CAT | CPU=
ID_10_0_EBX_MBA
+
typedef struct RDTState RDTState;
typedef struct RDTStatePerCore RDTStatePerCore;
typedef struct RDTMonitor RDTMonitor;
typedef struct RDTAllocation RDTAllocation;
=20
+uint32_t rdt_get_cpuid_F_0_edx_l3(void);
+
+uint32_t rdt_cpuid_F_1_edx_l3_total_bw_enabled(void);
+uint32_t rdt_cpuid_F_1_edx_l3_local_bw_enabled(void);
+uint32_t rdt_cpuid_F_1_edx_l3_occupancy_enabled(void);
+
+uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void);
+uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void);
+uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void);
+
+uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void);
+uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void);
+uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void);
uint32_t rdt_get_cpuid_10_1_edx_cos_max(void);
+
+uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void);
+uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void);
uint32_t rdt_get_cpuid_10_2_edx_cos_max(void);
+
+uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void);
+uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void);
uint32_t rdt_get_cpuid_10_3_edx_cos_max(void);
=20
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3725dbbc4b..c6e6cff19d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -41,6 +41,7 @@
#include "hw/boards.h"
#include "hw/i386/sgx-epc.h"
#endif
+#include "hw/i386/rdt.h"
=20
#include "disas/capstone.h"
#include "cpu-internal.h"
@@ -6725,6 +6726,76 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,=
uint32_t count,
assert(!(*eax & ~0x1f));
*ebx &=3D 0xffff; /* The count doesn't need to be reliable. */
break;
+#ifndef CONFIG_USER_ONLY
+ case 0xF:
+ /* Shared Resource Monitoring Enumeration Leaf */
+ *eax =3D 0;
+ *ebx =3D 0;
+ *ecx =3D 0;
+ *edx =3D 0;
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM))
+ break;
+ if (!(cpu->rdt)) {
+ warn_report("Intel RDT features enabled in commandline, "
+ "but rdt device not used");
+ break;
+ }
+ /* Non-zero count is ResId */
+ switch (count) {
+ /* Monitoring Resource Type Enumeration */
+ case 0:
+ *edx =3D env->features[FEAT_RDT_F_0_EDX];
+ *ebx =3D rdt_max_rmid(cpu->rdt);
+ break;
+ case 1:
+ *ebx =3D 1;
+ *ecx =3D rdt_max_rmid(cpu->rdt);
+ *edx =3D rdt_cpuid_F_1_edx_l3_total_bw_enabled() |
+ rdt_cpuid_F_1_edx_l3_local_bw_enabled() |
+ rdt_cpuid_F_1_edx_l3_occupancy_enabled();
+ break;
+ }
+ break;
+ case 0x10:
+ /* Shared Resource Director Technology Allocation Enumeration Leaf=
*/
+ *eax =3D 0;
+ *ebx =3D 0;
+ *ecx =3D 0;
+ *edx =3D 0;
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE))
+ break;
+ if (!(cpu->rdt)) {
+ warn_report("Intel RDT features enabled in commandline, "
+ "but rdt device not used");
+ break;
+ }
+ /* Non-zero count is ResId */
+ switch (count) {
+ /* Cache Allocation Technology Available Resource Types */
+ case 0:
+ *ebx |=3D rdt_cpuid_10_0_ebx_l3_cat_enabled();
+ *ebx |=3D rdt_cpuid_10_0_ebx_l2_cat_enabled();
+ *ebx |=3D rdt_cpuid_10_0_ebx_l2_mba_enabled();
+ break;
+ case 1:
+ *eax =3D rdt_get_cpuid_10_1_eax_cbm_length();
+ *ebx =3D rdt_cpuid_10_1_ebx_cbm_enabled();
+ *ecx |=3D rdt_cpuid_10_1_ecx_cdp_enabled();
+ *edx =3D rdt_get_cpuid_10_1_edx_cos_max();
+ break;
+ case 2:
+ *eax =3D rdt_get_cpuid_10_2_eax_cbm_length();
+ *ebx =3D rdt_cpuid_10_2_ebx_cbm_enabled();
+ *edx =3D rdt_get_cpuid_10_2_edx_cos_max();
+ break;
+ case 3:
+ *eax =3D rdt_get_cpuid_10_3_eax_thrtl_max();
+ *ecx =3D rdt_cpuid_10_3_eax_linear_response_enabled();
+ *edx =3D rdt_get_cpuid_10_3_edx_cos_max();
+ break;
+ }
+ break;
+#endif
case 0x1C:
if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED=
X_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 64a53efa30..a1ec2d5dde 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -678,6 +678,7 @@ typedef enum FeatureWord {
FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */
FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */
FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */
+ FEAT_RDT_F_0_EDX, /* CPUID[EAX=3D0xf,ECX=3D0].EDX (RDT CMT/MBM) */
FEATURE_WORDS,
} FeatureWord;
=20
@@ -852,8 +853,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp=
u, FeatureWord w);
#define CPUID_7_0_EBX_RTM (1U << 11)
/* Zero out FPU CS and FPU DS */
#define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13)
+/* Resource Director Technology Monitoring */
+#define CPUID_7_0_EBX_PQM (1U << 12)
/* Memory Protection Extension */
#define CPUID_7_0_EBX_MPX (1U << 14)
+/* Resource Director Technology Allocation */
+#define CPUID_7_0_EBX_PQE (1U << 15)
/* AVX-512 Foundation */
#define CPUID_7_0_EBX_AVX512F (1U << 16)
/* AVX-512 Doubleword & Quadword Instruction */
--=20
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Subject: [PATCH v5 6/8] i386: Add RDT feature flags.
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Add RDT features to feature word / TCG.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
target/i386/cpu.c | 30 ++++++++++++++++++++++++++++--
target/i386/cpu.h | 2 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c6e6cff19d..6f14d6fc62 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -869,7 +869,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo=
r1,
CPUID_7_0_EBX_CLFLUSHOPT | \
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE =
| \
CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED |=
\
- CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES)
+ CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \
+ CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE)
/* missing:
CPUID_7_0_EBX_HLE
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
@@ -906,6 +907,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo=
r1,
#define TCG_SGX_12_0_EBX_FEATURES 0
#define TCG_SGX_12_1_EAX_FEATURES 0
#define TCG_24_0_EBX_FEATURES 0
+#define TCG_RDT_F_0_EDX_FEATURES CPUID_F_0_EDX_L3
=20
#if defined CONFIG_USER_ONLY
#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
@@ -1063,7 +1065,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D {
"fsgsbase", "tsc-adjust", "sgx", "bmi1",
"hle", "avx2", "fdp-excptn-only", "smep",
"bmi2", "erms", "invpcid", "rtm",
- NULL, "zero-fcs-fds", "mpx", NULL,
+ "rdt-m", "zero-fcs-fds", "mpx", "rdt-a",
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
"clwb", "intel-pt", "avx512pf", "avx512er",
@@ -1651,6 +1653,30 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D=
{
},
.tcg_features =3D TCG_SGX_12_1_EAX_FEATURES,
},
+
+ [FEAT_RDT_10_0_EBX] =3D {
+ .type =3D CPUID_FEATURE_WORD,
+ .feat_names =3D {
+ NULL, "l3-cat", "l2-cat", "mba"
+ },
+ .cpuid =3D {
+ .eax =3D 0x10,
+ .needs_ecx =3D true, .ecx =3D 0,
+ .reg =3D R_EBX,
+ }
+ },
+ [FEAT_RDT_F_0_EDX] =3D {
+ .type =3D CPUID_FEATURE_WORD,
+ .feat_names =3D {
+ [1] =3D "l3-cmt"
+ },
+ .cpuid =3D {
+ .eax =3D 0xf,
+ .needs_ecx =3D true, .ecx =3D 0,
+ .reg =3D R_EDX,
+ },
+ .tcg_features =3D TCG_RDT_F_0_EDX_FEATURES,
+ },
};
=20
typedef struct FeatureMask {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a1ec2d5dde..2b5a5986de 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -678,7 +678,9 @@ typedef enum FeatureWord {
FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */
FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */
FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */
+ FEAT_RDT_F_0_EBX, /* CPUID[EAX=3D0xf,ECX=3D0].EBX (RDT CMT/MBM) */
FEAT_RDT_F_0_EDX, /* CPUID[EAX=3D0xf,ECX=3D0].EDX (RDT CMT/MBM) */
+ FEAT_RDT_10_0_EBX, /* CPUID[EAX=3D0x10,ECX=3D0].EBX (RDT CAT/MBA) */
FEATURE_WORDS,
} FeatureWord;
=20
--=20
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Subject: [PATCH v5 7/8] i386/cpu: Adjust CPUID level for RDT features
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
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Cc: peternewman@google.com,
"=?UTF-8?q?=E2=80=AAHendrik=20W=C3=BCthrich?=" <whendrik@google.com>
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Adjust minimum CPUID level if RDT monitoring or allocation features are
enabled to ensure that CPUID will return them.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6f14d6fc62..f7904870ed 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7719,6 +7719,16 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er=
rp)
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
}
+
+ /* RDT monitoring requires CPUID[0xF] */
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM) {
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0xF);
+ }
+
+ /* RDT allocation requires CPUID[0x10] */
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE) {
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x10);
+ }
}
=20
/* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set =
*/
--=20
2.47.1.613.gc27f4b7a9f-goog
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Subject: [PATCH v5 8/8] i386/cpu: Adjust level for RDT on
full_cpuid_auto_level
From: Hendrik Wuethrich <whendrik@google.com>
To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org,
marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com,
zhao1.liu@intel.com, xiaoyao.li@intel.com
Cc: peternewman@google.com,
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From: =E2=80=AAHendrik W=C3=BCthrich <whendrik@google.com>
Make sure that RDT monitoring and allocation features are included in
in full_cpuid_auto_level.
Signed-off-by: Hendrik W=C3=BCthrich <whendrik@google.com>
---
target/i386/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f7904870ed..4f1493043e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -880,6 +880,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo=
r1,
#else
#define TCG_7_0_ECX_RDPID 0
#endif
+
#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
/* CPUID_7_0_ECX_OSPKE is dynamic */ \
CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
@@ -7672,6 +7673,8 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err=
p)
x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
+ x86_cpu_adjust_feat_level(cpu, FEAT_RDT_F_0_EDX);
+ x86_cpu_adjust_feat_level(cpu, FEAT_RDT_10_0_EBX);
=20
/* Intel Processor Trace requires CPUID[0x14] */
if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
--=20
2.47.1.613.gc27f4b7a9f-goog