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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, peter.maydell@linaro.org,
quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng,
quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
Brian Cain <bcain@oss.qualcomm.com>
Subject: [PULL 1/5] Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG
Date: Thu, 12 Dec 2024 20:18:32 -0800
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From: Taylor Simpson <ltaylorsimpson@gmail.com>
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/README | 9 ---
target/hexagon/cpu.h | 6 --
target/hexagon/genptr.c | 7 ---
target/hexagon/helper.h | 3 -
target/hexagon/internal.h | 11 ----
target/hexagon/op_helper.c | 112 -------------------------------------
target/hexagon/translate.c | 66 ----------------------
target/hexagon/translate.h | 2 -
8 files changed, 216 deletions(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index 7ffd517d70..ca617e3364 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -282,10 +282,6 @@ For Hexagon Vector eXtensions (HVX), the following fie=
lds are used
=20
*** Debugging ***
=20
-You can turn on a lot of debugging by changing the HEX_DEBUG macro to 1 in
-internal.h. This will stream a lot of information as it generates TCG and
-executes the code.
-
To track down nasty issues with Hexagon->TCG generation, we compare the
execution results with actual hardware running on a Hexagon Linux target.
Run qemu with the "-d cpu" option. Then, we can diff the results and figu=
re
@@ -305,8 +301,3 @@ Here are some handy places to set breakpoints
The helper function for each instruction is named helper_<TAG>, so her=
e's
an example that will set a breakpoint at the start
br helper_A2_add
- If you have the HEX_DEBUG macro set, the following will be useful
- At the start of execution of a packet for a given PC
- br helper_debug_start_packet if env->gpr[41] =3D=3D 0xdeadbeef
- At the end of execution of a packet for a given PC
- br helper_debug_commit_end if this_PC =3D=3D 0xdeadbeef
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 764f3c38cc..25150d5214 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -79,12 +79,6 @@ typedef struct CPUArchState {
uint8_t slot_cancelled;
target_ulong new_value_usr;
=20
- /*
- * Only used when HEX_DEBUG is on, but unconditionally included
- * to reduce recompile time when turning HEX_DEBUG on/off.
- */
- target_ulong reg_written[TOTAL_PER_THREAD_REGS];
-
MemLog mem_log_stores[STORES_MAX];
=20
float_status fp_status;
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index dbae6c570a..2c5e15cfcf 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -100,10 +100,6 @@ void gen_log_reg_write(DisasContext *ctx, int rnum, TC=
Gv val)
=20
gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val);
- if (HEX_DEBUG) {
- /* Do this so HELPER(debug_commit_end) will know */
- tcg_gen_movi_tl(hex_reg_written[rnum], 1);
- }
}
=20
static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 v=
al)
@@ -151,9 +147,6 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TC=
Gv val)
} else {
tcg_gen_and_tl(pred, pred, base_val);
}
- if (HEX_DEBUG) {
- tcg_gen_ori_tl(ctx->pred_written, ctx->pred_written, 1 << pnum);
- }
set_bit(pnum, ctx->pregs_written);
}
=20
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index fa0ebaf7c8..f8baa599c8 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -19,9 +19,6 @@
#include "helper_protos_generated.h.inc"
=20
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
-DEF_HELPER_1(debug_start_packet, void, env)
-DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int=
, int)
-DEF_HELPER_FLAGS_5(debug_commit_end, TCG_CALL_NO_WG, void, env, i32, int, =
int, int)
DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_3(gather_store, void, env, i32, int)
DEF_HELPER_1(commit_hvx_stores, void, env)
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index beb08cb7e3..32e96f00d9 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -20,17 +20,6 @@
=20
#include "qemu/log.h"
=20
-/*
- * Change HEX_DEBUG to 1 to turn on debugging output
- */
-#define HEX_DEBUG 0
-#define HEX_DEBUG_LOG(...) \
- do { \
- if (HEX_DEBUG) { \
- qemu_log(__VA_ARGS__); \
- } \
- } while (0)
-
int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int =
n);
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 90e7aaa097..01d1a1b1a7 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -54,9 +54,6 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *=
env, uint32_t excp)
void log_store32(CPUHexagonState *env, target_ulong addr,
target_ulong val, int width, int slot)
{
- HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
- ", %" PRId32 " [0x08%" PRIx32 "])\n",
- width, addr, val, val);
env->mem_log_stores[slot].va =3D addr;
env->mem_log_stores[slot].width =3D width;
env->mem_log_stores[slot].data32 =3D val;
@@ -65,35 +62,11 @@ void log_store32(CPUHexagonState *env, target_ulong add=
r,
void log_store64(CPUHexagonState *env, target_ulong addr,
int64_t val, int width, int slot)
{
- HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
- ", %" PRId64 " [0x016%" PRIx64 "])\n",
- width, addr, val, val);
env->mem_log_stores[slot].va =3D addr;
env->mem_log_stores[slot].width =3D width;
env->mem_log_stores[slot].data64 =3D val;
}
=20
-/* Handy place to set a breakpoint */
-void HELPER(debug_start_packet)(CPUHexagonState *env)
-{
- HEX_DEBUG_LOG("Start packet: pc =3D 0x" TARGET_FMT_lx "\n",
- env->gpr[HEX_REG_PC]);
-
- for (int i =3D 0; i < TOTAL_PER_THREAD_REGS; i++) {
- env->reg_written[i] =3D 0;
- }
-}
-
-/* Checks for bookkeeping errors between disassembly context and runtime */
-void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int c=
heck)
-{
- if (env->mem_log_stores[slot].width !=3D check) {
- HEX_DEBUG_LOG("ERROR: %d !=3D %d\n",
- env->mem_log_stores[slot].width, check);
- g_assert_not_reached();
- }
-}
-
static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
{
uint8_t width =3D env->mem_log_stores[slot_num].width;
@@ -173,91 +146,6 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
}
}
=20
-static void print_store(CPUHexagonState *env, int slot)
-{
- if (!(env->slot_cancelled & (1 << slot))) {
- uint8_t width =3D env->mem_log_stores[slot].width;
- if (width =3D=3D 1) {
- uint32_t data =3D env->mem_log_stores[slot].data32 & 0xff;
- HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] =3D %" PRId32
- " (0x%02" PRIx32 ")\n",
- env->mem_log_stores[slot].va, data, data);
- } else if (width =3D=3D 2) {
- uint32_t data =3D env->mem_log_stores[slot].data32 & 0xffff;
- HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] =3D %" PRId32
- " (0x%04" PRIx32 ")\n",
- env->mem_log_stores[slot].va, data, data);
- } else if (width =3D=3D 4) {
- uint32_t data =3D env->mem_log_stores[slot].data32;
- HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] =3D %" PRId32
- " (0x%08" PRIx32 ")\n",
- env->mem_log_stores[slot].va, data, data);
- } else if (width =3D=3D 8) {
- HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] =3D %" PRId64
- " (0x%016" PRIx64 ")\n",
- env->mem_log_stores[slot].va,
- env->mem_log_stores[slot].data64,
- env->mem_log_stores[slot].data64);
- } else {
- HEX_DEBUG_LOG("\tBad store width %d\n", width);
- g_assert_not_reached();
- }
- }
-}
-
-/* This function is a handy place to set a breakpoint */
-void HELPER(debug_commit_end)(CPUHexagonState *env, uint32_t this_PC,
- int pred_written, int has_st0, int has_st1)
-{
- bool reg_printed =3D false;
- bool pred_printed =3D false;
- int i;
-
- HEX_DEBUG_LOG("Packet committed: pc =3D 0x" TARGET_FMT_lx "\n", this_P=
C);
- HEX_DEBUG_LOG("slot_cancelled =3D %d\n", env->slot_cancelled);
-
- for (i =3D 0; i < TOTAL_PER_THREAD_REGS; i++) {
- if (env->reg_written[i]) {
- if (!reg_printed) {
- HEX_DEBUG_LOG("Regs written\n");
- reg_printed =3D true;
- }
- HEX_DEBUG_LOG("\tr%d =3D " TARGET_FMT_ld " (0x" TARGET_FMT_lx =
")\n",
- i, env->gpr[i], env->gpr[i]);
- }
- }
-
- for (i =3D 0; i < NUM_PREGS; i++) {
- if (pred_written & (1 << i)) {
- if (!pred_printed) {
- HEX_DEBUG_LOG("Predicates written\n");
- pred_printed =3D true;
- }
- HEX_DEBUG_LOG("\tp%d =3D 0x" TARGET_FMT_lx "\n",
- i, env->pred[i]);
- }
- }
-
- if (has_st0 || has_st1) {
- HEX_DEBUG_LOG("Stores\n");
- if (has_st0) {
- print_store(env, 0);
- }
- if (has_st1) {
- print_store(env, 1);
- }
- }
-
- HEX_DEBUG_LOG("Next PC =3D " TARGET_FMT_lx "\n", env->gpr[HEX_REG_PC]);
- HEX_DEBUG_LOG("Exec counters: pkt =3D " TARGET_FMT_lx
- ", insn =3D " TARGET_FMT_lx
- ", hvx =3D " TARGET_FMT_lx "\n",
- env->gpr[HEX_REG_QEMU_PKT_CNT],
- env->gpr[HEX_REG_QEMU_INSN_CNT],
- env->gpr[HEX_REG_QEMU_HVX_CNT]);
-
-}
-
int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, int32_t M, int32_t C=
S)
{
uint32_t K_const =3D extract32(M, 24, 4);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 4b1bee3c6d..bce85eaeb8 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -50,7 +50,6 @@ TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
TCGv hex_pred[NUM_PREGS];
TCGv hex_slot_cancelled;
TCGv hex_new_value_usr;
-TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
TCGv hex_store_addr[STORES_MAX];
TCGv hex_store_width[STORES_MAX];
TCGv hex_store_val32[STORES_MAX];
@@ -195,21 +194,6 @@ static void gen_exception_end_tb(DisasContext *ctx, in=
t excp)
=20
}
=20
-#define PACKET_BUFFER_LEN 1028
-static void print_pkt(Packet *pkt)
-{
- GString *buf =3D g_string_sized_new(PACKET_BUFFER_LEN);
- snprint_a_pkt_debug(buf, pkt);
- HEX_DEBUG_LOG("%s", buf->str);
- g_string_free(buf, true);
-}
-#define HEX_DEBUG_PRINT_PKT(pkt) \
- do { \
- if (HEX_DEBUG) { \
- print_pkt(pkt); \
- } \
- } while (0)
-
static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
uint32_t words[])
{
@@ -235,14 +219,6 @@ static int read_packet_words(CPUHexagonState *env, Dis=
asContext *ctx,
g_assert(ctx->base.num_insns =3D=3D 1);
}
=20
- HEX_DEBUG_LOG("decode_packet: pc =3D 0x%" VADDR_PRIx "\n",
- ctx->base.pc_next);
- HEX_DEBUG_LOG(" words =3D { ");
- for (int i =3D 0; i < nwords; i++) {
- HEX_DEBUG_LOG("0x%x, ", words[i]);
- }
- HEX_DEBUG_LOG("}\n");
-
return nwords;
}
=20
@@ -465,11 +441,6 @@ static void gen_start_packet(DisasContext *ctx)
*/
bitmap_zero(ctx->pregs_written, NUM_PREGS);
=20
- if (HEX_DEBUG) {
- /* Handy place to set a breakpoint before the packet executes */
- gen_helper_debug_start_packet(tcg_env);
- }
-
/* Initialize the runtime state for packet semantics */
if (need_slot_cancelled(pkt)) {
tcg_gen_movi_tl(hex_slot_cancelled, 0);
@@ -484,10 +455,6 @@ static void gen_start_packet(DisasContext *ctx)
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
}
}
- if (HEX_DEBUG) {
- ctx->pred_written =3D tcg_temp_new();
- tcg_gen_movi_tl(ctx->pred_written, 0);
- }
=20
/* Preload the predicated registers into get_result_gpr(ctx, i) */
if (ctx->need_commit &&
@@ -635,15 +602,6 @@ static void gen_pred_writes(DisasContext *ctx)
}
}
=20
-static void gen_check_store_width(DisasContext *ctx, int slot_num)
-{
- if (HEX_DEBUG) {
- TCGv slot =3D tcg_constant_tl(slot_num);
- TCGv check =3D tcg_constant_tl(ctx->store_width[slot_num]);
- gen_helper_debug_check_store_width(tcg_env, slot, check);
- }
-}
-
static bool slot_is_predicated(Packet *pkt, int slot_num)
{
for (int i =3D 0; i < pkt->num_insns; i++) {
@@ -691,25 +649,21 @@ void process_store(DisasContext *ctx, int slot_num)
*/
switch (ctx->store_width[slot_num]) {
case 1:
- gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_UB);
break;
case 2:
- gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUW);
break;
case 4:
- gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUL);
break;
case 8:
- gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUQ);
@@ -937,16 +891,6 @@ static void gen_commit_packet(DisasContext *ctx)
gen_commit_hvx(ctx);
}
update_exec_counters(ctx);
- if (HEX_DEBUG) {
- TCGv has_st0 =3D
- tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa=
);
- TCGv has_st1 =3D
- tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa=
);
-
- /* Handy place to set a breakpoint at the end of execution */
- gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc),
- ctx->pred_written, has_st0, has_st1);
- }
=20
if (pkt->vhist_insn !=3D NULL) {
ctx->pre_commit =3D false;
@@ -975,7 +919,6 @@ static void decode_and_translate_packet(CPUHexagonState=
*env, DisasContext *ctx)
ctx->pkt =3D &pkt;
if (decode_packet(ctx, nwords, words, &pkt, false) > 0) {
pkt.pc =3D ctx->base.pc_next;
- HEX_DEBUG_PRINT_PKT(&pkt);
gen_start_packet(ctx);
for (i =3D 0; i < pkt.num_insns; i++) {
ctx->insn =3D &pkt.insn[i];
@@ -1093,7 +1036,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB=
lock *tb, int *max_insns,
}
=20
#define NAME_LEN 64
-static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
static char store_addr_names[STORES_MAX][NAME_LEN];
static char store_width_names[STORES_MAX][NAME_LEN];
static char store_val32_names[STORES_MAX][NAME_LEN];
@@ -1112,14 +1054,6 @@ void hexagon_translate_init(void)
hex_gpr[i] =3D tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, gpr[i]),
hexagon_regnames[i]);
-
- if (HEX_DEBUG) {
- snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
- hexagon_regnames[i]);
- hex_reg_written[i] =3D tcg_global_mem_new(tcg_env,
- offsetof(CPUHexagonState, reg_written[i]),
- reg_written_names[i]);
- }
}
hex_new_value_usr =3D tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 00cc2bcd63..d251e2233f 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -73,7 +73,6 @@ typedef struct DisasContext {
bool has_hvx_overlap;
TCGv new_value[TOTAL_PER_THREAD_REGS];
TCGv new_pred_value[NUM_PREGS];
- TCGv pred_written;
TCGv branch_taken;
TCGv dczero_addr;
} DisasContext;
@@ -271,7 +270,6 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
extern TCGv hex_pred[NUM_PREGS];
extern TCGv hex_slot_cancelled;
extern TCGv hex_new_value_usr;
-extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
extern TCGv hex_store_addr[STORES_MAX];
extern TCGv hex_store_width[STORES_MAX];
extern TCGv hex_store_val32[STORES_MAX];
--=20
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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, peter.maydell@linaro.org,
quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng,
quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
Brian Cain <bcain@quicinc.com>, Brian Cain <bcain@oss.qualcomm.com>,
Laurent Vivier <laurent@vivier.eu>
Subject: [PULL 2/5] target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*
Date: Thu, 12 Dec 2024 20:18:33 -0800
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From: Brian Cain <bcain@quicinc.com>
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
linux-user/hexagon/cpu_loop.c | 4 ++--
target/hexagon/cpu.h | 2 +-
target/hexagon/cpu_bits.h | 15 ++++++++-------
target/hexagon/gen_tcg.h | 2 +-
target/hexagon/translate.c | 6 +++---
5 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index d41159e52a..40db596301 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -42,7 +42,7 @@ void cpu_loop(CPUHexagonState *env)
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
- case HEX_EXCP_TRAP0:
+ case HEX_EVENT_TRAP0:
syscallnum =3D env->gpr[6];
env->gpr[HEX_REG_PC] +=3D 4;
ret =3D do_syscall(env,
@@ -60,7 +60,7 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] =3D ret;
}
break;
- case HEX_EXCP_PC_NOT_ALIGNED:
+ case HEX_CAUSE_PC_NOT_ALIGNED:
force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
env->gpr[HEX_REG_R31]);
break;
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 25150d5214..14e6e819c2 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -143,7 +143,7 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState=
*env, vaddr *pc,
}
*flags =3D hex_flags;
if (*pc & PCALIGN_MASK) {
- hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0);
+ hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
}
}
=20
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 4279281a71..2e60c0fafe 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -23,14 +23,15 @@
#define PCALIGN 4
#define PCALIGN_MASK (PCALIGN - 1)
=20
-#define HEX_EXCP_FETCH_NO_UPAGE 0x012
-#define HEX_EXCP_INVALID_PACKET 0x015
-#define HEX_EXCP_INVALID_OPCODE 0x015
-#define HEX_EXCP_PC_NOT_ALIGNED 0x01e
-#define HEX_EXCP_PRIV_NO_UREAD 0x024
-#define HEX_EXCP_PRIV_NO_UWRITE 0x025
+#define HEX_EVENT_TRAP0 0x008
=20
-#define HEX_EXCP_TRAP0 0x172
+#define HEX_CAUSE_TRAP0 0x172
+#define HEX_CAUSE_FETCH_NO_UPAGE 0x012
+#define HEX_CAUSE_INVALID_PACKET 0x015
+#define HEX_CAUSE_INVALID_OPCODE 0x015
+#define HEX_CAUSE_PC_NOT_ALIGNED 0x01e
+#define HEX_CAUSE_PRIV_NO_UREAD 0x024
+#define HEX_CAUSE_PRIV_NO_UWRITE 0x025
=20
#define PACKET_WORDS_MAX 4
=20
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 3fc1f4e281..8a3b801287 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1365,7 +1365,7 @@
do { \
uiV =3D uiV; \
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
- TCGv excp =3D tcg_constant_tl(HEX_EXCP_TRAP0); \
+ TCGv excp =3D tcg_constant_tl(HEX_EVENT_TRAP0); \
gen_helper_raise_exception(tcg_env, excp); \
} while (0)
#endif
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index bce85eaeb8..562105705a 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -558,7 +558,7 @@ static void gen_insn(DisasContext *ctx)
ctx->insn->generate(ctx);
mark_store_width(ctx);
} else {
- gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
+ gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE);
}
}
=20
@@ -912,7 +912,7 @@ static void decode_and_translate_packet(CPUHexagonState=
*env, DisasContext *ctx)
=20
nwords =3D read_packet_words(env, ctx, words);
if (!nwords) {
- gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
+ gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
return;
}
=20
@@ -927,7 +927,7 @@ static void decode_and_translate_packet(CPUHexagonState=
*env, DisasContext *ctx)
gen_commit_packet(ctx);
ctx->base.pc_next +=3D pkt.encod_pkt_size_in_bytes;
} else {
- gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
+ gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET);
}
}
=20
--=20
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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, peter.maydell@linaro.org,
quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng,
quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
Brian Cain <bcain@quicinc.com>, Brian Cain <bcain@oss.qualcomm.com>
Subject: [PULL 3/5] target/hexagon: add enums for event, cause
Date: Thu, 12 Dec 2024 20:18:34 -0800
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From: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/cpu_bits.h | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -23,15 +23,21 @@
#define PCALIGN 4
#define PCALIGN_MASK (PCALIGN - 1)
=20
-#define HEX_EVENT_TRAP0 0x008
+enum hex_event {
+ HEX_EVENT_NONE =3D -1,
+ HEX_EVENT_TRAP0 =3D 0x008,
+};
=20
-#define HEX_CAUSE_TRAP0 0x172
-#define HEX_CAUSE_FETCH_NO_UPAGE 0x012
-#define HEX_CAUSE_INVALID_PACKET 0x015
-#define HEX_CAUSE_INVALID_OPCODE 0x015
-#define HEX_CAUSE_PC_NOT_ALIGNED 0x01e
-#define HEX_CAUSE_PRIV_NO_UREAD 0x024
-#define HEX_CAUSE_PRIV_NO_UWRITE 0x025
+enum hex_cause {
+ HEX_CAUSE_NONE =3D -1,
+ HEX_CAUSE_TRAP0 =3D 0x172,
+ HEX_CAUSE_FETCH_NO_UPAGE =3D 0x012,
+ HEX_CAUSE_INVALID_PACKET =3D 0x015,
+ HEX_CAUSE_INVALID_OPCODE =3D 0x015,
+ HEX_CAUSE_PC_NOT_ALIGNED =3D 0x01e,
+ HEX_CAUSE_PRIV_NO_UREAD =3D 0x024,
+ HEX_CAUSE_PRIV_NO_UWRITE =3D 0x025,
+};
=20
#define PACKET_WORDS_MAX 4
=20
--=20
2.34.1
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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, peter.maydell@linaro.org,
quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng,
quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
Brian Cain <bcain@oss.qualcomm.com>
Subject: [PULL 4/5] target/hexagon: Use argparse in all python scripts
Date: Thu, 12 Dec 2024 20:18:35 -0800
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From: Anton Johansson <anjo@rev.ng>
QOL commit, all the various gen_* python scripts take a large set
arguments where order is implicit. Using argparse we also get decent
error messages if a field is missing or too many are added.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/gen_analyze_funcs.py | 6 +++--
target/hexagon/gen_decodetree.py | 19 +++++++++++---
target/hexagon/gen_helper_funcs.py | 7 +++---
target/hexagon/gen_helper_protos.py | 7 +++---
target/hexagon/gen_idef_parser_funcs.py | 11 +++++++--
target/hexagon/gen_op_attribs.py | 11 +++++++--
target/hexagon/gen_opcodes_def.py | 11 +++++++--
target/hexagon/gen_printinsn.py | 11 +++++++--
target/hexagon/gen_tcg_func_table.py | 11 +++++++--
target/hexagon/gen_tcg_funcs.py | 9 ++++---
target/hexagon/gen_trans_funcs.py | 18 +++++++++++---
target/hexagon/hex_common.py | 33 ++++++++++++-------------
target/hexagon/meson.build | 2 +-
13 files changed, 109 insertions(+), 47 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy=
ze_funcs.py
index 54bac19724..3ac7cc2cfe 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -78,11 +78,13 @@ def gen_analyze_func(f, tag, regs, imms):
=20
=20
def main():
- hex_common.read_common_files()
+ args =3D hex_common.parse_common_args(
+ "Emit functions analyzing register accesses"
+ )
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
f.write("#ifndef HEXAGON_ANALYZE_FUNCS_C_INC\n")
f.write("#define HEXAGON_ANALYZE_FUNCS_C_INC\n\n")
=20
diff --git a/target/hexagon/gen_decodetree.py b/target/hexagon/gen_decodetr=
ee.py
index a4fcd622c5..ce703af41d 100755
--- a/target/hexagon/gen_decodetree.py
+++ b/target/hexagon/gen_decodetree.py
@@ -24,6 +24,7 @@
import textwrap
import iset
import hex_common
+import argparse
=20
encs =3D {
tag: "".join(reversed(iset.iset[tag]["enc"].replace(" ", "")))
@@ -191,8 +192,18 @@ def gen_decodetree_file(f, class_to_decode):
f.write(f"{tag}\t{enc_str} @{tag}\n")
=20
=20
+def main():
+ parser =3D argparse.ArgumentParser(
+ description=3D"Emit opaque macro calls with instruction semantics"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("class_to_decode", help=3D"instruction class to de=
code")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+
+ hex_common.read_semantics_file(args.semantics)
+ with open(args.out, "w") as f:
+ gen_decodetree_file(f, args.class_to_decode)
+
if __name__ =3D=3D "__main__":
- hex_common.read_semantics_file(sys.argv[1])
- class_to_decode =3D sys.argv[2]
- with open(sys.argv[3], "w") as f:
- gen_decodetree_file(f, class_to_decode)
+ main()
diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper=
_funcs.py
index e9685bff2f..c1f806ac4b 100755
--- a/target/hexagon/gen_helper_funcs.py
+++ b/target/hexagon/gen_helper_funcs.py
@@ -102,12 +102,13 @@ def gen_helper_function(f, tag, tagregs, tagimms):
=20
=20
def main():
- hex_common.read_common_files()
+ args =3D hex_common.parse_common_args(
+ "Emit helper function definitions for each instruction"
+ )
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- output_file =3D sys.argv[-1]
- with open(output_file, "w") as f:
+ with open(args.out, "w") as f:
for tag in hex_common.tags:
## Skip the priv instructions
if "A_PRIV" in hex_common.attribdict[tag]:
diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helpe=
r_protos.py
index fd2bfd0f36..77f8e0a6a3 100755
--- a/target/hexagon/gen_helper_protos.py
+++ b/target/hexagon/gen_helper_protos.py
@@ -52,12 +52,13 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
=20
=20
def main():
- hex_common.read_common_files()
+ args =3D hex_common.parse_common_args(
+ "Emit helper function prototypes for each instruction"
+ )
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- output_file =3D sys.argv[-1]
- with open(output_file, "w") as f:
+ with open(args.out, "w") as f:
for tag in hex_common.tags:
## Skip the priv instructions
if "A_PRIV" in hex_common.attribdict[tag]:
diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_i=
def_parser_funcs.py
index 72f11c68ca..2f6e826f76 100644
--- a/target/hexagon/gen_idef_parser_funcs.py
+++ b/target/hexagon/gen_idef_parser_funcs.py
@@ -20,6 +20,7 @@
import sys
import re
import string
+import argparse
from io import StringIO
=20
import hex_common
@@ -43,13 +44,19 @@
## them are inputs ("in" prefix), while some others are outputs.
##
def main():
- hex_common.read_semantics_file(sys.argv[1])
+ parser =3D argparse.ArgumentParser(
+ "Emit instruction implementations that can be fed to idef-parser"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
hex_common.calculate_attribs()
hex_common.init_registers()
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
f.write('#include "macros.h.inc"\n\n')
=20
for tag in hex_common.tags:
diff --git a/target/hexagon/gen_op_attribs.py b/target/hexagon/gen_op_attri=
bs.py
index 99448220da..bbbb02df3a 100755
--- a/target/hexagon/gen_op_attribs.py
+++ b/target/hexagon/gen_op_attribs.py
@@ -21,16 +21,23 @@
import re
import string
import hex_common
+import argparse
=20
=20
def main():
- hex_common.read_semantics_file(sys.argv[1])
+ parser =3D argparse.ArgumentParser(
+ "Emit opaque macro calls containing instruction attributes"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
hex_common.calculate_attribs()
=20
##
## Generate all the attributes associated with each instruction
##
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
for tag in hex_common.tags:
f.write(
f"OP_ATTRIB({tag},ATTRIBS("
diff --git a/target/hexagon/gen_opcodes_def.py b/target/hexagon/gen_opcodes=
_def.py
index 536f0eb68a..94a19ff412 100755
--- a/target/hexagon/gen_opcodes_def.py
+++ b/target/hexagon/gen_opcodes_def.py
@@ -21,15 +21,22 @@
import re
import string
import hex_common
+import argparse
=20
=20
def main():
- hex_common.read_semantics_file(sys.argv[1])
+ parser =3D argparse.ArgumentParser(
+ description=3D"Emit opaque macro calls with instruction names"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
=20
##
## Generate a list of all the opcodes
##
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
for tag in hex_common.tags:
f.write(f"OPCODE({tag}),\n")
=20
diff --git a/target/hexagon/gen_printinsn.py b/target/hexagon/gen_printinsn=
.py
index 8bf4d0985c..d5f969960a 100755
--- a/target/hexagon/gen_printinsn.py
+++ b/target/hexagon/gen_printinsn.py
@@ -21,6 +21,7 @@
import re
import string
import hex_common
+import argparse
=20
=20
##
@@ -96,11 +97,17 @@ def spacify(s):
=20
=20
def main():
- hex_common.read_semantics_file(sys.argv[1])
+ parser =3D argparse.ArgumentParser(
+ "Emit opaque macro calls with information for printing string repr=
esentations of instrucions"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
=20
immext_casere =3D re.compile(r"IMMEXT\(([A-Za-z])")
=20
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
for tag in hex_common.tags:
if not hex_common.behdict[tag]:
continue
diff --git a/target/hexagon/gen_tcg_func_table.py b/target/hexagon/gen_tcg_=
func_table.py
index 978ac1819b..299a39b1aa 100755
--- a/target/hexagon/gen_tcg_func_table.py
+++ b/target/hexagon/gen_tcg_func_table.py
@@ -21,15 +21,22 @@
import re
import string
import hex_common
+import argparse
=20
=20
def main():
- hex_common.read_semantics_file(sys.argv[1])
+ parser =3D argparse.ArgumentParser(
+ "Emit opaque macro calls with instruction semantics"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
hex_common.calculate_attribs()
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- with open(sys.argv[-1], "w") as f:
+ with open(args.out, "w") as f:
f.write("#ifndef HEXAGON_FUNC_TABLE_H\n")
f.write("#define HEXAGON_FUNC_TABLE_H\n\n")
=20
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs=
.py
index 05aa0a7855..c2ba91ddc0 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -108,15 +108,16 @@ def gen_def_tcg_func(f, tag, tagregs, tagimms):
=20
=20
def main():
- is_idef_parser_enabled =3D hex_common.read_common_files()
+ args =3D hex_common.parse_common_args(
+ "Emit functions calling generated code implementing instruction se=
mantics (helpers, idef-parser)"
+ )
tagregs =3D hex_common.get_tagregs()
tagimms =3D hex_common.get_tagimms()
=20
- output_file =3D sys.argv[-1]
- with open(output_file, "w") as f:
+ with open(args.out, "w") as f:
f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
- if is_idef_parser_enabled:
+ if args.idef_parser:
f.write('#include "idef-generated-emitter.h.inc"\n\n')
=20
for tag in hex_common.tags:
diff --git a/target/hexagon/gen_trans_funcs.py b/target/hexagon/gen_trans_f=
uncs.py
index 30f0c73e0c..45da1b7b5d 100755
--- a/target/hexagon/gen_trans_funcs.py
+++ b/target/hexagon/gen_trans_funcs.py
@@ -24,6 +24,7 @@
import textwrap
import iset
import hex_common
+import argparse
=20
encs =3D {
tag: "".join(reversed(iset.iset[tag]["enc"].replace(" ", "")))
@@ -136,8 +137,19 @@ def gen_trans_funcs(f):
"""))
=20
=20
-if __name__ =3D=3D "__main__":
- hex_common.read_semantics_file(sys.argv[1])
+def main():
+ parser =3D argparse.ArgumentParser(
+ description=3D"Emit trans_*() functions to be called by " \
+ "instruction decoder"
+ )
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("out", help=3D"output file")
+ args =3D parser.parse_args()
+ hex_common.read_semantics_file(args.semantics)
hex_common.init_registers()
- with open(sys.argv[2], "w") as f:
+ with open(args.out, "w") as f:
gen_trans_funcs(f)
+
+
+if __name__ =3D=3D "__main__":
+ main()
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 15ed4980e4..758e5fd12d 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -21,6 +21,7 @@
import re
import string
import textwrap
+import argparse
=20
behdict =3D {} # tag ->behavior
semdict =3D {} # tag -> semantics
@@ -1181,22 +1182,20 @@ def helper_args(tag, regs, imms):
return args
=20
=20
-def read_common_files():
- read_semantics_file(sys.argv[1])
- read_overrides_file(sys.argv[2])
- read_overrides_file(sys.argv[3])
- ## Whether or not idef-parser is enabled is
- ## determined by the number of arguments to
- ## this script:
- ##
- ## 4 args. -> not enabled,
- ## 5 args. -> idef-parser enabled.
- ##
- ## The 5:th arg. then holds a list of the successfully
- ## parsed instructions.
- is_idef_parser_enabled =3D len(sys.argv) > 5
- if is_idef_parser_enabled:
- read_idef_parser_enabled_file(sys.argv[4])
+def parse_common_args(desc):
+ parser =3D argparse.ArgumentParser(desc)
+ parser.add_argument("semantics", help=3D"semantics file")
+ parser.add_argument("overrides", help=3D"overrides file")
+ parser.add_argument("overrides_vec", help=3D"vector overrides file")
+ parser.add_argument("out", help=3D"output file")
+ parser.add_argument("--idef-parser",
+ help=3D"file of instructions translated by idef-pa=
rser")
+ args =3D parser.parse_args()
+ read_semantics_file(args.semantics)
+ read_overrides_file(args.overrides)
+ read_overrides_file(args.overrides_vec)
+ if args.idef_parser:
+ read_idef_parser_enabled_file(args.idef_parser)
calculate_attribs()
init_registers()
- return is_idef_parser_enabled
+ return args
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index f1723778a6..bb4ebaae81 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -346,7 +346,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in targ=
et_dirs
# Setup input and dependencies for the next step, this depends on whet=
her or
# not idef-parser is enabled
helper_dep =3D [semantics_generated, idef_generated_tcg_c, idef_genera=
ted_tcg]
- helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, idef_gen=
erated_list]
+ helper_in =3D [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, '--idef-=
parser', idef_generated_list]
else
# Setup input and dependencies for the next step, this depends on whet=
her or
# not idef-parser is enabled
--=20
2.34.1
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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, peter.maydell@linaro.org,
quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng,
quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
Brian Cain <bcain@oss.qualcomm.com>
Subject: [PULL 5/5] target/hexagon: Make HVX vector args. restrict *
Date: Thu, 12 Dec 2024 20:18:36 -0800
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From: Anton Johansson <anjo@rev.ng>
Adds restrict qualifier to HVX pointer arguments. This will allow the
compiler to produce better optimized code, as input vectors are now
assumed not to alias, and no runtime aliasing checks will be required.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/mmvec/macros.h | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index 1ceb9453ee..bcd4a1e897 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -23,26 +23,26 @@
#include "mmvec/system_ext_mmvec.h"
=20
#ifndef QEMU_GENERATE
-#define VdV (*(MMVector *)(VdV_void))
-#define VsV (*(MMVector *)(VsV_void))
-#define VuV (*(MMVector *)(VuV_void))
-#define VvV (*(MMVector *)(VvV_void))
-#define VwV (*(MMVector *)(VwV_void))
-#define VxV (*(MMVector *)(VxV_void))
-#define VyV (*(MMVector *)(VyV_void))
+#define VdV (*(MMVector *restrict)(VdV_void))
+#define VsV (*(MMVector *restrict)(VsV_void))
+#define VuV (*(MMVector *restrict)(VuV_void))
+#define VvV (*(MMVector *restrict)(VvV_void))
+#define VwV (*(MMVector *restrict)(VwV_void))
+#define VxV (*(MMVector *restrict)(VxV_void))
+#define VyV (*(MMVector *restrict)(VyV_void))
=20
-#define VddV (*(MMVectorPair *)(VddV_void))
-#define VuuV (*(MMVectorPair *)(VuuV_void))
-#define VvvV (*(MMVectorPair *)(VvvV_void))
-#define VxxV (*(MMVectorPair *)(VxxV_void))
+#define VddV (*(MMVectorPair *restrict)(VddV_void))
+#define VuuV (*(MMVectorPair *restrict)(VuuV_void))
+#define VvvV (*(MMVectorPair *restrict)(VvvV_void))
+#define VxxV (*(MMVectorPair *restrict)(VxxV_void))
=20
-#define QeV (*(MMQReg *)(QeV_void))
-#define QdV (*(MMQReg *)(QdV_void))
-#define QsV (*(MMQReg *)(QsV_void))
-#define QtV (*(MMQReg *)(QtV_void))
-#define QuV (*(MMQReg *)(QuV_void))
-#define QvV (*(MMQReg *)(QvV_void))
-#define QxV (*(MMQReg *)(QxV_void))
+#define QeV (*(MMQReg *restrict)(QeV_void))
+#define QdV (*(MMQReg *restrict)(QdV_void))
+#define QsV (*(MMQReg *restrict)(QsV_void))
+#define QtV (*(MMQReg *restrict)(QtV_void))
+#define QuV (*(MMQReg *restrict)(QuV_void))
+#define QvV (*(MMQReg *restrict)(QvV_void))
+#define QxV (*(MMQReg *restrict)(QxV_void))
#endif
=20
#define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \
--=20
2.34.1