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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Roman Artemev <roman.artemev@syntacore.com>, qemu-stable@nongnu.org,
Denis Tomashev <denis.tomashev@syntacore.com>
Subject: [PULL 2/4] tcg/riscv: Fix StoreStore barrier generation
Date: Thu, 12 Dec 2024 14:48:16 -0600
Message-ID: <20241212204818.2468583-3-richard.henderson@linaro.org>
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From: Roman Artemev <roman.artemev@syntacore.com>
On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f8331e4688..96f9a7e348 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
insn |=3D 0x02100000;
}
if (a0 & TCG_MO_ST_ST) {
- insn |=3D 0x02200000;
+ insn |=3D 0x01100000;
}
tcg_out32(s, insn);
}
--=20
2.43.0