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Thu, 12 Dec 2024 09:22:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHPtuQ9i7Q5Wttof82EifUn50vzbZkbe6+LFSMkXywkQw18sj1mp8gRfekBMl6pkeLXWAnpZg== X-Received: by 2002:a05:600c:4e49:b0:434:edcf:7474 with SMTP id 5b1f17b1804b1-43622883cd8mr37848415e9.33.1734024144601; Thu, 12 Dec 2024 09:22:24 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: philmd@linaro.org, qemu-rust@nongnu.org Subject: [PATCH 5/7] rust: pl011: extend registers to 32 bits Date: Thu, 12 Dec 2024 18:22:02 +0100 Message-ID: <20241212172209.533779-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241212172209.533779-1-pbonzini@redhat.com> References: <20241212172209.533779-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.496, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1734024200711116600 Content-Type: text/plain; charset="utf-8" The PL011 Technical Reference Manual lists the "real" size of the registers in table 3-1, and only rounds up to the next byte when describing the registers; for example, UARTDR is listed as having width 12/8 (12 bits read, 8 written) and only bits 15:0 are listed in "Table 3-2 UARTDR Register". However, in practice these are 32-bit registers, accessible only through 32-bit MMIO accesses; preserving the fiction that they're smaller introduces multiple casts (to go from the bilge bitfield type to e.g u16 to u64) and more importantly it breaks the migration stream (though only on big-endian machines) because the Rust vmstate macros are not yet type safe. So, just make everything 32-bits wide. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu --- rust/hw/char/pl011/src/device.rs | 36 ++++++++++++++------------------ rust/hw/char/pl011/src/lib.rs | 23 +++++++++----------- 2 files changed, 26 insertions(+), 33 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index e88ea24b00e..332e0a31a82 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -190,10 +190,10 @@ unsafe fn init(&mut self) { pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::Con= trolFlow { use RegisterOffset::*; =20 - std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { + let value =3D match RegisterOffset::try_from(offset) { Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> { let device_id =3D self.get_class().device_id; - u64::from(device_id[(offset - 0xfe0) >> 2]) + u32::from(device_id[(offset - 0xfe0) >> 2]) } Err(_) =3D> { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); @@ -219,27 +219,25 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint)= -> std::ops::ControlFlow u8::from(self.receive_status_error_clear).into(), - Ok(FR) =3D> u16::from(self.flags).into(), - Ok(FBRD) =3D> self.fbrd.into(), - Ok(ILPR) =3D> self.ilpr.into(), - Ok(IBRD) =3D> self.ibrd.into(), - Ok(LCR_H) =3D> u16::from(self.line_control).into(), - Ok(CR) =3D> { - // We exercise our self-control. - u16::from(self.control).into() - } - Ok(FLS) =3D> self.ifl.into(), - Ok(IMSC) =3D> self.int_enabled.into(), - Ok(RIS) =3D> self.int_level.into(), - Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(RSR) =3D> u32::from(self.receive_status_error_clear), + Ok(FR) =3D> u32::from(self.flags), + Ok(FBRD) =3D> self.fbrd, + Ok(ILPR) =3D> self.ilpr, + Ok(IBRD) =3D> self.ibrd, + Ok(LCR_H) =3D> u32::from(self.line_control), + Ok(CR) =3D> u32::from(self.control), + Ok(FLS) =3D> self.ifl, + Ok(IMSC) =3D> self.int_enabled, + Ok(RIS) =3D> self.int_level, + Ok(MIS) =3D> self.int_level & self.int_enabled, Ok(ICR) =3D> { // "The UARTICR Register is the interrupt clear register a= nd is write-only" // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR 0 } - Ok(DMACR) =3D> self.dmacr.into(), - }) + Ok(DMACR) =3D> self.dmacr, + }; + std::ops::ControlFlow::Break(value.into()) } =20 pub fn write(&mut self, offset: hwaddr, value: u64) { @@ -281,7 +279,6 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { self.fbrd =3D value; } Ok(LCR_H) =3D> { - let value =3D value as u16; let new_val: registers::LineControl =3D value.into(); // Reset the FIFO state on FIFO enable or disable if bool::from(self.line_control.fifos_enabled()) @@ -308,7 +305,6 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { } Ok(CR) =3D> { // ??? Need to implement the enable bit. - let value =3D value as u16; self.control =3D value.into(); self.loopback_mdmctrl(); } diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 463ae60543b..0747e130cae 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -131,12 +131,6 @@ const fn _assert_exhaustive(val: RegisterOffset) { pub mod registers { //! Device registers exposed as typed structs which are backed by arbi= trary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. - //! - //! All PL011 registers are essentially 32-bit wide, but are typed her= e as - //! bitmaps with only the necessary width. That is, if a struct bitmap - //! in this module is for example 16 bits long, it should be conceived - //! as a 32-bit register where the unmentioned higher bits are always - //! unused thus treated as zero when read or written. use bilge::prelude::*; =20 /// Receive Status Register / Data Register common error bits @@ -234,10 +228,11 @@ impl Data { /// # Source /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, /// UARTRSR/UARTECR - #[bitsize(8)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct ReceiveStatusErrorClear { pub errors: Errors, + _reserved_unpredictable: u24, } =20 impl ReceiveStatusErrorClear { @@ -257,7 +252,7 @@ fn default() -> Self { } } =20 - #[bitsize(16)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] /// Flag Register, `UARTFR` #[doc(alias =3D "UARTFR")] @@ -309,7 +304,7 @@ pub struct Flags { pub transmit_fifo_empty: bool, /// `RI`, is `true` when `nUARTRI` is `LOW`. pub ring_indicator: bool, - _reserved_zero_no_modify: u7, + _reserved_zero_no_modify: u23, } =20 impl Flags { @@ -328,7 +323,7 @@ fn default() -> Self { } } =20 - #[bitsize(16)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] /// Line Control Register, `UARTLCR_H` #[doc(alias =3D "UARTLCR_H")] @@ -382,8 +377,8 @@ pub struct LineControl { /// the PEN bit disables parity checking and generation. See Table= 3-11 /// on page 3-14 for the parity truth table. pub sticky_parity: bool, - /// 15:8 - Reserved, do not modify, read as zero. - _reserved_zero_no_modify: u8, + /// 31:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u24, } =20 impl LineControl { @@ -454,7 +449,7 @@ pub enum WordLength { /// /// # Source /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 - #[bitsize(16)] + #[bitsize(32)] #[doc(alias =3D "UARTCR")] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct Control { @@ -532,6 +527,8 @@ pub struct Control { /// CTS hardware flow control is enabled. Data is only transmitted= when /// the `nUARTCTS` signal is asserted. pub cts_hardware_flow_control_enable: bool, + /// 31:16 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify2: u16, } =20 impl Control { --=20 2.47.1