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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 1/7] rust: pl011: fix declaration of LineControl bits
Date: Thu, 12 Dec 2024 18:21:58 +0100
Message-ID: <20241212172209.533779-2-pbonzini@redhat.com>
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The bits in the LineControl struct were backwards. :(
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/lib.rs | 82 +++++++++++++++++------------------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 4dc0e8f345f..d5089f78854 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -319,32 +319,21 @@ fn default() -> Self {
/// Line Control Register, `UARTLCR_H`
#[doc(alias =3D "UARTLCR_H")]
pub struct LineControl {
- /// 15:8 - Reserved, do not modify, read as zero.
- _reserved_zero_no_modify: u8,
- /// 7 SPS Stick parity select.
- /// 0 =3D stick parity is disabled
- /// 1 =3D either:
- /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt=
ed and checked
- /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is
- /// transmitted and checked as a 0. This bit has no effect when
- /// the PEN bit disables parity checking and generation. See Table=
3-11
- /// on page 3-14 for the parity truth table.
- pub sticky_parity: bool,
- /// WLEN Word length. These bits indicate the number of data bits
- /// transmitted or received in a frame as follows: b11 =3D 8 bits
- /// b10 =3D 7 bits
- /// b01 =3D 6 bits
- /// b00 =3D 5 bits.
- pub word_length: WordLength,
- /// FEN Enable FIFOs:
- /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b=
ecome
- /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO
- /// buffers are enabled (FIFO mode).
- pub fifos_enabled: Mode,
- /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop=
bits
- /// are transmitted at the end of the frame. The receive
- /// logic does not check for two stop bits being received.
- pub two_stops_bits: bool,
+ /// BRK Send break.
+ ///
+ /// If this bit is set to `1`, a low-level is continually output o=
n the
+ /// `UARTTXD` output, after completing transmission of the
+ /// current character. For the proper execution of the break comma=
nd,
+ /// the software must set this bit for at least two complete
+ /// frames. For normal use, this bit must be cleared to `0`.
+ pub send_break: bool,
+ /// 1 PEN Parity enable:
+ ///
+ /// - 0 =3D parity is disabled and no parity bit added to the data=
frame
+ /// - 1 =3D parity checking and generation is enabled.
+ ///
+ /// See Table 3-11 on page 3-14 for the parity truth table.
+ pub parity_enabled: bool,
/// EPS Even parity select. Controls the type of parity the UART u=
ses
/// during transmission and reception:
/// - 0 =3D odd parity. The UART generates or checks for an odd nu=
mber of
@@ -355,21 +344,32 @@ pub struct LineControl {
/// and generation. See Table 3-11 on page 3-14 for the parity
/// truth table.
pub parity: Parity,
- /// 1 PEN Parity enable:
- ///
- /// - 0 =3D parity is disabled and no parity bit added to the data=
frame
- /// - 1 =3D parity checking and generation is enabled.
- ///
- /// See Table 3-11 on page 3-14 for the parity truth table.
- pub parity_enabled: bool,
- /// BRK Send break.
- ///
- /// If this bit is set to `1`, a low-level is continually output o=
n the
- /// `UARTTXD` output, after completing transmission of the
- /// current character. For the proper execution of the break comma=
nd,
- /// the software must set this bit for at least two complete
- /// frames. For normal use, this bit must be cleared to `0`.
- pub send_break: bool,
+ /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop=
bits
+ /// are transmitted at the end of the frame. The receive
+ /// logic does not check for two stop bits being received.
+ pub two_stops_bits: bool,
+ /// FEN Enable FIFOs:
+ /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b=
ecome
+ /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO
+ /// buffers are enabled (FIFO mode).
+ pub fifos_enabled: Mode,
+ /// WLEN Word length. These bits indicate the number of data bits
+ /// transmitted or received in a frame as follows: b11 =3D 8 bits
+ /// b10 =3D 7 bits
+ /// b01 =3D 6 bits
+ /// b00 =3D 5 bits.
+ pub word_length: WordLength,
+ /// 7 SPS Stick parity select.
+ /// 0 =3D stick parity is disabled
+ /// 1 =3D either:
+ /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt=
ed and checked
+ /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is
+ /// transmitted and checked as a 0. This bit has no effect when
+ /// the PEN bit disables parity checking and generation. See Table=
3-11
+ /// on page 3-14 for the parity truth table.
+ pub sticky_parity: bool,
+ /// 15:8 - Reserved, do not modify, read as zero.
+ _reserved_zero_no_modify: u8,
}
=20
impl LineControl {
--=20
2.47.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 2/7] rust: pl011: match break logic of C version
Date: Thu, 12 Dec 2024 18:21:59 +0100
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Check loopback_enabled(), not fifo_enabled(), like the C code.
Also, set_break_error() must not happen until the break is read from
the FIFO.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 41220c99a83..c6a8dbe1af4 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -465,9 +465,8 @@ pub fn can_receive(&self) -> bool {
}
=20
pub fn event(&mut self, event: QEMUChrEvent) {
- if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.f=
ifo_enabled() {
+ if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.l=
oopback_enabled() {
self.put_fifo(DATA_BREAK);
- self.receive_status_error_clear.set_break_error(true);
}
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 3/7] rust: pl011: always use reset() method on registers
Date: Thu, 12 Dec 2024 18:22:00 +0100
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For CR, the ugly-ish "0.into()" idiom is already hidden within the
Default trait. Do not repeat it.
For FR, standardize on reset() being equivalent to "*self =3D Self::default=
()"
and let reset_fifo toggle only the bits that are related to FIFOs. This
commit also reproduces C commit 02b1f7f6192 ("hw/char/pl011: Split RX/TX
path of pl011_reset_fifo()", 2024-09-13).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 23 ++++++++++++++++-------
rust/hw/char/pl011/src/lib.rs | 13 +++++--------
2 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index c6a8dbe1af4..eb15e9d5788 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -267,7 +267,7 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
self.update();
}
Ok(RSR) =3D> {
- self.receive_status_error_clear =3D 0.into();
+ self.receive_status_error_clear.reset();
}
Ok(FR) =3D> {
// flag writes are ignored
@@ -288,7 +288,8 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
if bool::from(self.line_control.fifos_enabled())
^ bool::from(new_val.fifos_enabled())
{
- self.reset_fifo();
+ self.reset_rx_fifo();
+ self.reset_tx_fifo();
}
if self.line_control.send_break() ^ new_val.send_break() {
let mut break_enable: c_int =3D new_val.send_break().i=
nto();
@@ -447,16 +448,24 @@ pub fn reset(&mut self) {
self.read_trigger =3D 1;
self.ifl =3D 0x12;
self.control.reset();
- self.flags =3D 0.into();
- self.reset_fifo();
+ self.flags.reset();
+ self.reset_rx_fifo();
+ self.reset_tx_fifo();
}
=20
- pub fn reset_fifo(&mut self) {
+ pub fn reset_rx_fifo(&mut self) {
self.read_count =3D 0;
self.read_pos =3D 0;
=20
- /* Reset FIFO flags */
- self.flags.reset();
+ // Reset FIFO flags
+ self.flags.set_receive_fifo_full(false);
+ self.flags.set_receive_fifo_empty(true);
+ }
+
+ pub fn reset_tx_fifo(&mut self) {
+ // Reset FIFO flags
+ self.flags.set_transmit_fifo_full(false);
+ self.flags.set_transmit_fifo_empty(true);
}
=20
pub fn can_receive(&self) -> bool {
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index d5089f78854..e3eacb0e6b9 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -230,7 +230,7 @@ pub struct ReceiveStatusErrorClear {
impl ReceiveStatusErrorClear {
pub fn reset(&mut self) {
// All the bits are cleared to 0 on reset.
- *self =3D 0.into();
+ *self =3D Self::default();
}
}
=20
@@ -297,19 +297,16 @@ pub struct Flags {
=20
impl Flags {
pub fn reset(&mut self) {
- // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a=
re 1
- self.set_receive_fifo_full(false);
- self.set_transmit_fifo_full(false);
- self.set_busy(false);
- self.set_receive_fifo_empty(true);
- self.set_transmit_fifo_empty(true);
+ *self =3D Self::default();
}
}
=20
impl Default for Flags {
fn default() -> Self {
let mut ret: Self =3D 0.into();
- ret.reset();
+ // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a=
re 1
+ ret.set_receive_fifo_empty(true);
+ ret.set_transmit_fifo_empty(true);
ret
}
}
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 4/7] rust: pl011: fix break errors and definition of Data
struct
Date: Thu, 12 Dec 2024 18:22:01 +0100
Message-ID: <20241212172209.533779-5-pbonzini@redhat.com>
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The Data struct is wrong, and does not show how bits 8-15 of DR
are the receive status. Fix it, and use it to fix break
errors ("c >> 8" in the C code does not translate to
"c.to_be_bytes()[3]").
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 15 ++++++------
rust/hw/char/pl011/src/lib.rs | 41 ++++++++++++++++++++++----------
2 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index eb15e9d5788..e88ea24b00e 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -30,8 +30,6 @@
/// Fractional Baud Rate Divider, `UARTFBRD`
const FBRD_MASK: u32 =3D 0x3f;
=20
-const DATA_BREAK: u32 =3D 1 << 10;
-
/// QEMU sourced constant.
pub const PL011_FIFO_DEPTH: usize =3D 16_usize;
=20
@@ -68,7 +66,7 @@ pub struct PL011State {
pub dmacr: u32,
pub int_enabled: u32,
pub int_level: u32,
- pub read_fifo: [u32; PL011_FIFO_DEPTH],
+ pub read_fifo: [registers::Data; PL011_FIFO_DEPTH],
pub ilpr: u32,
pub ibrd: u32,
pub fbrd: u32,
@@ -215,10 +213,11 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint)=
-> std::ops::ControlFlow<u
self.int_level &=3D !registers::INT_RX;
}
// Update error bits.
- self.receive_status_error_clear =3D c.to_be_bytes()[3].int=
o();
+ self.receive_status_error_clear.set_from_data(c);
self.update();
// Must call qemu_chr_fe_accept_input, so return Continue:
- return std::ops::ControlFlow::Continue(c.into());
+ let c =3D u32::from(c);
+ return std::ops::ControlFlow::Continue(u64::from(c));
}
Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(),
Ok(FR) =3D> u16::from(self.flags).into(),
@@ -411,7 +410,7 @@ fn loopback_mdmctrl(&mut self) {
=20
fn loopback_break(&mut self, enable: bool) {
if enable {
- self.loopback_tx(DATA_BREAK);
+ self.loopback_tx(registers::Data::BREAK.into());
}
}
=20
@@ -475,7 +474,7 @@ pub fn can_receive(&self) -> bool {
=20
pub fn event(&mut self, event: QEMUChrEvent) {
if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.l=
oopback_enabled() {
- self.put_fifo(DATA_BREAK);
+ self.put_fifo(registers::Data::BREAK.into());
}
}
=20
@@ -502,7 +501,7 @@ pub fn put_fifo(&mut self, value: c_uint) {
let depth =3D self.fifo_depth();
assert!(depth > 0);
let slot =3D (self.read_pos + self.read_count) & (depth - 1);
- self.read_fifo[slot] =3D value;
+ self.read_fifo[slot] =3D registers::Data::from(value);
self.read_count +=3D 1;
self.flags.set_receive_fifo_empty(false);
if self.read_count =3D=3D depth {
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index e3eacb0e6b9..463ae60543b 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -139,6 +139,21 @@ pub mod registers {
//! unused thus treated as zero when read or written.
use bilge::prelude::*;
=20
+ /// Receive Status Register / Data Register common error bits
+ ///
+ /// The `UARTRSR` register is updated only when a read occurs
+ /// from the `UARTDR` register with the same status information
+ /// that can also be obtained by reading the `UARTDR` register
+ #[bitsize(8)]
+ #[derive(Clone, Copy, Default, DebugBits, FromBits)]
+ pub struct Errors {
+ pub framing_error: bool,
+ pub parity_error: bool,
+ pub break_error: bool,
+ pub overrun_error: bool,
+ _reserved_unpredictable: u4,
+ }
+
// TODO: FIFO Mode has different semantics
/// Data Register, `UARTDR`
///
@@ -181,16 +196,18 @@ pub mod registers {
///
/// # Source
/// ARM DDI 0183G 3.3.1 Data Register, UARTDR
- #[bitsize(16)]
- #[derive(Clone, Copy, DebugBits, FromBits)]
+ #[bitsize(32)]
+ #[derive(Clone, Copy, Default, DebugBits, FromBits)]
#[doc(alias =3D "UARTDR")]
pub struct Data {
- _reserved: u4,
pub data: u8,
- pub framing_error: bool,
- pub parity_error: bool,
- pub break_error: bool,
- pub overrun_error: bool,
+ pub errors: Errors,
+ _reserved: u16,
+ }
+
+ impl Data {
+ // bilge is not very const-friendly, unfortunately
+ pub const BREAK: Self =3D Self { value: 1 << 10 };
}
=20
// TODO: FIFO Mode has different semantics
@@ -220,14 +237,14 @@ pub struct Data {
#[bitsize(8)]
#[derive(Clone, Copy, DebugBits, FromBits)]
pub struct ReceiveStatusErrorClear {
- pub framing_error: bool,
- pub parity_error: bool,
- pub break_error: bool,
- pub overrun_error: bool,
- _reserved_unpredictable: u4,
+ pub errors: Errors,
}
=20
impl ReceiveStatusErrorClear {
+ pub fn set_from_data(&mut self, data: Data) {
+ self.set_errors(data.errors());
+ }
+
pub fn reset(&mut self) {
// All the bits are cleared to 0 on reset.
*self =3D Self::default();
--=20
2.47.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 5/7] rust: pl011: extend registers to 32 bits
Date: Thu, 12 Dec 2024 18:22:02 +0100
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The PL011 Technical Reference Manual lists the "real" size of the
registers in table 3-1, and only rounds up to the next byte when
describing the registers; for example, UARTDR is listed as having
width 12/8 (12 bits read, 8 written) and only bits 15:0 are listed
in "Table 3-2 UARTDR Register".
However, in practice these are 32-bit registers, accessible only
through 32-bit MMIO accesses; preserving the fiction that they're
smaller introduces multiple casts (to go from the bilge bitfield
type to e.g u16 to u64) and more importantly it breaks the
migration stream (though only on big-endian machines) because
the Rust vmstate macros are not yet type safe.
So, just make everything 32-bits wide.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 36 ++++++++++++++------------------
rust/hw/char/pl011/src/lib.rs | 23 +++++++++-----------
2 files changed, 26 insertions(+), 33 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index e88ea24b00e..332e0a31a82 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -190,10 +190,10 @@ unsafe fn init(&mut self) {
pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::Con=
trolFlow<u64, u64> {
use RegisterOffset::*;
=20
- std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset=
) {
+ let value =3D match RegisterOffset::try_from(offset) {
Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
let device_id =3D self.get_class().device_id;
- u64::from(device_id[(offset - 0xfe0) >> 2])
+ u32::from(device_id[(offset - 0xfe0) >> 2])
}
Err(_) =3D> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
@@ -219,27 +219,25 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint)=
-> std::ops::ControlFlow<u
let c =3D u32::from(c);
return std::ops::ControlFlow::Continue(u64::from(c));
}
- Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(),
- Ok(FR) =3D> u16::from(self.flags).into(),
- Ok(FBRD) =3D> self.fbrd.into(),
- Ok(ILPR) =3D> self.ilpr.into(),
- Ok(IBRD) =3D> self.ibrd.into(),
- Ok(LCR_H) =3D> u16::from(self.line_control).into(),
- Ok(CR) =3D> {
- // We exercise our self-control.
- u16::from(self.control).into()
- }
- Ok(FLS) =3D> self.ifl.into(),
- Ok(IMSC) =3D> self.int_enabled.into(),
- Ok(RIS) =3D> self.int_level.into(),
- Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled),
+ Ok(RSR) =3D> u32::from(self.receive_status_error_clear),
+ Ok(FR) =3D> u32::from(self.flags),
+ Ok(FBRD) =3D> self.fbrd,
+ Ok(ILPR) =3D> self.ilpr,
+ Ok(IBRD) =3D> self.ibrd,
+ Ok(LCR_H) =3D> u32::from(self.line_control),
+ Ok(CR) =3D> u32::from(self.control),
+ Ok(FLS) =3D> self.ifl,
+ Ok(IMSC) =3D> self.int_enabled,
+ Ok(RIS) =3D> self.int_level,
+ Ok(MIS) =3D> self.int_level & self.int_enabled,
Ok(ICR) =3D> {
// "The UARTICR Register is the interrupt clear register a=
nd is write-only"
// Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, =
UARTICR
0
}
- Ok(DMACR) =3D> self.dmacr.into(),
- })
+ Ok(DMACR) =3D> self.dmacr,
+ };
+ std::ops::ControlFlow::Break(value.into())
}
=20
pub fn write(&mut self, offset: hwaddr, value: u64) {
@@ -281,7 +279,6 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
self.fbrd =3D value;
}
Ok(LCR_H) =3D> {
- let value =3D value as u16;
let new_val: registers::LineControl =3D value.into();
// Reset the FIFO state on FIFO enable or disable
if bool::from(self.line_control.fifos_enabled())
@@ -308,7 +305,6 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
}
Ok(CR) =3D> {
// ??? Need to implement the enable bit.
- let value =3D value as u16;
self.control =3D value.into();
self.loopback_mdmctrl();
}
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 463ae60543b..0747e130cae 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -131,12 +131,6 @@ const fn _assert_exhaustive(val: RegisterOffset) {
pub mod registers {
//! Device registers exposed as typed structs which are backed by arbi=
trary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
- //!
- //! All PL011 registers are essentially 32-bit wide, but are typed her=
e as
- //! bitmaps with only the necessary width. That is, if a struct bitmap
- //! in this module is for example 16 bits long, it should be conceived
- //! as a 32-bit register where the unmentioned higher bits are always
- //! unused thus treated as zero when read or written.
use bilge::prelude::*;
=20
/// Receive Status Register / Data Register common error bits
@@ -234,10 +228,11 @@ impl Data {
/// # Source
/// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register,
/// UARTRSR/UARTECR
- #[bitsize(8)]
+ #[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)]
pub struct ReceiveStatusErrorClear {
pub errors: Errors,
+ _reserved_unpredictable: u24,
}
=20
impl ReceiveStatusErrorClear {
@@ -257,7 +252,7 @@ fn default() -> Self {
}
}
=20
- #[bitsize(16)]
+ #[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)]
/// Flag Register, `UARTFR`
#[doc(alias =3D "UARTFR")]
@@ -309,7 +304,7 @@ pub struct Flags {
pub transmit_fifo_empty: bool,
/// `RI`, is `true` when `nUARTRI` is `LOW`.
pub ring_indicator: bool,
- _reserved_zero_no_modify: u7,
+ _reserved_zero_no_modify: u23,
}
=20
impl Flags {
@@ -328,7 +323,7 @@ fn default() -> Self {
}
}
=20
- #[bitsize(16)]
+ #[bitsize(32)]
#[derive(Clone, Copy, DebugBits, FromBits)]
/// Line Control Register, `UARTLCR_H`
#[doc(alias =3D "UARTLCR_H")]
@@ -382,8 +377,8 @@ pub struct LineControl {
/// the PEN bit disables parity checking and generation. See Table=
3-11
/// on page 3-14 for the parity truth table.
pub sticky_parity: bool,
- /// 15:8 - Reserved, do not modify, read as zero.
- _reserved_zero_no_modify: u8,
+ /// 31:8 - Reserved, do not modify, read as zero.
+ _reserved_zero_no_modify: u24,
}
=20
impl LineControl {
@@ -454,7 +449,7 @@ pub enum WordLength {
///
/// # Source
/// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
- #[bitsize(16)]
+ #[bitsize(32)]
#[doc(alias =3D "UARTCR")]
#[derive(Clone, Copy, DebugBits, FromBits)]
pub struct Control {
@@ -532,6 +527,8 @@ pub struct Control {
/// CTS hardware flow control is enabled. Data is only transmitted=
when
/// the `nUARTCTS` signal is asserted.
pub cts_hardware_flow_control_enable: bool,
+ /// 31:16 - Reserved, do not modify, read as zero.
+ _reserved_zero_no_modify2: u16,
}
=20
impl Control {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 6/7] rust: pl011: fix migration stream
Date: Thu, 12 Dec 2024 18:22:03 +0100
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The Rust vmstate macros lack the type-safety of their C equivalents (so
safe, much abstraction), and therefore they were predictably wrong.
The registers have already been changed to 32-bits in the previous patch,
but read_pos/read_count/read_trigger also have to be u32 instead of usize.
The easiest way to do so is to let the FIFO use u32 indices instead
of usize.
My plan for making VMStateField typesafe is to have a trait to retrieve
a basic VMStateField; for example something like vmstate_uint32 would
become an implementation of the VMState trait on u32. Then you'd write
something like "vmstate_of!(Type, field).with_version_id(2)". That is,
vmstate_of retrieves the basic VMStateField and fills in the offset,
and then more changes can be applied on top.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 38 ++++++++++++++++++++++----
rust/hw/char/pl011/src/device_class.rs | 8 +++---
rust/qemu-api/src/vmstate.rs | 22 ---------------
3 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 332e0a31a82..cfe2734703e 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -31,7 +31,7 @@
const FBRD_MASK: u32 =3D 0x3f;
=20
/// QEMU sourced constant.
-pub const PL011_FIFO_DEPTH: usize =3D 16_usize;
+pub const PL011_FIFO_DEPTH: u32 =3D 16;
=20
#[derive(Clone, Copy)]
struct DeviceId(&'static [u8; 8]);
@@ -49,6 +49,32 @@ impl DeviceId {
const LUMINARY: Self =3D Self(&[0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x=
05, 0xb1]);
}
=20
+// FIFOs use 32-bit indices instead of usize, for compatibility with
+// the migration stream produced by the C version of this device.
+#[repr(transparent)]
+#[derive(Debug, Default)]
+pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]);
+
+impl Fifo {
+ const fn len(&self) -> u32 {
+ self.0.len() as u32
+ }
+}
+
+impl std::ops::IndexMut<u32> for Fifo {
+ fn index_mut(&mut self, idx: u32) -> &mut Self::Output {
+ &mut self.0[idx as usize]
+ }
+}
+
+impl std::ops::Index<u32> for Fifo {
+ type Output =3D registers::Data;
+
+ fn index(&self, idx: u32) -> &Self::Output {
+ &self.0[idx as usize]
+ }
+}
+
#[repr(C)]
#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)]
/// PL011 Device Model in QEMU
@@ -66,14 +92,14 @@ pub struct PL011State {
pub dmacr: u32,
pub int_enabled: u32,
pub int_level: u32,
- pub read_fifo: [registers::Data; PL011_FIFO_DEPTH],
+ pub read_fifo: Fifo,
pub ilpr: u32,
pub ibrd: u32,
pub fbrd: u32,
pub ifl: u32,
- pub read_pos: usize,
- pub read_count: usize,
- pub read_trigger: usize,
+ pub read_pos: u32,
+ pub read_count: u32,
+ pub read_trigger: u32,
#[doc(alias =3D "chr")]
pub char_backend: CharBackend,
/// QEMU interrupts
@@ -485,7 +511,7 @@ pub fn loopback_enabled(&self) -> bool {
}
=20
#[inline]
- pub fn fifo_depth(&self) -> usize {
+ pub fn fifo_depth(&self) -> u32 {
// Note: FIFO depth is expected to be power-of-2
if self.fifo_enabled() {
return PL011_FIFO_DEPTH;
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index 975c3d42be7..759c521a99e 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -6,7 +6,7 @@
use std::os::raw::{c_int, c_void};
=20
use qemu_api::{
- bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_int32, vmst=
ate_subsections,
+ bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_subsections,
vmstate_uint32, vmstate_uint32_array, vmstate_unused, zeroable::Zeroab=
le,
};
=20
@@ -64,9 +64,9 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, versio=
n_id: c_int) -> c_int {
vmstate_uint32!(ibrd, PL011State),
vmstate_uint32!(fbrd, PL011State),
vmstate_uint32!(ifl, PL011State),
- vmstate_int32!(read_pos, PL011State),
- vmstate_int32!(read_count, PL011State),
- vmstate_int32!(read_trigger, PL011State),
+ vmstate_uint32!(read_pos, PL011State),
+ vmstate_uint32!(read_count, PL011State),
+ vmstate_uint32!(read_trigger, PL011State),
},
subsections: vmstate_subsections! {
VMSTATE_PL011_CLOCK
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 25c68b703ea..63c897abcdf 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -106,28 +106,6 @@ macro_rules! vmstate_uint32 {
}};
}
=20
-#[doc(alias =3D "VMSTATE_INT32_V")]
-#[macro_export]
-macro_rules! vmstate_int32_v {
- ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{
- $crate::vmstate_single!(
- $field_name,
- $struct_name,
- $version_id,
- ::core::ptr::addr_of!($crate::bindings::vmstate_info_int32),
- ::core::mem::size_of::<i32>()
- )
- }};
-}
-
-#[doc(alias =3D "VMSTATE_INT32")]
-#[macro_export]
-macro_rules! vmstate_int32 {
- ($field_name:ident, $struct_name:ty) =3D> {{
- $crate::vmstate_int32_v!($field_name, $struct_name, 0)
- }};
-}
-
#[doc(alias =3D "VMSTATE_ARRAY")]
#[macro_export]
macro_rules! vmstate_array {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
qemu-rust@nongnu.org
Subject: [PATCH 7/7] rust: pl011: simplify handling of the FIFO enabled bit in
LCR
Date: Thu, 12 Dec 2024 18:22:04 +0100
Message-ID: <20241212172209.533779-8-pbonzini@redhat.com>
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Use =3D=3D/!=3D instead of going through bool and xor.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
rust/hw/char/pl011/src/device.rs | 6 ++----
rust/hw/char/pl011/src/lib.rs | 6 ------
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index cfe2734703e..169ff3779c6 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -307,9 +307,7 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
Ok(LCR_H) =3D> {
let new_val: registers::LineControl =3D value.into();
// Reset the FIFO state on FIFO enable or disable
- if bool::from(self.line_control.fifos_enabled())
- ^ bool::from(new_val.fifos_enabled())
- {
+ if self.line_control.fifos_enabled() !=3D new_val.fifos_en=
abled() {
self.reset_rx_fifo();
self.reset_tx_fifo();
}
@@ -502,7 +500,7 @@ pub fn event(&mut self, event: QEMUChrEvent) {
=20
#[inline]
pub fn fifo_enabled(&self) -> bool {
- matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO)
+ self.line_control.fifos_enabled() =3D=3D registers::Mode::FIFO
}
=20
#[inline]
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 0747e130cae..69064d6929b 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -419,12 +419,6 @@ pub enum Mode {
FIFO =3D 1,
}
=20
- impl From<Mode> for bool {
- fn from(val: Mode) -> Self {
- matches!(val, Mode::FIFO)
- }
- }
-
#[bitsize(2)]
#[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
/// `WLEN` Word length, field of [Line Control register](LineControl).
--=20
2.47.1