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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:02 +0000
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Subject: [RFC PATCH 01/11] target/ppc: introduce gen_ld_tl() function
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This function is intended to be used for all memory load operations. Conver=
t the
GEN_QEMU_LOAD_TL() macro to use it as a starting point.
Signed-off-by: Mark Cave-Aykand <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 47ca50a064..5ddaf69599 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2575,12 +2575,18 @@ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
#define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
=20
+static void gen_ld_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
+ MemOp memop)
+{
+ tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+}
+
#define GEN_QEMU_LOAD_TL(ldop, op) \
static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
TCGv val, \
TCGv addr) \
{ \
- tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
+ gen_ld_tl(ctx, val, addr, ctx->mem_idx, op); \
}
=20
GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:03 +0000
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Subject: [RFC PATCH 02/11] target/ppc: replace tcg_gen_qemu_ld_tl() with
gen_ld_tl()
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To ensure that all memory loads are performed by gen_ld_tl(), convert all
remaining users of tcg_gen_qemu_ld_tl() with gen_ld_tl().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 14 +++++++-------
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5ddaf69599..5fb0aa36ce 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2675,7 +2675,7 @@ static void glue(gen_, name##epx)(DisasContext *ctx) =
\
gen_set_access_type(ctx, ACCESS_INT); =
\
EA =3D tcg_temp_new(); =
\
gen_addr_reg_index(ctx, EA); =
\
- tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ld=
op);\
+ gen_ld_tl(ctx, cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);=
\
}
=20
GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
@@ -2942,7 +2942,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp =
memop)
=20
gen_set_access_type(ctx, ACCESS_RES);
gen_addr_reg_index(ctx, t0);
- tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
+ gen_ld_tl(ctx, gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
tcg_gen_mov_tl(cpu_reserve, t0);
tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
tcg_gen_mov_tl(cpu_reserve_val, gpr);
@@ -2966,9 +2966,9 @@ static void gen_fetch_inc_conditional(DisasContext *c=
tx, MemOp memop,
TCGv t2 =3D tcg_temp_new();
TCGv u =3D tcg_temp_new();
=20
- tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
+ gen_ld_tl(ctx, t, EA, ctx->mem_idx, memop);
tcg_gen_addi_tl(t2, EA, memop_size(memop));
- tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
+ gen_ld_tl(ctx, t2, t2, ctx->mem_idx, memop);
tcg_gen_addi_tl(u, t, addend);
=20
/* E.g. for fetch and increment bounded... */
@@ -3031,7 +3031,7 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp me=
mop)
TCGv t0 =3D tcg_temp_new();
TCGv t1 =3D tcg_temp_new();
=20
- tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
+ gen_ld_tl(ctx, t0, EA, ctx->mem_idx, memop);
if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D =
32) {
tcg_gen_mov_tl(t1, src);
} else {
@@ -3138,9 +3138,9 @@ static void gen_st_atomic(DisasContext *ctx, MemOp me=
mop)
TCGv s2 =3D tcg_temp_new();
TCGv ea_plus_s =3D tcg_temp_new();
=20
- tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
+ gen_ld_tl(ctx, t, EA, ctx->mem_idx, memop);
tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop));
- tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
+ gen_ld_tl(ctx, t2, ea_plus_s, ctx->mem_idx, memop);
tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl=
ate/fixedpoint-impl.c.inc
index fa0191e866..717e3f122f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -37,7 +37,7 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TC=
Gv displ, bool update,
if (store) {
tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
} else {
- tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ gen_ld_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
}
if (update) {
tcg_gen_mov_tl(cpu_gpr[ra], ea);
--=20
2.39.5
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To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:04 +0000
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Subject: [RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function
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This function is intended to be used for all memory store operations. Conve=
rt the
GEN_QEMU_STORE_TL() macro to use it as a starting point.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5fb0aa36ce..bf94f3a5de 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2616,12 +2616,18 @@ GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ))
GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
#endif
=20
+static void gen_st_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
+ MemOp memop)
+{
+ tcg_gen_qemu_st_tl(val, addr, idx, memop);
+}
+
#define GEN_QEMU_STORE_TL(stop, op) \
static void glue(gen_qemu_, stop)(DisasContext *ctx, \
TCGv val, \
TCGv addr) \
{ \
- tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
+ gen_st_tl(ctx, val, addr, ctx->mem_idx, op); \
}
=20
#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
--=20
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:05 +0000
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Subject: [RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with
gen_st_tl()
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To ensure that all memory stores are performed by gen_st_tl(), convert all
remaining users of tcg_gen_qemu_st_tl() with gen_st_tl().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 10 +++++-----
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bf94f3a5de..4c47f97607 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2724,7 +2724,7 @@ static void glue(gen_, name##epx)(DisasContext *ctx) =
\
gen_set_access_type(ctx, ACCESS_INT); =
\
EA =3D tcg_temp_new(); =
\
gen_addr_reg_index(ctx, EA); =
\
- tcg_gen_qemu_st_tl( =
\
+ gen_st_tl(ctx, =
\
cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); =
\
}
=20
@@ -2980,7 +2980,7 @@ static void gen_fetch_inc_conditional(DisasContext *c=
tx, MemOp memop,
/* E.g. for fetch and increment bounded... */
/* mem(EA,s) =3D (t !=3D t2 ? u =3D t + 1 : t) */
tcg_gen_movcond_tl(cond, u, t, t2, u, t);
- tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, u, EA, ctx->mem_idx, memop);
=20
/* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */
tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
@@ -3045,7 +3045,7 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp me=
mop)
}
tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
cpu_gpr[(rt + 2) & 31], t0);
- tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, t1, EA, ctx->mem_idx, memop);
tcg_gen_mov_tl(dst, t0);
}
break;
@@ -3149,8 +3149,8 @@ static void gen_st_atomic(DisasContext *ctx, MemOp me=
mop)
gen_ld_tl(ctx, t2, ea_plus_s, ctx->mem_idx, memop);
tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
- tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
- tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
+ gen_st_tl(ctx, s, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, s2, ea_plus_s, ctx->mem_idx, memop);
}
break;
default:
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl=
ate/fixedpoint-impl.c.inc
index 717e3f122f..6b2265bd8f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -35,7 +35,7 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TC=
Gv displ, bool update,
ea =3D do_ea_calc(ctx, ra, displ);
mop ^=3D ctx->default_tcg_memop_mask;
if (store) {
- tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ gen_st_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
} else {
gen_ld_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
}
--=20
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This function determines whether the MSR_LE bit should be used to implement
little endian accesses using address swizzling, instead of reversing the
byte order.
(FIXME: which CPUs?)
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4c47f97607..1211435039 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -208,6 +208,12 @@ struct DisasContext {
#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
=20
+/* Return true iff address swizzling required */
+static inline bool need_addrswizzle_le(const DisasContext *ctx)
+{
+ return ctx->le_mode && true;
+}
+
/* Return true iff byteswap is needed in a scalar memop */
static inline bool need_byteswap(const DisasContext *ctx)
{
@@ -2578,7 +2584,9 @@ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
static void gen_ld_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
MemOp memop)
{
- tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+ if (!need_addrswizzle_le(ctx)) {
+ tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+ }
}
=20
#define GEN_QEMU_LOAD_TL(ldop, op) \
@@ -2619,7 +2627,9 @@ GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
static void gen_st_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
MemOp memop)
{
- tcg_gen_qemu_st_tl(val, addr, idx, memop);
+ if (!need_addrswizzle_le(ctx)) {
+ tcg_gen_qemu_st_tl(val, addr, idx, memop);
+ }
}
=20
#define GEN_QEMU_STORE_TL(stop, op) \
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:07 +0000
Message-Id: <20241212151412.570454-7-mark.cave-ayland@ilande.co.uk>
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Subject: [RFC PATCH 06/11] target/ppc: introduce gen_addr_swizzle_le()
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This function is used to swizzle the address lines to implement little endi=
an
accesses as used by older CPUs. Add the address line swizzle to the gen_ld_=
tl()
and gen_st_tl() functions.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1211435039..ddc0f85fb7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2561,6 +2561,24 @@ static TCGv do_ea_calc(DisasContext *ctx, int ra, TC=
Gv displ)
return ea;
}
=20
+/*
+ * Swizzle the address lines for little endian accesses as used by older
+ * CPUs. The bottom 3 address lines are exlusive-ORed by a constant to
+ * generate the correct address for a little endian access. For more
+ * information see https://wiki.preterhuman.net/images/f/fc/Endian.pdf
+ */
+static inline void gen_addr_swizzle_le(TCGv ret, TCGv addr, MemOp op)
+{
+ MemOp size =3D op & MO_SIZE;
+ TCGv aoff =3D tcg_temp_new();
+ static int c_swizzle[MO_SIZE] =3D { 0x7, 0x6, 0x4, 0x0 };
+
+ tcg_gen_andi_tl(aoff, addr, (1 << size) - 1);
+ tcg_gen_andi_tl(ret, addr, ~((1 << size) - 1));
+ tcg_gen_xori_tl(ret, ret, c_swizzle[size]);
+ tcg_gen_sub_tl(ret, ret, aoff);
+}
+
#if defined(TARGET_PPC64)
/* EA <- (ra =3D=3D 0) ? 0 : GPR[ra] */
static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
@@ -2586,6 +2604,10 @@ static void gen_ld_tl(DisasContext *ctx, TCGv val, T=
CGv addr, TCGArg idx,
{
if (!need_addrswizzle_le(ctx)) {
tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+ } else {
+ TCGv taddr =3D tcg_temp_new();
+ gen_addr_swizzle_le(taddr, addr, memop);
+ tcg_gen_qemu_ld_tl(val, taddr, idx, memop);
}
}
=20
@@ -2629,6 +2651,10 @@ static void gen_st_tl(DisasContext *ctx, TCGv val, T=
CGv addr, TCGArg idx,
{
if (!need_addrswizzle_le(ctx)) {
tcg_gen_qemu_st_tl(val, addr, idx, memop);
+ } else {
+ TCGv taddr =3D tcg_temp_new();
+ gen_addr_swizzle_le(taddr, addr, memop);
+ tcg_gen_qemu_st_tl(val, taddr, idx, memop);
}
}
=20
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:08 +0000
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Ensure that the address swizzle is implemented when retrieving instructions=
from
guest memory for translation.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ddc0f85fb7..74aa398f25 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6600,7 +6600,11 @@ static void ppc_tr_translate_insn(DisasContextBase *=
dcbase, CPUState *cs)
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
=20
ctx->cia =3D pc =3D ctx->base.pc_next;
- insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
+ if (!need_addrswizzle_le(ctx)) {
+ insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
+ } else {
+ insn =3D translator_ldl(env, dcbase, pc ^ 4);
+ }
ctx->base.pc_next =3D pc +=3D 4;
=20
if (!is_prefix_insn(ctx, insn)) {
@@ -6616,8 +6620,13 @@ static void ppc_tr_translate_insn(DisasContextBase *=
dcbase, CPUState *cs)
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN=
);
ok =3D true;
} else {
- uint32_t insn2 =3D translator_ldl_swap(env, dcbase, pc,
- need_byteswap(ctx));
+ uint32_t insn2;
+
+ if (!need_addrswizzle_le(ctx)) {
+ insn2 =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(c=
tx));
+ } else {
+ insn2 =3D translator_ldl(env, dcbase, pc ^ 4);
+ }
ctx->base.pc_next =3D pc +=3D 4;
ok =3D decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
}
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:09 +0000
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Subject: [RFC PATCH 08/11] target/ppc: implement address swizzle for
gen_ld_atomic()
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The gen_ld_atomic() function uses a number of TCG atomic primitives within =
its
implementation. Update gen_ld_atomic() so that it implements the address sw=
izzle
if required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 81 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 72 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 74aa398f25..b549525bb6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3039,31 +3039,94 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp =
memop)
memop |=3D MO_ALIGN;
switch (gpr_FC) {
case 0: /* Fetch and add */
- tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_add_tl(dst, ta, src, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
+ }
break;
case 1: /* Fetch and xor */
- tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_xor_tl(dst, ta, src, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
+ }
break;
case 2: /* Fetch and or */
- tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_or_tl(dst, ta, src, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
+ }
break;
case 3: /* Fetch and 'and' */
- tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_and_tl(dst, ta, src, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
+ }
break;
case 4: /* Fetch and max unsigned */
- tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_umax_tl(dst, ta, src, ctx->mem_idx, memop=
);
+ } else {
+ tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop=
);
+ }
break;
case 5: /* Fetch and max signed */
- tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_smax_tl(dst, ta, src, ctx->mem_idx, memop=
);
+ } else {
+ tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop=
);
+ }
break;
case 6: /* Fetch and min unsigned */
- tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_umin_tl(dst, ta, src, ctx->mem_idx, memop=
);
+ } else {
+ tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop=
);
+ }
break;
case 7: /* Fetch and min signed */
- tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_fetch_smin_tl(dst, ta, src, ctx->mem_idx, memop=
);
+ } else {
+ tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop=
);
+ }
break;
case 8: /* Swap */
- tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_xchg_tl(dst, ta, src, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
+ }
break;
=20
case 16: /* Compare and swap not equal */
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:10 +0000
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Subject: [RFC PATCH 09/11] target/ppc: implement address swizzle for
gen_st_atomic()
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The gen_st_atomic() function uses a number of TCG atomic primitives within =
its
implementation. Update gen_st_atomic() so that it implements the address sw=
izzle
if required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 72 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 64 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b549525bb6..fc44e3293a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3208,28 +3208,84 @@ static void gen_st_atomic(DisasContext *ctx, MemOp =
memop)
memop |=3D MO_ALIGN;
switch (gpr_FC) {
case 0: /* add and Store */
- tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_add_fetch_tl(discard, ta, src, ctx->mem_idx, me=
mop);
+ } else {
+ tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, me=
mop);
+ }
break;
case 1: /* xor and Store */
- tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_xor_fetch_tl(discard, ta, src, ctx->mem_idx, me=
mop);
+ } else {
+ tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, me=
mop);
+ }
break;
case 2: /* Or and Store */
- tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_or_fetch_tl(discard, ta, src, ctx->mem_idx, mem=
op);
+ } else {
+ tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, mem=
op);
+ }
break;
case 3: /* 'and' and Store */
- tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_and_fetch_tl(discard, ta, src, ctx->mem_idx, me=
mop);
+ } else {
+ tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, me=
mop);
+ }
break;
case 4: /* Store max unsigned */
- tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop=
);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_umax_fetch_tl(discard, ta, src, ctx->mem_idx, m=
emop);
+ } else {
+ tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, m=
emop);
+ }
break;
case 5: /* Store max signed */
- tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop=
);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_smax_fetch_tl(discard, ta, src, ctx->mem_idx, m=
emop);
+ } else {
+ tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, m=
emop);
+ }
break;
case 6: /* Store min unsigned */
- tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop=
);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_umin_fetch_tl(discard, ta, src, ctx->mem_idx, m=
emop);
+ } else {
+ tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, m=
emop);
+ }
break;
case 7: /* Store min signed */
- tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop=
);
+ if (need_addrswizzle_le(ctx)) {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, EA, memop);
+ tcg_gen_atomic_smin_fetch_tl(discard, ta, src, ctx->mem_idx, m=
emop);
+ } else {
+ tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, m=
emop);
+ }
break;
case 24: /* Store twin */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:11 +0000
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Subject: [RFC PATCH 10/11] target/ppc: implement address swizzle for
gen_conditional_store()
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The gen_conditional_store() function uses tcg_gen_atomic_cmpxchg_tl() withi=
n its
implementation. Update gen_conditional_store() so that it implements the ad=
dress
swizzle if required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index fc44e3293a..e8ae96cd46 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3345,9 +3345,18 @@ static void gen_conditional_store(DisasContext *ctx,=
MemOp memop)
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop),=
lfail);
=20
- tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
- cpu_gpr[rs], ctx->mem_idx,
- DEF_MEMOP(memop) | MO_ALIGN);
+ if (!need_addrswizzle_le(ctx)) {
+ tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
+ cpu_gpr[rs], ctx->mem_idx,
+ DEF_MEMOP(memop) | MO_ALIGN);
+ } else {
+ TCGv ta =3D tcg_temp_new();
+
+ gen_addr_swizzle_le(ta, cpu_reserve, memop);
+ tcg_gen_atomic_cmpxchg_tl(t0, ta, cpu_reserve_val,
+ cpu_gpr[rs], ctx->mem_idx,
+ DEF_MEMOP(memop) | MO_ALIGN);
+ }
tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
tcg_gen_or_tl(cr0, cr0, t0);
--=20
2.39.5
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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: npiggin@gmail.com, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Date: Thu, 12 Dec 2024 15:14:12 +0000
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Subject: [RFC PATCH 11/11] target/ppc: update DisasContext
default_tcg_memop_mask value
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If address swizzling is enabled for little endian accesses, don't use littl=
e endian
memory ordering. This is because the conversion is performed by swizzling t=
he
physical address lines as opposed to reversing the memory storage order.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e8ae96cd46..4a0be4d70c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6664,7 +6664,8 @@ static void ppc_tr_init_disas_context(DisasContextBas=
e *dcbase, CPUState *cs)
ctx->access_type =3D -1;
ctx->need_access_type =3D !mmu_is_64bit(env->mmu_model);
ctx->le_mode =3D (hflags >> HFLAGS_LE) & 1;
- ctx->default_tcg_memop_mask =3D ctx->le_mode ? MO_LE : MO_BE;
+ ctx->default_tcg_memop_mask =3D (!need_addrswizzle_le(ctx) &&
+ ctx->le_mode) ? MO_LE : MO_BE;
ctx->flags =3D env->flags;
#if defined(TARGET_PPC64)
ctx->excp_model =3D env->excp_model;
--=20
2.39.5