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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com,
mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com,
nicolinc@nvidia.com, joao.m.martins@oracle.com,
clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,
chao.p.peng@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: [PATCH v6 07/20] intel_iommu: Check if the input address is canonical
Date: Thu, 12 Dec 2024 16:37:44 +0800
Message-Id: <20241212083757.605022-8-zhenzhong.duan@intel.com>
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From: Cl=C3=A9ment Mathieu--Drif <clement.mathieu--drif@eviden.com>
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Cl=C3=A9ment Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 86d3354198..3e7365dfff 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -326,6 +326,7 @@ typedef enum VTDFaultReason {
/* Non-zero reserved field in present first-stage paging entry */
VTD_FR_FS_PAGING_ENTRY_RSVD =3D 0x72,
VTD_FR_PASID_ENTRY_FSPTPTR_INV =3D 0x73, /* Invalid FSPTPTR in PASID e=
ntry */
+ VTD_FR_FS_NON_CANONICAL =3D 0x80, /* SNG.1 : Address for FS not canoni=
cal.*/
VTD_FR_FS_PAGING_ENTRY_US =3D 0x81, /* Privilege violation */
VTD_FR_SM_WRITE =3D 0x85, /* No write permission */
=20
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dbfd48fb65..a4a2a44f92 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1824,6 +1824,7 @@ static const bool vtd_qualified_faults[] =3D {
[VTD_FR_FS_PAGING_ENTRY_P] =3D true,
[VTD_FR_FS_PAGING_ENTRY_RSVD] =3D true,
[VTD_FR_PASID_ENTRY_FSPTPTR_INV] =3D true,
+ [VTD_FR_FS_NON_CANONICAL] =3D true,
[VTD_FR_FS_PAGING_ENTRY_US] =3D true,
[VTD_FR_SM_WRITE] =3D true,
[VTD_FR_SM_INTERRUPT_ADDR] =3D true,
@@ -1930,6 +1931,22 @@ static inline bool vtd_flpte_present(uint64_t flpte)
return !!(flpte & VTD_FL_P);
}
=20
+/* Return true if IOVA is canonical, otherwise false. */
+static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova,
+ VTDContextEntry *ce, uint32_t pasi=
d)
+{
+ uint64_t iova_limit =3D vtd_iova_limit(s, ce, s->aw_bits, pasid);
+ uint64_t upper_bits_mask =3D ~(iova_limit - 1);
+ uint64_t upper_bits =3D iova & upper_bits_mask;
+ bool msb =3D ((iova & (iova_limit >> 1)) !=3D 0);
+
+ if (msb) {
+ return upper_bits =3D=3D upper_bits_mask;
+ } else {
+ return !upper_bits;
+ }
+}
+
/*
* Given the @iova, get relevant @flptep. @flpte_level will be the last le=
vel
* of the translation, can be used for deciding the size of large page.
@@ -1945,6 +1962,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTD=
ContextEntry *ce,
uint32_t offset;
uint64_t flpte;
=20
+ if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) {
+ error_report_once("%s: detected non canonical IOVA (iova=3D0x%" PR=
Ix64 ","
+ "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid);
+ return -VTD_FR_FS_NON_CANONICAL;
+ }
+
while (true) {
offset =3D vtd_iova_level_offset(iova, level);
flpte =3D vtd_get_pte(addr, offset);
--=20
2.34.1