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Tsirkin" , Marcel Apfelbaum , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Dmitry Fleytman , Akihiko Odaki , Sriram Yagnaraman Subject: [PATCH 4/8] tests/qtest/e1000e|igb: Fix e1000e and igb tests to re-trigger interrupts Date: Thu, 12 Dec 2024 18:34:57 +1000 Message-ID: <20241212083502.1439033-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241212083502.1439033-1-npiggin@gmail.com> References: <20241212083502.1439033-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733992595982116600 Content-Type: text/plain; charset="utf-8" The e1000e and igb tests don't clear the msix pending bit after waiting for it sit is masked so the irq doesn't get delivered. Failing to clear the pending interrupt means all subsequent waits for interrupt after the first do not actually wait for an interrupt genreated by the device. Explicitly clearing the msix pending bit results in the multiple-transfers test hanging waiting for the second interrupt. This happens because the e1000e and igb tests do not clear (or set auto-clear) on queue interrupts, so the cause remains ste in ICR/EICR, which inhibits triggering of a new interrupt. Fix both these problems. Clear the msix pending bit explicitly after waiting for it; and clear the ICR/EICR cause bits after seeing and interrupt (also verify we saw the correct cause bit). Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Cc: Dmitry Fleytman Cc: Akihiko Odaki Cc: Sriram Yagnaraman Signed-off-by: Nicholas Piggin --- tests/qtest/e1000e-test.c | 8 ++++++-- tests/qtest/igb-test.c | 8 ++++++-- tests/qtest/libqos/e1000e.c | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c index de9738fdb74..a69759da70e 100644 --- a/tests/qtest/e1000e-test.c +++ b/tests/qtest/e1000e-test.c @@ -64,8 +64,10 @@ static void e1000e_send_verify(QE1000E *d, int *test_soc= kets, QGuestAllocator *a /* Put descriptor to the ring */ e1000e_tx_ring_push(d, &descr); =20 - /* Wait for TX WB interrupt */ + /* Wait for TX WB interrupt (this clears the MSIX PBA) */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read ICR which clears it ready for next interrupt, assert TXQ0 caus= e */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_TXQ0); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, =3D= =3D, @@ -115,8 +117,10 @@ static void e1000e_receive_verify(QE1000E *d, int *tes= t_sockets, QGuestAllocator /* Put descriptor to the ring */ e1000e_rx_ring_push(d, &descr); =20 - /* Wait for TX WB interrupt */ + /* Wait for TX WB interrupt (this clears the MSIX PBA) */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); + /* Read ICR which clears it ready for next interrupt, assert RXQ0 caus= e */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_RXQ0); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c index 3d397ea6973..2f22c4fb208 100644 --- a/tests/qtest/igb-test.c +++ b/tests/qtest/igb-test.c @@ -67,8 +67,10 @@ static void igb_send_verify(QE1000E *d, int *test_socket= s, QGuestAllocator *allo /* Put descriptor to the ring */ e1000e_tx_ring_push(d, &descr); =20 - /* Wait for TX WB interrupt */ + /* Wait for TX WB interrupt (this clears the MSIX PBA) */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert TXQ0 cau= se */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_TX0_MSG_ID)); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, =3D= =3D, @@ -118,8 +120,10 @@ static void igb_receive_verify(QE1000E *d, int *test_s= ockets, QGuestAllocator *a /* Put descriptor to the ring */ e1000e_rx_ring_push(d, &descr); =20 - /* Wait for TX WB interrupt */ + /* Wait for TX WB interrupt (this clears the MSIX PBA) */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert RXQ0 cau= se */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_RX0_MSG_ID)); =20 /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index 925654c7fd4..8ef6a04f43e 100644 --- a/tests/qtest/libqos/e1000e.c +++ b/tests/qtest/libqos/e1000e.c @@ -83,7 +83,7 @@ void e1000e_wait_isr(QE1000E *d, uint16_t msg_id) guint64 end_time =3D g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; =20 do { - if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) { + if (qpci_msix_test_clear_pending(&d_pci->pci_dev, msg_id)) { return; } qtest_clock_step(d_pci->pci_dev.bus->qts, 10000); --=20 2.45.2