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From: Frederic Konrad <fkonrad@amd.com>
To: <qemu-riscv@nongnu.org>
CC: <palmer@dabbelt.com>, <alistair.francis@wdc.com>, <bmeng.cn@gmail.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>, <qemu-devel@nongnu.org>,
<francisco.iglesias@amd.com>, <Luc.Michel@amd.com>, Frederic Konrad
<fkonrad@amd.com>
Subject: [PATCH 1/3] target/riscv: add a trap-misaligned-access property
Date: Wed, 11 Dec 2024 22:19:31 +0100
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On riscv target, misaligned accesses are either authorized and implemented =
in
hardware, or unimplemented and generate a trap to be implemented in softwar=
e.
At the moment misaligned accesses for rvi just succeed, the intention of th=
is
new property is to let the user choose to have a trap when a misaligned acc=
ess
happens.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..1696d3db2a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2697,6 +2697,11 @@ static Property riscv_cpu_properties[] =3D {
* it with -x and default to 'false'.
*/
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
+ /*
+ * when set, misaligned accesses will generate a trap.
+ */
+ DEFINE_PROP_BOOL("trap-misaligned-access", RISCVCPU,
+ cfg.trap_misaligned_access, false),
DEFINE_PROP_END_OF_LIST(),
};
=20
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..cc560371a1 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -173,6 +173,7 @@ struct RISCVCPUConfig {
bool pmp;
bool debug;
bool misa_w;
+ bool trap_misaligned_access;
=20
bool short_isa_string;
=20
--=20
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From: Frederic Konrad <fkonrad@amd.com>
To: <qemu-riscv@nongnu.org>
CC: <palmer@dabbelt.com>, <alistair.francis@wdc.com>, <bmeng.cn@gmail.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>, <qemu-devel@nongnu.org>,
<francisco.iglesias@amd.com>, <Luc.Michel@amd.com>, Frederic Konrad
<fkonrad@amd.com>
Subject: [PATCH 2/3] target/riscv: generate misaligned access trap for rvi
insn
Date: Wed, 11 Dec 2024 22:19:32 +0100
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Now there is an option to enable misaligned accesses traps, check the align=
ment
during load and store for the RVI instructions. Do not generate them if the
zama16b extension is there.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr=
ans/trans_rvi.c.inc
index 96c218a9d7..1283207fc7 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -323,6 +323,10 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Mem=
Op memop)
{
bool out;
=20
+ if (ctx->cfg_ptr->trap_misaligned_access && !ctx->cfg_ptr->ext_zama16b=
) {
+ memop |=3D MO_ALIGN;
+ }
+
if (ctx->cfg_ptr->ext_zama16b) {
memop |=3D MO_ATOM_WITHIN16;
}
@@ -424,6 +428,9 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a=
, MemOp memop)
=20
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
+ if (ctx->cfg_ptr->trap_misaligned_access && !ctx->cfg_ptr->ext_zama16b=
) {
+ memop |=3D MO_ALIGN;
+ }
if (ctx->cfg_ptr->ext_zama16b) {
memop |=3D MO_ATOM_WITHIN16;
}
--=20
2.43.5
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From: Frederic Konrad <fkonrad@amd.com>
To: <qemu-riscv@nongnu.org>
CC: <palmer@dabbelt.com>, <alistair.francis@wdc.com>, <bmeng.cn@gmail.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>, <qemu-devel@nongnu.org>,
<francisco.iglesias@amd.com>, <Luc.Michel@amd.com>, Frederic Konrad
<fkonrad@amd.com>
Subject: [PATCH 3/3] target/riscv: fix the trap generation for conditional
store
Date: Wed, 11 Dec 2024 22:19:33 +0100
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From Unpriviledged ISA manual:
"For LR and SC, the Zalrsc extension requires that the address held in rs1 =
be
naturally aligned to the size of the operand (i.e., eight-byte aligned for
doublewords and four-byte aligned for words). If the address is not natural=
ly
aligned, an address-misaligned exception or an access-fault exception will =
be
generated. The access-fault exception can be generated for a memory access =
that
would otherwise be able to complete except for the misalignment, if the
misaligned access should not be emulated."
Here nothing checks that the address is naturally aligned, so this fixes th=
at
wrong behavior by raising address-misaligned exception if the address in rs1
is not naturally aligned.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr=
ans/trans_rva.c.inc
index 9cf3ae8019..30a047164c 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -58,11 +58,30 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Me=
mOp mop)
static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv dest, src1, src2;
+ TCGv tmp =3D tcg_temp_new();
+ TCGLabel *l3 =3D gen_new_label();
TCGLabel *l1 =3D gen_new_label();
TCGLabel *l2 =3D gen_new_label();
=20
decode_save_opc(ctx, 0);
src1 =3D get_address(ctx, a->rs1, 0);
+ /*
+ * A misaligned store trap should be triggered even if the store should
+ * fail due to the reservation.
+ */
+ tcg_gen_andi_tl(tmp, src1, ~((uint64_t)0) << memop_alignment_bits(mop)=
);
+ tcg_gen_brcond_tl(TCG_COND_EQ, tmp, src1, l3);
+
+ /*
+ * Store the faulty address, and the actual PC. Then generate the
+ * exception.
+ */
+ tcg_gen_st_tl(src1, tcg_env, offsetof(CPURISCVState, badaddr));
+ gen_pc_plus_diff(cpu_pc, ctx, 0);
+ gen_helper_raise_exception(tcg_env,
+ tcg_constant_i32(RISCV_EXCP_STORE_AMO_ADDR_=
MIS));
+
+ gen_set_label(l3);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
=20
/*
--=20
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