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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934025; x=1734538825; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ec4PeXlmg7CtR/PXfmSknGAM8RrcTIj+cvTbuOFtEy4=; b=pSTaD1Nm43/gBYTdPld+9u59QRWGv8PjPYCTHMftgKH2i25lolhahKyLQxoU5n7RSq aqaHBrIhX+yCy0Q+WglIHkEQV6tA3gxEI44K7ZJsJp/5zPMjQmsSaj8O1g9gQa6cXHOj zqpaCuKE1Ehon6hiQUNnZHRSEpPRlUn+oS8ocDjWErCIgyCFUY6Luyhp1JpR1Z0uULhV ikntkT5wJo13kqQTSqCDXWiODen6jdPcuBx5zpMhVyOxvQd/JfPHiDMHhrfO9e/KIeGg jYk0oyTZmrb0o6/QQ5B2BGus5emN+gGFcgjE0p6Rex2sGY1dHepgOmZdqJKnjlCazplK uvqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934025; x=1734538825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ec4PeXlmg7CtR/PXfmSknGAM8RrcTIj+cvTbuOFtEy4=; b=p5gIK55mq8hj8CKDgNDaRFh2TGTp1iaPtFSkB8gr5xjzZqlggyTNiHS2u2ttXmBTY8 6H3/T0PiG6T9+JRiL/25+T4cY3Yq6mAkmH0GYpXnuz6xv6ATSYX73RlAhxZn6rAXKcox Z8AbJlYzoNg8ByVEcW4XIlhBs3Vxn0IOutCFLHia5//tbFgDxnFD1Lc2viAxM2AUnqkb jnoxDmyhelAi5mTIT0VxApNJdgpkg8zW/q8yCUA/idQRMnKfdYx+dCq75g8ZrBtTtEHQ XsHE4Sc9vBjI9tGcMgAHi3PUrg3HRUArhRPPC4COaSYU41rqUpFA64EwNu/TR2VTVAQF Tthw== X-Gm-Message-State: AOJu0Yz9yZTAGGTaCycBXFqOf0sr+HDJVp2qjYcZYbE+OPtgsKOakN4H ZVAOllpZKeyTFG+9GkSN9pU72oSAg6dbYNmOSxrRDDS4GVDuzqPumyZsZlzjL8lqRhvPnPdt/hp z X-Gm-Gg: ASbGnctWGYqD6efCpcXSj24svRWaTmRxi1WlV8XCty2ddXQuoAyEd03o8DC+jHmP6l/ UOzKswwHckbfzg6gb2FALKbD+y3/PchkTzXIU6FU1Lcnb/ul+q7HS7xrdijfnIobVgSpTo2C+I+ xxW9Qxnrx5XPobKcGaNlxhNJkk4MST8PA/e4CyqHtPmq8Q2HJiU1/nx27OXO22ju1UPID0f4Emp 0Hj+asnWQEZXlWaH8GTgHM72QzJkqqtpNewNHlOGXy8ftPtWM1XvzKR6faR X-Google-Smtp-Source: AGHT+IHJnppq2CoS0hE17Vt3ZVYBR9CTS+SmhdW4L/YKW64+BkqDPO0jnveWamUnTkaMbtUnm/vgmg== X-Received: by 2002:a05:600c:1c82:b0:434:a04f:2557 with SMTP id 5b1f17b1804b1-4361c396b7cmr27999955e9.4.1733934025481; Wed, 11 Dec 2024 08:20:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:06 +0000 Message-Id: <20241211162004.2795499-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1733934420687116601 Content-Type: text/plain; charset="utf-8" Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-10-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status= ); =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b= _cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,ze= ro,nan) --=20 2.34.1