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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 1/6] target/arm: Implement fine-grained-trap handling for
FEAT_XS
Date: Wed, 11 Dec 2024 14:44:35 +0000
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FEAT_XS introduces a set of new TLBI maintenance instructions with an
"nXS" qualifier. These behave like the stardard ones except that
they do not wait for memory accesses with the XS attribute to
complete. They have an interaction with the fine-grained-trap
handling: the FGT bits that a hypervisor can use to trap TLBI
maintenance instructions normally trap also the nXS variants, but the
hypervisor can elect to not trap the nXS variants by setting
HCRX_EL2.FGTnXS to 1.
Add support to our FGT mechanism for these TLBI bits. For each
TLBI-trapping FGT bit we define, for example:
* FGT_TLBIVAE1 -- the same value we do at present for the
normal variant of the insn
* FGT_TLBIVAE1NXS -- for the nXS qualified insn; the value of
this enum has an NXS bit ORed into it
In access_check_cp_reg() we can then ignore the trap bit for an
access where ri->fgt has the NXS bit set and HCRX_EL2.FGTnXS is 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpregs.h | 72 ++++++++++++++++++++++----------------
target/arm/cpu-features.h | 5 +++
target/arm/helper.c | 5 ++-
target/arm/tcg/op_helper.c | 11 +++++-
4 files changed, 61 insertions(+), 32 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index cc7c54378f4..87704762ef9 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -621,6 +621,7 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
=20
+FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
/* Which fine-grained trap bit register to check, if any */
FIELD(FGT, TYPE, 10, 3)
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
@@ -639,6 +640,17 @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the ui=
nt64_t */
#define DO_REV_BIT(REG, BITNAME) \
FGT_##BITNAME =3D FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
=20
+/*
+ * The FGT bits for TLBI maintenance instructions accessible at EL1 always
+ * affect the "normal" TLBI insns; they affect the corresponding TLBI insns
+ * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g.
+ * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use
+ * for the nXS qualified insn.
+ */
+#define DO_TLBINXS_BIT(REG, BITNAME) \
+ FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
+ FGT_##BITNAME##NXS =3D FGT_##BITNAME | R_FGT_NXS_MASK
+
typedef enum FGTBit {
/*
* These bits tell us which register arrays to use:
@@ -772,36 +784,36 @@ typedef enum FGTBit {
DO_BIT(HFGITR, ATS1E0W),
DO_BIT(HFGITR, ATS1E1RP),
DO_BIT(HFGITR, ATS1E1WP),
- DO_BIT(HFGITR, TLBIVMALLE1OS),
- DO_BIT(HFGITR, TLBIVAE1OS),
- DO_BIT(HFGITR, TLBIASIDE1OS),
- DO_BIT(HFGITR, TLBIVAAE1OS),
- DO_BIT(HFGITR, TLBIVALE1OS),
- DO_BIT(HFGITR, TLBIVAALE1OS),
- DO_BIT(HFGITR, TLBIRVAE1OS),
- DO_BIT(HFGITR, TLBIRVAAE1OS),
- DO_BIT(HFGITR, TLBIRVALE1OS),
- DO_BIT(HFGITR, TLBIRVAALE1OS),
- DO_BIT(HFGITR, TLBIVMALLE1IS),
- DO_BIT(HFGITR, TLBIVAE1IS),
- DO_BIT(HFGITR, TLBIASIDE1IS),
- DO_BIT(HFGITR, TLBIVAAE1IS),
- DO_BIT(HFGITR, TLBIVALE1IS),
- DO_BIT(HFGITR, TLBIVAALE1IS),
- DO_BIT(HFGITR, TLBIRVAE1IS),
- DO_BIT(HFGITR, TLBIRVAAE1IS),
- DO_BIT(HFGITR, TLBIRVALE1IS),
- DO_BIT(HFGITR, TLBIRVAALE1IS),
- DO_BIT(HFGITR, TLBIRVAE1),
- DO_BIT(HFGITR, TLBIRVAAE1),
- DO_BIT(HFGITR, TLBIRVALE1),
- DO_BIT(HFGITR, TLBIRVAALE1),
- DO_BIT(HFGITR, TLBIVMALLE1),
- DO_BIT(HFGITR, TLBIVAE1),
- DO_BIT(HFGITR, TLBIASIDE1),
- DO_BIT(HFGITR, TLBIVAAE1),
- DO_BIT(HFGITR, TLBIVALE1),
- DO_BIT(HFGITR, TLBIVAALE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVALE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIASIDE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAAE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVALE1),
+ DO_TLBINXS_BIT(HFGITR, TLBIVAALE1),
DO_BIT(HFGITR, CFPRCTX),
DO_BIT(HFGITR, DVPRCTX),
DO_BIT(HFGITR, CPPRCTX),
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index e806f138b8f..30302d6c5b4 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -474,6 +474,11 @@ static inline bool isar_feature_aa64_fcma(const ARMISA=
Registers *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0;
}
=20
+static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) !=3D 0;
+}
+
/*
* These are the values from APA/API/APA3.
* In general these must be compared '>=3D', per the normal Arm ARM
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 910ae62c476..8e62769ec0d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5346,10 +5346,13 @@ static void hcrx_write(CPUARMState *env, const ARMC=
PRegInfo *ri,
valid_mask |=3D HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
}
/* FEAT_CMOW adds CMOW */
-
if (cpu_isar_feature(aa64_cmow, cpu)) {
valid_mask |=3D HCRX_CMOW;
}
+ /* FEAT_XS adds FGTnXS, FnXS */
+ if (cpu_isar_feature(aa64_xs, cpu)) {
+ valid_mask |=3D HCRX_FGTNXS | HCRX_FNXS;
+ }
=20
/* Clear RES0 bits. */
env->cp15.hcrx_el2 =3D value & valid_mask;
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 1ecb4659889..1161d301b71 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -817,6 +817,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *en=
v, uint32_t key,
unsigned int idx =3D FIELD_EX32(ri->fgt, FGT, IDX);
unsigned int bitpos =3D FIELD_EX32(ri->fgt, FGT, BITPOS);
bool rev =3D FIELD_EX32(ri->fgt, FGT, REV);
+ bool nxs =3D FIELD_EX32(ri->fgt, FGT, NXS);
bool trapbit;
=20
if (ri->fgt & FGT_EXEC) {
@@ -830,7 +831,15 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e=
nv, uint32_t key,
trapword =3D env->cp15.fgt_write[idx];
}
=20
- trapbit =3D extract64(trapword, bitpos, 1);
+ if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) {
+ /*
+ * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for
+ * TLBI maintenance insns does *not* apply to the nXS variant.
+ */
+ trapbit =3D 0;
+ } else {
+ trapbit =3D extract64(trapword, bitpos, 1);
+ }
if (trapbit !=3D rev) {
res =3D CP_ACCESS_TRAP_EL2;
goto fail;
--=20
2.34.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 2/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS
insns
Date: Wed, 11 Dec 2024 14:44:36 +0000
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All of the TLBI insns with an NXS variant put that variant at the
same encoding but with a CRn field that is one greater than for the
original TLBI insn. To avoid having to define every TLBI insn
effectively twice, once in the normal way and once in a set of cpreg
arrays that are only registered when FEAT_XS is present, we define a
new ARM_CP_ADD_TLB_NXS type flag for cpregs. When this flag is set
in a cpreg struct and FEAT_XS is present,
define_one_arm_cp_reg_with_opaque() will automatically add a second
cpreg to the hash table for the TLBI NXS insn with:
* the crn+1 encoding
* an FGT field that indicates that it should honour HCR_EL2.FGTnXS
* a name with the "NXS" suffix
(If there are future TLBI NXS insns that don't use this same
encoding convention, it is also possible to define them manually.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpregs.h | 8 ++++++++
target/arm/helper.c | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 87704762ef9..1759d9defbe 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -126,6 +126,14 @@ enum {
* equivalent EL1 register when FEAT_NV2 is enabled.
*/
ARM_CP_NV2_REDIRECT =3D 1 << 20,
+ /*
+ * Flag: this is a TLBI insn which (when FEAT_XS is present) also has
+ * an NXS variant at the same encoding except that crn is 1 greater,
+ * so when registering this cpreg automatically also register one
+ * for the TLBI NXS variant. (For QEMU the NXS variant behaves
+ * identically to the normal one, other than FGT trapping handling.)
+ */
+ ARM_CP_ADD_TLBI_NXS =3D 1 << 21,
};
=20
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8e62769ec0d..c2a70f8c053 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9146,6 +9146,31 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
if (r->state !=3D state && r->state !=3D ARM_CP_STATE_=
BOTH) {
continue;
}
+ if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
+ cpu_isar_feature(aa64_xs, cpu)) {
+ /*
+ * This is a TLBI insn which has an NXS variant. T=
he
+ * NXS variant is at the same encoding except that
+ * crn is +1, and has the same behaviour except for
+ * fine-grained trapping. Add the NXS insn here and
+ * then fall through to add the normal register.
+ * add_cpreg_to_hashtable() copies the cpreg struct
+ * and name that it is passed, so it's OK to use
+ * a local struct here.
+ */
+ ARMCPRegInfo nxs_ri =3D *r;
+ g_autofree char *name =3D g_strdup_printf("%sNXS",=
r->name);
+
+ assert(state =3D=3D ARM_CP_STATE_AA64);
+ assert(nxs_ri.crn < 0xf);
+ nxs_ri.crn++;
+ if (nxs_ri.fgt) {
+ nxs_ri.fgt |=3D R_FGT_NXS_MASK;
+ }
+ add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
+ ARM_CP_SECSTATE_NS,
+ crm, opc1, opc2, name);
+ }
if (state =3D=3D ARM_CP_STATE_AA32) {
/*
* Under AArch32 CP registers can be common
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 3/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI
insns
Date: Wed, 11 Dec 2024 14:44:37 +0000
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Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant.
This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI
insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/tlb-insns.c | 202 +++++++++++++++++++++++--------------
1 file changed, 124 insertions(+), 78 deletions(-)
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 0f67294edc4..fadc61a76e9 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -617,95 +617,107 @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] =3D {
/* AArch64 TLBI operations */
{ .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVMALLE1IS,
.writefn =3D tlbi_aa64_vmalle1is_write },
{ .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAE1IS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIASIDE1IS,
.writefn =3D tlbi_aa64_vmalle1is_write },
{ .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAAE1IS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVALE1IS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAALE1IS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVMALLE1,
.writefn =3D tlbi_aa64_vmalle1_write },
{ .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAE1,
.writefn =3D tlbi_aa64_vae1_write },
{ .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIASIDE1,
.writefn =3D tlbi_aa64_vmalle1_write },
{ .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAAE1,
.writefn =3D tlbi_aa64_vae1_write },
{ .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVALE1,
.writefn =3D tlbi_aa64_vae1_write },
{ .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAALE1,
.writefn =3D tlbi_aa64_vae1_write },
{ .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ipas2e1is_write },
{ .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ipas2e1is_write },
{ .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1is_write },
{ .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1is_write },
{ .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ipas2e1_write },
{ .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ipas2e1_write },
{ .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1_write },
{ .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1is_write },
};
=20
@@ -732,54 +744,60 @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D {
.writefn =3D tlbimva_hyp_is_write },
{ .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_alle2_write },
{ .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2_write },
{ .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2_write },
{ .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_alle2is_write },
{ .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2is_write },
{ .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2is_write },
};
=20
static const ARMCPRegInfo tlbi_el3_cp_reginfo[] =3D {
{ .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle3is_write },
{ .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3is_write },
{ .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3is_write },
{ .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle3_write },
{ .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3_write },
{ .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3_write },
};
=20
@@ -981,204 +999,232 @@ static void tlbi_aa64_ripas2e1is_write(CPUARMState =
*env,
static const ARMCPRegInfo tlbirange_reginfo[] =3D {
{ .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAE1IS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAAE1IS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVALE1IS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbis,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAALE1IS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAE1OS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAAE1OS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVALE1OS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAALE1OS,
.writefn =3D tlbi_aa64_rvae1is_write },
{ .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAE1,
.writefn =3D tlbi_aa64_rvae1_write },
{ .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAAE1,
.writefn =3D tlbi_aa64_rvae1_write },
{ .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVALE1,
.writefn =3D tlbi_aa64_rvae1_write },
{ .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+ .access =3D PL1_W, .accessfn =3D access_ttlb,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIRVAALE1,
.writefn =3D tlbi_aa64_rvae1_write },
{ .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ripas2e1is_write },
{ .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ripas2e1is_write },
{ .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2is_write },
{ .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2is_write },
{ .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ripas2e1_write },
{ .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_ripas2e1_write },
{ .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2is_write },
{ .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2is_write },
{ .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2_write },
{ .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_rvae2_write },
{ .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3is_write },
{ .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3is_write },
{ .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3is_write },
{ .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3is_write },
{ .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3_write },
{ .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_rvae3_write },
};
=20
static const ARMCPRegInfo tlbios_reginfo[] =3D {
{ .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVMALLE1OS,
.writefn =3D tlbi_aa64_vmalle1is_write },
{ .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
.fgt =3D FGT_TLBIVAE1OS,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIASIDE1OS,
.writefn =3D tlbi_aa64_vmalle1is_write },
{ .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAAE1OS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVALE1OS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7,
- .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+ .access =3D PL1_W, .accessfn =3D access_ttlbos,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt =3D FGT_TLBIVAALE1OS,
.writefn =3D tlbi_aa64_vae1is_write },
{ .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_alle2is_write },
{ .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2is_write },
{ .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1is_write },
{ .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+ .access =3D PL2_W,
+ .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UN=
DEF,
.writefn =3D tlbi_aa64_vae2is_write },
{ .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6,
- .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle1is_write },
{ .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0,
- .access =3D PL2_W, .type =3D ARM_CP_NOP },
+ .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3,
- .access =3D PL2_W, .type =3D ARM_CP_NOP },
+ .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4,
- .access =3D PL2_W, .type =3D ARM_CP_NOP },
+ .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7,
- .access =3D PL2_W, .type =3D ARM_CP_NOP },
+ .access =3D PL2_W, .type =3D ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_alle3is_write },
{ .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3is_write },
{ .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
- .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+ .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn =3D tlbi_aa64_vae3is_write },
};
=20
--=20
2.34.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 4/6] target/arm: Add decodetree entry for DSB nXS variant
Date: Wed, 11 Dec 2024 14:44:38 +0000
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From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
The DSB nXS variant is always both a reads and writes request type.
Ignore the domain field like we do in plain DSB and perform a full
system barrier operation.
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
[PMM: added missing "UNDEF unless feature present" check]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 9 +++++++++
2 files changed, 12 insertions(+)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 331a8e180c0..c4f516abc18 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -245,6 +245,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
=20
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
+# For the DSB nXS variant, types always equals MBReqTypes_All and we ignor=
e the
+# domain bits.
+DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111
=20
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index b2851ea5032..953386c0416 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1959,6 +1959,15 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_D=
MB *a)
return true;
}
=20
+static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
+{
+ if (!dc_isar_feature(aa64_xs, s)) {
+ return false;
+ }
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
+ return true;
+}
+
static bool trans_ISB(DisasContext *s, arg_ISB *a)
{
/*
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 5/6] target/arm: Enable FEAT_XS for the max cpu
Date: Wed, 11 Dec 2024 14:44:39 +0000
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From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Add entry for FEAT_XS to documentation]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 38534dcdd32..60176d08597 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -154,6 +154,7 @@ the following architecture extensions:
- FEAT_VMID16 (16-bit VMID)
- FEAT_WFxT (WFE and WFI instructions with timeout)
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
+- FEAT_XS (XS attribute)
=20
For information on the specifics of these extensions, please refer
to the `Arm Architecture Reference Manual for A-profile architecture
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 2963d7510f3..449cec5a626 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF=
16 */
t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
+ t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
cpu->isar.id_aa64isar1 =3D t;
=20
t =3D cpu->isar.id_aa64isar2;
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH v2 6/6] tests/tcg/aarch64: add system test for FEAT_XS
Date: Wed, 11 Dec 2024 14:44:40 +0000
Message-Id: <20241211144440.2700268-7-peter.maydell@linaro.org>
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From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Add system test to make sure FEAT_XS is enabled for max cpu emulation
and that QEMU doesn't crash when encountering an NXS instruction
variant.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
[PMM: In ISAR field test, mask with 0xf, not 0xff; use < rather
than an equality test to follow the standard ID register field
check guidelines]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/system/feat-xs.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 tests/tcg/aarch64/system/feat-xs.c
diff --git a/tests/tcg/aarch64/system/feat-xs.c b/tests/tcg/aarch64/system/=
feat-xs.c
new file mode 100644
index 00000000000..f310fc837e0
--- /dev/null
+++ b/tests/tcg/aarch64/system/feat-xs.c
@@ -0,0 +1,27 @@
+/*
+ * FEAT_XS Test
+ *
+ * Copyright (c) 2024 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <minilib.h>
+#include <stdint.h>
+
+int main(void)
+{
+ uint64_t isar1;
+
+ asm volatile ("mrs %0, id_aa64isar1_el1" : "=3Dr"(isar1));
+ if (((isar1 >> 56) & 0xf) < 1) {
+ ml_printf("FEAT_XS not supported by CPU");
+ return 1;
+ }
+ /* VMALLE1NXS */
+ asm volatile (".inst 0xd508971f");
+ /* VMALLE1OSNXS */
+ asm volatile (".inst 0xd508911f");
+
+ return 0;
+}
--=20
2.34.1