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To: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Bin Meng
 <bmeng.cn@gmail.com>, "open list:SD (Secure Card)" <qemu-block@nongnu.org>,
 "open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
 <yunlin.tang@aspeedtech.com>
Subject: [RFC.PATCH v1 1/2] sd:sdhci: Fix boundary_count overflow in
 sdhci_sdma_transfer_multi_blocks
Date: Wed, 11 Dec 2024 17:51:09 +0800
Message-ID: <20241211095111.1421928-2-jamin_lin@aspeedtech.com>
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
From: Jamin Lin via <qemu-devel@nongnu.org>
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How to reproduce it:
1. The value of "s->blksie" was 0x7200. The bits[14:12] was "111", so the b=
uffer
   boundary was 0x80000.(512Kbytes). This SDMA buffer boundary the same as
   u-boot default value.
   The bit[11:0] is "001000000000", so the block size is 0x200.(512bytes)
2. The SDMA address was 0x83123456 which was not page aligned and
   "s->sdmasysad % boundary_chk" was 0x23456. The value of boundary_count w=
as
   0x5cbaa.("boundary_chk - (s->sdmasysad % boundary_chk)" -->
   "(0x80000 - 0x23456)")

However, boundary_count did not aligned the block size 512 bytes and the SD=
MA
address is not page aligned(0x80000), so the following if-statement never b=
e true,
```
if (((boundary_count + begin) < block_size) && page_aligned)
````

Finally, it caused boundary_count overflow because its data type was uint32=
_t.
Ex: the last boundary_count was 0x1aa and "0x1aa - 0x200" became "0xffffffa=
a".
It is the wrong behavior.

To fix it, it seems we can directly check the "boundary_count < blocksize"
instead of "boundary_count < blocksize && page_aligned"

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/sd/sdhci.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 37875c02c3..47d96b935b 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -590,7 +590,6 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_=
t value, unsigned size)
 /* Multi block SDMA transfer */
 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
 {
-    bool page_aligned =3D false;
     unsigned int begin;
     const uint16_t block_size =3D s->blksize & BLOCK_SIZE_MASK;
     uint32_t boundary_chk =3D 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12=
) + 12);
@@ -601,15 +600,6 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIStat=
e *s)
         return;
     }
=20
-    /*
-     * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account f=
or
-     * possible stop at page boundary if initial address is not page align=
ed,
-     * allow them to work properly
-     */
-    if ((s->sdmasysad % boundary_chk) =3D=3D 0) {
-        page_aligned =3D true;
-    }
-
     s->prnsts |=3D SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE;
     if (s->trnmod & SDHC_TRNS_READ) {
         s->prnsts |=3D SDHC_DOING_READ;
@@ -618,7 +608,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState=
 *s)
                 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
             }
             begin =3D s->data_count;
-            if (((boundary_count + begin) < block_size) && page_aligned) {
+            if (((boundary_count + begin) < block_size)) {
                 s->data_count =3D boundary_count + begin;
                 boundary_count =3D 0;
              } else {
@@ -634,7 +624,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState=
 *s)
             if (s->data_count =3D=3D block_size) {
                 s->data_count =3D 0;
             }
-            if (page_aligned && boundary_count =3D=3D 0) {
+            if (boundary_count =3D=3D 0) {
                 break;
             }
         }
@@ -642,7 +632,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState=
 *s)
         s->prnsts |=3D SDHC_DOING_WRITE;
         while (s->blkcnt) {
             begin =3D s->data_count;
-            if (((boundary_count + begin) < block_size) && page_aligned) {
+            if (((boundary_count + begin) < block_size)) {
                 s->data_count =3D boundary_count + begin;
                 boundary_count =3D 0;
              } else {
@@ -659,7 +649,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState=
 *s)
                     s->blkcnt--;
                 }
             }
-            if (page_aligned && boundary_count =3D=3D 0) {
+            if (boundary_count =3D=3D 0) {
                 break;
             }
         }
--=20
2.34.1
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To: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Bin Meng
 <bmeng.cn@gmail.com>, "open list:SD (Secure Card)" <qemu-block@nongnu.org>,
 "open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
 <yunlin.tang@aspeedtech.com>
Subject: [RFC.PATCH v1 2/2] sd:sdhci: Fix data transfer did not complete if
 data size is bigger then SDMA Buffer Boundary
Date: Wed, 11 Dec 2024 17:51:10 +0800
Message-ID: <20241211095111.1421928-3-jamin_lin@aspeedtech.com>
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According to the design of sdhci_sdma_transfer_multi_blocks, if the
"s->blkcnt * 512" was bigger than the SDMA Buffer boundary, it breaked the
while loop of data transfer and set SDHC_NISEN_DMA in the normal interreupt
status to notify the firmware that this SDMA boundary buffer Transfer Compl=
ete
and firmware should set the system address of the next SDMA boundary buffer
for the remaining data transfer.

However, after firmware set the system address of the next SDMA boundary bu=
ffer
in the SDMA System Address Register(0x00), SDHCI modle did not start the da=
ta
transfer, again. Finally, firmware breaked the data transfer because firmwa=
re
did not receive the DMA Interrupt and Tansfer Complete Interrupt from SDHCI
model.

Error log from u-boot
```
sdhci_transfer_data: Transfer data timeout
 ** fs_devread read error - block
```

According to the following mention from SDMA System Address Refister of SDH=
CI
spec,
'''
This register contains the system memory address for an SDMA transfer in
32-bit addressing mode. When the Host Controller stops an SDMA transfer,
this register shall point to the system address of the next contiguous data
position.
It can be accessed only if no transaction is executing (i.e., after a trans=
action
has stopped). Reading this register during SDMA transfers may return an
invalid value.
The Host Driver shall initialize this register before starting an SDMA
transaction.
After SDMA has stopped, the next system address of the next contiguous
data position can be read from this register.
The SDMA transfer waits at the every boundary specified by the SDMA
Buffer Boundary in the Block Size register. The Host Controller generates
DMA Interrupt to request the Host Driver to update this register. The Host
Driver sets the next system address of the next data position to this regis=
ter.
When the most upper byte of this register (003h) is written, the Host Contr=
oller
restarts the SDMA transfer.
''',

restrat the data transfer if firmware set the SDMA System Address, s->blkcnt
is bigger than 0 and SDHCI is in the data transfer state.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/sd/sdhci.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 47d96b935b..53c23c5437 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1170,6 +1170,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va=
l, unsigned size)
                     sdhci_sdma_transfer_single_block(s);
                 }
             }
+        } else if (TRANSFERRING_DATA(s->prnsts)) {
+            /* restarts the SDMA transfer if blkcnt is not zero  */
+            if (s->blkcnt && SDHC_DMA_TYPE(s->hostctl1) =3D=3D SDHC_CTRL_S=
DMA) {
+                if (s->trnmod & SDHC_TRNS_MULTI) {
+                    sdhci_sdma_transfer_multi_blocks(s);
+                } else {
+                    sdhci_sdma_transfer_single_block(s);
+                }
+            }
         }
         break;
     case SDHC_BLKSIZE:
--=20
2.34.1