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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 01/24] arm: Remove tacoma-bmc machine
Date: Wed, 11 Dec 2024 07:30:35 +0100
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Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
docs/about/deprecated.rst | 8 --------
docs/about/removed-features.rst | 10 ++++++++++
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c | 28 ----------------------------
4 files changed, 10 insertions(+), 37 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index d8dc29d0a4ee..267892b62f23 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -263,14 +263,6 @@ images are not available, OpenWRT dropped support in 2=
019, U-Boot in
2017, Linux also is dropping support in 2024. It is time to let go of
this ancient hardware and focus on newer CPUs and platforms.
=20
-Arm ``tacoma-bmc`` machine (since 9.1)
-''''''''''''''''''''''''''''''''''''''''
-
-The ``tacoma-bmc`` machine was a board including an AST2600 SoC based
-BMC and a witherspoon like OpenPOWER system. It was used for bring up
-of the AST2600 SoC in labs. It can be easily replaced by the
-``rainier-bmc`` machine which is a real product.
-
Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pm=
u`` machines (since 9.2)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''=
''''''''''''''''''''''''
=20
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.=
rst
index ee6455aeeebe..9bebee795c0e 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -1019,6 +1019,16 @@ Aspeed ``swift-bmc`` machine (removed in 7.0)
This machine was removed because it was unused. Alternative AST2500 based
OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
=20
+Aspeed ``tacoma-bmc`` machine (removed in 10.0)
+'''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``tacoma-bmc`` machine was removed because it didn't bring much
+compared to the ``rainier-bmc`` machine. Also, the ``tacoma-bmc`` was
+a board used for bring up of the AST2600 SoC that never left the
+labs. It can be easily replaced by the ``rainier-bmc`` machine, which
+was the actual final product, or by the ``ast2600-evb`` with some
+tweaks.
+
ppc ``taihu`` machine (removed in 7.2)
'''''''''''''''''''''''''''''''''''''''''''''
=20
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index d17fe7a4fc81..fa4aa28eeff2 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -32,7 +32,6 @@ AST2500 SoC based machines :
AST2600 SoC based machines :
=20
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
-- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
- ``rainier-bmc`` IBM Rainier POWER10 BMC
- ``fuji-bmc`` Facebook Fuji BMC
- ``bletchley-bmc`` Facebook Bletchley BMC
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6ca145362cbd..556498f2a061 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -185,10 +185,6 @@ struct AspeedMachineState {
#define AST2700_EVB_HW_STRAP2 0x00000003
#endif
=20
-/* Tacoma hardware value */
-#define TACOMA_BMC_HW_STRAP1 0x00000000
-#define TACOMA_BMC_HW_STRAP2 0x00000040
-
/* Rainier hardware value: (QEMU prototype) */
#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_=
EMMC)
#define RAINIER_BMC_HW_STRAP2 0x80000848
@@ -1425,26 +1421,6 @@ static void aspeed_machine_ast2600_evb_class_init(Ob=
jectClass *oc, void *data)
aspeed_machine_ast2600_class_emmc_init(oc);
};
=20
-static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc =3D MACHINE_CLASS(oc);
- AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc);
-
- mc->desc =3D "OpenPOWER Tacoma BMC (Cortex-A7)";
- amc->soc_name =3D "ast2600-a3";
- amc->hw_strap1 =3D TACOMA_BMC_HW_STRAP1;
- amc->hw_strap2 =3D TACOMA_BMC_HW_STRAP2;
- amc->fmc_model =3D "mx66l1g45g";
- amc->spi_model =3D "mx66l1g45g";
- amc->num_cs =3D 2;
- amc->macs_mask =3D ASPEED_MAC2_ON;
- amc->i2c_init =3D witherspoon_bmc_i2c_init; /* Same board layout */
- mc->default_ram_size =3D 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-
- mc->deprecation_reason =3D "Please use the similar 'rainier-bmc' machi=
ne";
-};
-
static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc =3D MACHINE_CLASS(oc);
@@ -1766,10 +1742,6 @@ static const TypeInfo aspeed_machine_types[] =3D {
.name =3D MACHINE_TYPE_NAME("yosemitev2-bmc"),
.parent =3D TYPE_ASPEED_MACHINE,
.class_init =3D aspeed_machine_yosemitev2_class_init,
- }, {
- .name =3D MACHINE_TYPE_NAME("tacoma-bmc"),
- .parent =3D TYPE_ASPEED_MACHINE,
- .class_init =3D aspeed_machine_tacoma_class_init,
}, {
.name =3D MACHINE_TYPE_NAME("tiogapass-bmc"),
.parent =3D TYPE_ASPEED_MACHINE,
--=20
2.47.1
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=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 02/24] hw/sd/aspeed_sdhci: Fix coding style
Date: Wed, 11 Dec 2024 07:30:36 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-2-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/sd/aspeed_sdhci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 98d5460905df..acd65382611c 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -87,10 +87,12 @@ static void aspeed_sdhci_write(void *opaque, hwaddr add=
r, uint64_t val,
sdhci->regs[TO_REG(addr)] =3D (uint32_t)val & ~ASPEED_SDHCI_INFO_R=
ESET;
break;
case ASPEED_SDHCI_SDIO_140:
- sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 0, =
32, val);
+ sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg,
+ 0, 32, val);
break;
case ASPEED_SDHCI_SDIO_144:
- sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg, 32,=
32, val);
+ sdhci->slots[0].capareg =3D deposit64(sdhci->slots[0].capareg,
+ 32, 32, val);
break;
case ASPEED_SDHCI_SDIO_148:
sdhci->slots[0].maxcurr =3D deposit64(sdhci->slots[0].maxcurr,
--=20
2.47.1
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To: qemu-arm@nongnu.org,
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 03/24] hw/arm/aspeed: Fix coding style
Date: Wed, 11 Dec 2024 07:30:37 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast2600.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index be3eb70cdd77..c40d3d84435f 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -541,7 +541,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev=
, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_=
GPIO]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
=20
--=20
2.47.1
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To: qemu-arm@nongnu.org,
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 04/24] hw:sdhci: Introduce a new "capareg" class member to set
the different Capability Registers
Date: Wed, 11 Dec 2024 07:30:38 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Currently, it set the hardcode value of capability registers to all ASPEED =
SOCs
However, the value of capability registers should be different for all ASPE=
ED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.
The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST26=
00.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
include/hw/sd/aspeed_sdhci.h | 12 +++++++--
hw/arm/aspeed_ast2400.c | 3 ++-
hw/arm/aspeed_ast2600.c | 7 +++---
hw/sd/aspeed_sdhci.c | 47 +++++++++++++++++++++++++++++++++++-
4 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index 057bc5f3d139..8083797e25bc 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -13,9 +13,11 @@
#include "qom/object.h"
=20
#define TYPE_ASPEED_SDHCI "aspeed.sdhci"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI)
+#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
+#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
+#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
+OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
=20
-#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
#define ASPEED_SDHCI_NUM_SLOTS 2
#define ASPEED_SDHCI_NUM_REGS (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t=
))
#define ASPEED_SDHCI_REG_SIZE 0x100
@@ -32,4 +34,10 @@ struct AspeedSDHCIState {
uint32_t regs[ASPEED_SDHCI_NUM_REGS];
};
=20
+struct AspeedSDHCIClass {
+ SysBusDeviceClass parent_class;
+
+ uint64_t capareg;
+};
+
#endif /* ASPEED_SDHCI_H */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index ecc81ecc79ce..3c1b4199452e 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -224,7 +224,8 @@ static void aspeed_ast2400_soc_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
object_initialize_child(obj, "gpio", &s->gpio, typename);
=20
- object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
+ snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+ object_initialize_child(obj, "sdc", &s->sdhci, typename);
=20
object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abor=
t);
=20
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index c40d3d84435f..b5703bd064c1 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -236,8 +236,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
=20
- object_initialize_child(obj, "sd-controller", &s->sdhci,
- TYPE_ASPEED_SDHCI);
+ snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+ object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
=20
object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abor=
t);
=20
@@ -247,8 +247,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
&s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
}
=20
- object_initialize_child(obj, "emmc-controller", &s->emmc,
- TYPE_ASPEED_SDHCI);
+ object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
=20
object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort=
);
=20
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index acd65382611c..ae2ec4a91644 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -148,6 +148,7 @@ static void aspeed_sdhci_realize(DeviceState *dev, Erro=
r **errp)
{
SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev);
AspeedSDHCIState *sdhci =3D ASPEED_SDHCI(dev);
+ AspeedSDHCIClass *asc =3D ASPEED_SDHCI_GET_CLASS(sdhci);
=20
/* Create input irqs for the slots */
qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
@@ -167,7 +168,7 @@ static void aspeed_sdhci_realize(DeviceState *dev, Erro=
r **errp)
}
=20
if (!object_property_set_uint(sdhci_slot, "capareg",
- ASPEED_SDHCI_CAPABILITIES, errp)) {
+ asc->capareg, errp)) {
return;
}
=20
@@ -218,12 +219,56 @@ static void aspeed_sdhci_class_init(ObjectClass *clas=
sp, void *data)
device_class_set_props(dc, aspeed_sdhci_properties);
}
=20
+static void aspeed_2400_sdhci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedSDHCIClass *asc =3D ASPEED_SDHCI_CLASS(klass);
+
+ dc->desc =3D "ASPEED 2400 SDHCI Controller";
+ asc->capareg =3D 0x0000000001e80080;
+}
+
+static void aspeed_2500_sdhci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedSDHCIClass *asc =3D ASPEED_SDHCI_CLASS(klass);
+
+ dc->desc =3D "ASPEED 2500 SDHCI Controller";
+ asc->capareg =3D 0x0000000001e80080;
+}
+
+static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedSDHCIClass *asc =3D ASPEED_SDHCI_CLASS(klass);
+
+ dc->desc =3D "ASPEED 2600 SDHCI Controller";
+ asc->capareg =3D 0x0000000701f80080;
+}
+
static const TypeInfo aspeed_sdhci_types[] =3D {
{
.name =3D TYPE_ASPEED_SDHCI,
.parent =3D TYPE_SYS_BUS_DEVICE,
.instance_size =3D sizeof(AspeedSDHCIState),
.class_init =3D aspeed_sdhci_class_init,
+ .class_size =3D sizeof(AspeedSDHCIClass),
+ .abstract =3D true,
+ },
+ {
+ .name =3D TYPE_ASPEED_2400_SDHCI,
+ .parent =3D TYPE_ASPEED_SDHCI,
+ .class_init =3D aspeed_2400_sdhci_class_init,
+ },
+ {
+ .name =3D TYPE_ASPEED_2500_SDHCI,
+ .parent =3D TYPE_ASPEED_SDHCI,
+ .class_init =3D aspeed_2500_sdhci_class_init,
+ },
+ {
+ .name =3D TYPE_ASPEED_2600_SDHCI,
+ .parent =3D TYPE_ASPEED_SDHCI,
+ .class_init =3D aspeed_2600_sdhci_class_init,
},
};
=20
--=20
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 05/24] hw/sd/aspeed_sdhci: Add AST2700 Support
Date: Wed, 11 Dec 2024 07:30:39 +0100
Message-ID: <20241211063058.1222038-6-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI c=
lass
init function and set the value of capability register to "0x0000000719f800=
80".
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
include/hw/sd/aspeed_sdhci.h | 1 +
hw/sd/aspeed_sdhci.c | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index 8083797e25bc..4ef177047114 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -16,6 +16,7 @@
#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
+#define TYPE_ASPEED_2700_SDHCI TYPE_ASPEED_SDHCI "-ast2700"
OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
=20
#define ASPEED_SDHCI_NUM_SLOTS 2
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index ae2ec4a91644..f82b05397e83 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -246,6 +246,15 @@ static void aspeed_2600_sdhci_class_init(ObjectClass *=
klass, void *data)
asc->capareg =3D 0x0000000701f80080;
}
=20
+static void aspeed_2700_sdhci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedSDHCIClass *asc =3D ASPEED_SDHCI_CLASS(klass);
+
+ dc->desc =3D "ASPEED 2700 SDHCI Controller";
+ asc->capareg =3D 0x0000000719f80080;
+}
+
static const TypeInfo aspeed_sdhci_types[] =3D {
{
.name =3D TYPE_ASPEED_SDHCI,
@@ -270,6 +279,11 @@ static const TypeInfo aspeed_sdhci_types[] =3D {
.parent =3D TYPE_ASPEED_SDHCI,
.class_init =3D aspeed_2600_sdhci_class_init,
},
+ {
+ .name =3D TYPE_ASPEED_2700_SDHCI,
+ .parent =3D TYPE_ASPEED_SDHCI,
+ .class_init =3D aspeed_2700_sdhci_class_init,
+ },
};
=20
DEFINE_TYPES(aspeed_sdhci_types)
--=20
2.47.1
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To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 06/24] aspeed/soc: Support SDHCI for AST2700
Date: Wed, 11 Dec 2024 07:30:40 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only suppor=
t 1
slot and registers base address is start at 0x1408_0000 and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-6-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 63d1fcb086d7..baddd35ecf7d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -65,6 +65,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
[ASPEED_DEV_I2C] =3D 0x14C0F000,
[ASPEED_DEV_GPIO] =3D 0x14C0B000,
[ASPEED_DEV_RTC] =3D 0x12C0F000,
+ [ASPEED_DEV_SDHCI] =3D 0x14080000,
};
=20
#define AST2700_MAX_IRQ 256
@@ -113,6 +114,7 @@ static const int aspeed_soc_ast2700_irqmap[] =3D {
[ASPEED_DEV_KCS] =3D 128,
[ASPEED_DEV_DP] =3D 28,
[ASPEED_DEV_I3C] =3D 131,
+ [ASPEED_DEV_SDHCI] =3D 133,
};
=20
/* GICINT 128 */
@@ -158,6 +160,7 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] =
=3D {
=20
/* GICINT 133 */
static const int aspeed_soc_ast2700_gic133_intcmap[] =3D {
+ [ASPEED_DEV_SDHCI] =3D 1,
[ASPEED_DEV_PECI] =3D 4,
};
=20
@@ -380,6 +383,14 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "gpio", &s->gpio, typename);
=20
object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
+
+ snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+ object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
+ object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abor=
t);
+
+ /* Init sd card slot class here so that they're under the correct pare=
nt */
+ object_initialize_child(obj, "sd-controller.sdhci",
+ &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
}
=20
/*
@@ -681,6 +692,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *de=
v, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
=20
+ /* SDHCI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+ sc->memmap[ASPEED_DEV_SDHCI]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--=20
2.47.1
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 07/24] aspeed/soc: Support eMMC for AST2700
Date: Wed, 11 Dec 2024 07:30:41 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_0000 and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-7-jamin_lin@aspeedtec=
h.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index baddd35ecf7d..23571584b2f6 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -391,6 +391,12 @@ static void aspeed_soc_ast2700_init(Object *obj)
/* Init sd card slot class here so that they're under the correct pare=
nt */
object_initialize_child(obj, "sd-controller.sdhci",
&s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
+
+ object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
+ object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort=
);
+
+ object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0=
],
+ TYPE_SYSBUS_SDHCI);
}
=20
/*
@@ -701,6 +707,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *de=
v, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
=20
+ /* eMMC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
+ sc->memmap[ASPEED_DEV_EMMC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--=20
2.47.1
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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>,
Thomas Huth <thuth@redhat.com>
Subject: [PULL 08/24] tests/functional: Introduce a specific test for ast1030
SoC
Date: Wed, 11 Dec 2024 07:30:42 +0100
Message-ID: <20241211063058.1222038-9-clg@redhat.com>
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This simply moves the ast1030 tests to a new test file. No changes.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-2-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/meson.build | 1 +
tests/functional/test_arm_aspeed.py | 64 ----------------
tests/functional/test_arm_aspeed_ast1030.py | 81 +++++++++++++++++++++
3 files changed, 82 insertions(+), 64 deletions(-)
create mode 100644 tests/functional/test_arm_aspeed_ast1030.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index d6d2c0196c76..66f10da99d63 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -66,6 +66,7 @@ tests_alpha_system_thorough =3D [
=20
tests_arm_system_thorough =3D [
'arm_aspeed',
+ 'arm_aspeed_ast1030',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed.py
index d88170ac2415..9e58fcd84009 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -19,70 +19,6 @@
from zipfile import ZipFile
from unittest import skipUnless
=20
-class AST1030Machine(LinuxKernelTest):
-
- ASSET_ZEPHYR_1_04 =3D Asset(
- ('https://github.com/AspeedTech-BMC'
- '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
- '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
-
- def test_ast1030_zephyros_1_04(self):
- self.set_machine('ast1030-evb')
-
- zip_file =3D self.ASSET_ZEPHYR_1_04.fetch()
-
- kernel_name =3D "ast1030-evb-demo/zephyr.elf"
- with ZipFile(zip_file, 'r') as zf:
- zf.extract(kernel_name, path=3Dself.workdir)
- kernel_file =3D os.path.join(self.workdir, kernel_name)
-
- self.vm.set_console()
- self.vm.add_args('-kernel', kernel_file, '-nographic')
- self.vm.launch()
- self.wait_for_console_pattern("Booting Zephyr OS")
- exec_command_and_wait_for_pattern(self, "help",
- "Available commands")
-
- ASSET_ZEPHYR_1_07 =3D Asset(
- ('https://github.com/AspeedTech-BMC'
- '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
- 'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
-
- def test_ast1030_zephyros_1_07(self):
- self.set_machine('ast1030-evb')
-
- zip_file =3D self.ASSET_ZEPHYR_1_07.fetch()
-
- kernel_name =3D "ast1030-evb-demo/zephyr.bin"
- with ZipFile(zip_file, 'r') as zf:
- zf.extract(kernel_name, path=3Dself.workdir)
- kernel_file =3D os.path.join(self.workdir, kernel_name)
-
- self.vm.set_console()
- self.vm.add_args('-kernel', kernel_file, '-nographic')
- self.vm.launch()
- self.wait_for_console_pattern("Booting Zephyr OS")
- for shell_cmd in [
- 'kernel stacks',
- 'otp info conf',
- 'otp info scu',
- 'hwinfo devid',
- 'crypto aes256_cbc_vault',
- 'random get',
- 'jtag JTAG1 sw_xfer high TMS',
- 'adc ADC0 resolution 12',
- 'adc ADC0 read 42',
- 'adc ADC1 read 69',
- 'i2c scan I2C_0',
- 'i3c attach I3C_0',
- 'hash test',
- 'kernel uptime',
- 'kernel reboot warm',
- 'kernel uptime',
- 'kernel reboot cold',
- 'kernel uptime',
- ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
-
class AST2x00Machine(LinuxKernelTest):
=20
def do_test_arm_aspeed(self, machine, image):
diff --git a/tests/functional/test_arm_aspeed_ast1030.py b/tests/functional=
/test_arm_aspeed_ast1030.py
new file mode 100644
index 000000000000..380a76ec015c
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast1030.py
@@ -0,0 +1,81 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2022 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+
+from qemu_test import LinuxKernelTest, Asset
+from qemu_test import exec_command_and_wait_for_pattern
+from zipfile import ZipFile
+
+class AST1030Machine(LinuxKernelTest):
+
+ ASSET_ZEPHYR_1_04 =3D Asset(
+ ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
+ '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
+
+ def test_ast1030_zephyros_1_04(self):
+ self.set_machine('ast1030-evb')
+
+ zip_file =3D self.ASSET_ZEPHYR_1_04.fetch()
+
+ kernel_name =3D "ast1030-evb-demo/zephyr.elf"
+ with ZipFile(zip_file, 'r') as zf:
+ zf.extract(kernel_name, path=3Dself.workdir)
+ kernel_file =3D os.path.join(self.workdir, kernel_name)
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file, '-nographic')
+ self.vm.launch()
+ self.wait_for_console_pattern("Booting Zephyr OS")
+ exec_command_and_wait_for_pattern(self, "help",
+ "Available commands")
+
+ ASSET_ZEPHYR_1_07 =3D Asset(
+ ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
+ 'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
+
+ def test_ast1030_zephyros_1_07(self):
+ self.set_machine('ast1030-evb')
+
+ zip_file =3D self.ASSET_ZEPHYR_1_07.fetch()
+
+ kernel_name =3D "ast1030-evb-demo/zephyr.bin"
+ with ZipFile(zip_file, 'r') as zf:
+ zf.extract(kernel_name, path=3Dself.workdir)
+ kernel_file =3D os.path.join(self.workdir, kernel_name)
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file, '-nographic')
+ self.vm.launch()
+ self.wait_for_console_pattern("Booting Zephyr OS")
+ for shell_cmd in [
+ 'kernel stacks',
+ 'otp info conf',
+ 'otp info scu',
+ 'hwinfo devid',
+ 'crypto aes256_cbc_vault',
+ 'random get',
+ 'jtag JTAG1 sw_xfer high TMS',
+ 'adc ADC0 resolution 12',
+ 'adc ADC0 read 42',
+ 'adc ADC1 read 69',
+ 'i2c scan I2C_0',
+ 'i3c attach I3C_0',
+ 'hash test',
+ 'kernel uptime',
+ 'kernel reboot warm',
+ 'kernel uptime',
+ 'kernel reboot cold',
+ 'kernel uptime',
+ ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
+
+
+if __name__ =3D=3D '__main__':
+ LinuxKernelTest.main()
--=20
2.47.1
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Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>,
Thomas Huth <thuth@redhat.com>
Subject: [PULL 09/24] tests/functional: Introduce a specific test for
palmetto-bmc machine
Date: Wed, 11 Dec 2024 07:30:43 +0100
Message-ID: <20241211063058.1222038-10-clg@redhat.com>
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This introduces a new aspeed module for sharing code between tests and
moves the palmetto test to a new test file. No changes in the test.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-3-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/aspeed.py | 23 +++++++++++++++++++
tests/functional/meson.build | 2 ++
tests/functional/test_arm_aspeed.py | 10 --------
tests/functional/test_arm_aspeed_palmetto.py | 24 ++++++++++++++++++++
4 files changed, 49 insertions(+), 10 deletions(-)
create mode 100644 tests/functional/aspeed.py
create mode 100644 tests/functional/test_arm_aspeed_palmetto.py
diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
new file mode 100644
index 000000000000..d4dc5320b97a
--- /dev/null
+++ b/tests/functional/aspeed.py
@@ -0,0 +1,23 @@
+# Test class to boot aspeed machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import LinuxKernelTest
+
+class AspeedTest(LinuxKernelTest):
+
+ def do_test_arm_aspeed(self, machine, image):
+ self.set_machine(machine)
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw',
+ '-net', 'nic', '-snapshot')
+ self.vm.launch()
+
+ self.wait_for_console_pattern("U-Boot 2016.07")
+ self.wait_for_console_pattern("## Loading kernel from FIT Image at=
20080000")
+ self.wait_for_console_pattern("Starting kernel ...")
+ self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
+ self.wait_for_console_pattern(
+ "aspeed-smc 1e620000.spi: read control register: 203b0641")
+ self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: i=
rq ")
+ self.wait_for_console_pattern("systemd[1]: Set hostname to")
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 66f10da99d63..4752dca9d66c 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -18,6 +18,7 @@ test_timeouts =3D {
'aarch64_tuxrun' : 240,
'aarch64_virt' : 720,
'acpi_bits' : 420,
+ 'arm_aspeed_palmetto' : 120,
'arm_aspeed' : 600,
'arm_bpim2u' : 500,
'arm_collie' : 180,
@@ -67,6 +68,7 @@ tests_alpha_system_thorough =3D [
tests_arm_system_thorough =3D [
'arm_aspeed',
'arm_aspeed_ast1030',
+ 'arm_aspeed_palmetto',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed.py
index 9e58fcd84009..48a229608ef6 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -37,16 +37,6 @@ def do_test_arm_aspeed(self, machine, image):
self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: i=
rq ")
self.wait_for_console_pattern("systemd[1]: Set hostname to")
=20
- ASSET_PALMETTO_FLASH =3D Asset(
- ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
- 'obmc-phosphor-image-palmetto.static.mtd'),
- '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d'=
);
-
- def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
- image_path =3D self.ASSET_PALMETTO_FLASH.fetch()
-
- self.do_test_arm_aspeed('palmetto-bmc', image_path)
-
ASSET_ROMULUS_FLASH =3D Asset(
('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
'obmc-phosphor-image-romulus.static.mtd'),
diff --git a/tests/functional/test_arm_aspeed_palmetto.py b/tests/functiona=
l/test_arm_aspeed_palmetto.py
new file mode 100644
index 000000000000..6588c02aad79
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_palmetto.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+
+class PalmettoMachine(AspeedTest):
+
+ ASSET_PALMETTO_FLASH =3D Asset(
+ ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
+ 'obmc-phosphor-image-palmetto.static.mtd'),
+ '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d'=
);
+
+ def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
+ image_path =3D self.ASSET_PALMETTO_FLASH.fetch()
+
+ self.do_test_arm_aspeed('palmetto-bmc', image_path)
+
+
+if __name__ =3D=3D '__main__':
+ AspeedTest.main()
--=20
2.47.1
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Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>,
Thomas Huth <thuth@redhat.com>
Subject: [PULL 10/24] tests/functional: Introduce a specific test for
romulus-bmc machine
Date: Wed, 11 Dec 2024 07:30:44 +0100
Message-ID: <20241211063058.1222038-11-clg@redhat.com>
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This simply moves the romulus-bmc test to a new test file. No changes
in the test. The do_test_arm_aspeed routine is removed from the
test_arm_aspeed.py file because it is now unused.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-4-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/meson.build | 2 ++
tests/functional/test_arm_aspeed.py | 26 ---------------------
tests/functional/test_arm_aspeed_romulus.py | 24 +++++++++++++++++++
3 files changed, 26 insertions(+), 26 deletions(-)
create mode 100644 tests/functional/test_arm_aspeed_romulus.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 4752dca9d66c..e9ec5af0f1e4 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -19,6 +19,7 @@ test_timeouts =3D {
'aarch64_virt' : 720,
'acpi_bits' : 420,
'arm_aspeed_palmetto' : 120,
+ 'arm_aspeed_romulus' : 120,
'arm_aspeed' : 600,
'arm_bpim2u' : 500,
'arm_collie' : 180,
@@ -69,6 +70,7 @@ tests_arm_system_thorough =3D [
'arm_aspeed',
'arm_aspeed_ast1030',
'arm_aspeed_palmetto',
+ 'arm_aspeed_romulus',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed.py
index 48a229608ef6..bdc000a00a32 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -21,32 +21,6 @@
=20
class AST2x00Machine(LinuxKernelTest):
=20
- def do_test_arm_aspeed(self, machine, image):
- self.set_machine(machine)
- self.vm.set_console()
- self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw',
- '-net', 'nic', '-snapshot')
- self.vm.launch()
-
- self.wait_for_console_pattern("U-Boot 2016.07")
- self.wait_for_console_pattern("## Loading kernel from FIT Image at=
20080000")
- self.wait_for_console_pattern("Starting kernel ...")
- self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
- self.wait_for_console_pattern(
- "aspeed-smc 1e620000.spi: read control register: 203b0641")
- self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: i=
rq ")
- self.wait_for_console_pattern("systemd[1]: Set hostname to")
-
- ASSET_ROMULUS_FLASH =3D Asset(
- ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
- 'obmc-phosphor-image-romulus.static.mtd'),
- '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
-
- def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
- image_path =3D self.ASSET_ROMULUS_FLASH.fetch()
-
- self.do_test_arm_aspeed('romulus-bmc', image_path)
-
def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern=3D=
'Aspeed EVB'):
self.require_netdev('user')
self.vm.set_console()
diff --git a/tests/functional/test_arm_aspeed_romulus.py b/tests/functional=
/test_arm_aspeed_romulus.py
new file mode 100644
index 000000000000..747b616201ce
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_romulus.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+
+class RomulusMachine(AspeedTest):
+
+ ASSET_ROMULUS_FLASH =3D Asset(
+ ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
+ 'obmc-phosphor-image-romulus.static.mtd'),
+ '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
+
+ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
+ image_path =3D self.ASSET_ROMULUS_FLASH.fetch()
+
+ self.do_test_arm_aspeed('romulus-bmc', image_path)
+
+
+if __name__ =3D=3D '__main__':
+ AspeedTest.main()
--=20
2.47.1
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Subject: [PULL 11/24] tests/functional: Introduce a specific test for ast2500
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This moves the ast2500-evb tests to a new test file and extends the
aspeed module with routines used to run the buildroot and sdk
tests. No changes in the test.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-5-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/aspeed.py | 33 ++++++++++++
tests/functional/meson.build | 2 +
tests/functional/test_arm_aspeed.py | 44 ---------------
tests/functional/test_arm_aspeed_ast2500.py | 59 +++++++++++++++++++++
4 files changed, 94 insertions(+), 44 deletions(-)
create mode 100644 tests/functional/test_arm_aspeed_ast2500.py
diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
index d4dc5320b97a..62f50bab7a33 100644
--- a/tests/functional/aspeed.py
+++ b/tests/functional/aspeed.py
@@ -2,6 +2,7 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
=20
+from qemu_test import exec_command_and_wait_for_pattern
from qemu_test import LinuxKernelTest
=20
class AspeedTest(LinuxKernelTest):
@@ -21,3 +22,35 @@ def do_test_arm_aspeed(self, machine, image):
"aspeed-smc 1e620000.spi: read control register: 203b0641")
self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: i=
rq ")
self.wait_for_console_pattern("systemd[1]: Set hostname to")
+
+ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern=3D=
'Aspeed EVB'):
+ self.require_netdev('user')
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw,read-only=3Dtrue',
+ '-net', 'nic', '-net', 'user')
+ self.vm.launch()
+
+ self.wait_for_console_pattern('U-Boot 2019.04')
+ self.wait_for_console_pattern('## Loading kernel from FIT Image')
+ self.wait_for_console_pattern('Starting kernel ...')
+ self.wait_for_console_pattern('Booting Linux on physical CPU ' + c=
pu_id)
+ self.wait_for_console_pattern('lease of 10.0.2.15')
+ # the line before login:
+ self.wait_for_console_pattern(pattern)
+ exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+ exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
+
+ def do_test_arm_aspeed_buildroot_poweroff(self):
+ exec_command_and_wait_for_pattern(self, 'poweroff',
+ 'reboot: System halted');
+
+ def do_test_arm_aspeed_sdk_start(self, image):
+ self.require_netdev('user')
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw',
+ '-net', 'nic', '-net', 'user', '-snapshot')
+ self.vm.launch()
+
+ self.wait_for_console_pattern('U-Boot 2019.04')
+ self.wait_for_console_pattern('## Loading kernel from FIT Image')
+ self.wait_for_console_pattern('Starting kernel ...')
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index e9ec5af0f1e4..cb97d2e3a003 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -20,6 +20,7 @@ test_timeouts =3D {
'acpi_bits' : 420,
'arm_aspeed_palmetto' : 120,
'arm_aspeed_romulus' : 120,
+ 'arm_aspeed_ast2500' : 480,
'arm_aspeed' : 600,
'arm_bpim2u' : 500,
'arm_collie' : 180,
@@ -71,6 +72,7 @@ tests_arm_system_thorough =3D [
'arm_aspeed_ast1030',
'arm_aspeed_palmetto',
'arm_aspeed_romulus',
+ 'arm_aspeed_ast2500',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed.py
index bdc000a00a32..48cf0bfb27ca 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -41,34 +41,6 @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_=
id, pattern=3D'Aspeed EVB'
def do_test_arm_aspeed_buildroot_poweroff(self):
exec_command_and_wait_for_pattern(self, 'poweroff',
'reboot: System halted');
-
- ASSET_BR2_202311_AST2500_FLASH =3D Asset(
- ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
- 'images/ast2500-evb/buildroot-2023.11/flash.img'),
- 'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
-
- def test_arm_ast2500_evb_buildroot(self):
- self.set_machine('ast2500-evb')
-
- image_path =3D self.ASSET_BR2_202311_AST2500_FLASH.fetch()
-
- self.vm.add_args('-device',
- 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id=
=3Dtmp-test');
- self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
- 'ast2500-evb login:')
-
- exec_command_and_wait_for_pattern(self,
- 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
- 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon1/temp1_input', '0=
')
- self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
- property=3D'temperature', value=3D18000);
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon1/temp1_input', '1=
8000')
-
- self.do_test_arm_aspeed_buildroot_poweroff()
-
ASSET_BR2_202311_AST2600_FLASH =3D Asset(
('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
'images/ast2600-evb/buildroot-2023.11/flash.img'),
@@ -161,22 +133,6 @@ def do_test_arm_aspeed_sdk_start(self, image):
self.wait_for_console_pattern('## Loading kernel from FIT Image')
self.wait_for_console_pattern('Starting kernel ...')
=20
- ASSET_SDK_V806_AST2500 =3D Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.0=
6/ast2500-default-obmc.tar.gz',
- 'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
-
- def test_arm_ast2500_evb_sdk(self):
- self.set_machine('ast2500-evb')
-
- image_path =3D self.ASSET_SDK_V806_AST2500.fetch()
-
- archive_extract(image_path, self.workdir)
-
- self.do_test_arm_aspeed_sdk_start(
- self.workdir + '/ast2500-default/image-bmc')
-
- self.wait_for_console_pattern('ast2500-default login:')
-
ASSET_SDK_V806_AST2600_A2 =3D Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.0=
6/ast2600-a2-obmc.tar.gz',
'9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
diff --git a/tests/functional/test_arm_aspeed_ast2500.py b/tests/functional=
/test_arm_aspeed_ast2500.py
new file mode 100644
index 000000000000..79baf37537e5
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast2500.py
@@ -0,0 +1,59 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+from qemu_test import exec_command_and_wait_for_pattern
+from qemu_test.utils import archive_extract
+
+class AST2500Machine(AspeedTest):
+
+ ASSET_BR2_202311_AST2500_FLASH =3D Asset(
+ ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+ 'images/ast2500-evb/buildroot-2023.11/flash.img'),
+ 'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
+
+ def test_arm_ast2500_evb_buildroot(self):
+ self.set_machine('ast2500-evb')
+
+ image_path =3D self.ASSET_BR2_202311_AST2500_FLASH.fetch()
+
+ self.vm.add_args('-device',
+ 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id=
=3Dtmp-test');
+ self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
+ 'ast2500-evb login:')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
+ 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon1/temp1_input', '0=
')
+ self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
+ property=3D'temperature', value=3D18000);
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon1/temp1_input', '1=
8000')
+
+ self.do_test_arm_aspeed_buildroot_poweroff()
+
+ ASSET_SDK_V806_AST2500 =3D Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.0=
6/ast2500-default-obmc.tar.gz',
+ 'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
+
+ def test_arm_ast2500_evb_sdk(self):
+ self.set_machine('ast2500-evb')
+
+ image_path =3D self.ASSET_SDK_V806_AST2500.fetch()
+
+ archive_extract(image_path, self.workdir)
+
+ self.do_test_arm_aspeed_sdk_start(
+ self.workdir + '/ast2500-default/image-bmc')
+
+ self.wait_for_console_pattern('ast2500-default login:')
+
+
+if __name__ =3D=3D '__main__':
+ AspeedTest.main()
--=20
2.47.1
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Subject: [PULL 12/24] tests/functional: Introduce a specific test for ast2600
SoC
Date: Wed, 11 Dec 2024 07:30:46 +0100
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This moves the ast2600-evb tests to a new test file. No changes in the
test. The routines used to run the buildroot and sdk tests are removed
from the test_arm_aspeed.py file because now unused.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-6-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/meson.build | 2 +
tests/functional/test_arm_aspeed.py | 155 --------------------
tests/functional/test_arm_aspeed_ast2600.py | 143 ++++++++++++++++++
3 files changed, 145 insertions(+), 155 deletions(-)
create mode 100644 tests/functional/test_arm_aspeed_ast2600.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index cb97d2e3a003..b5fd3bededde 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -21,6 +21,7 @@ test_timeouts =3D {
'arm_aspeed_palmetto' : 120,
'arm_aspeed_romulus' : 120,
'arm_aspeed_ast2500' : 480,
+ 'arm_aspeed_ast2600' : 720,
'arm_aspeed' : 600,
'arm_bpim2u' : 500,
'arm_collie' : 180,
@@ -73,6 +74,7 @@ tests_arm_system_thorough =3D [
'arm_aspeed_palmetto',
'arm_aspeed_romulus',
'arm_aspeed_ast2500',
+ 'arm_aspeed_ast2600',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed.py
index 48cf0bfb27ca..8cf86795af3c 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -19,161 +19,6 @@
from zipfile import ZipFile
from unittest import skipUnless
=20
-class AST2x00Machine(LinuxKernelTest):
-
- def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern=3D=
'Aspeed EVB'):
- self.require_netdev('user')
- self.vm.set_console()
- self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw,read-only=3Dtrue',
- '-net', 'nic', '-net', 'user')
- self.vm.launch()
-
- self.wait_for_console_pattern('U-Boot 2019.04')
- self.wait_for_console_pattern('## Loading kernel from FIT Image')
- self.wait_for_console_pattern('Starting kernel ...')
- self.wait_for_console_pattern('Booting Linux on physical CPU ' + c=
pu_id)
- self.wait_for_console_pattern('lease of 10.0.2.15')
- # the line before login:
- self.wait_for_console_pattern(pattern)
- exec_command_and_wait_for_pattern(self, 'root', 'Password:')
- exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
-
- def do_test_arm_aspeed_buildroot_poweroff(self):
- exec_command_and_wait_for_pattern(self, 'poweroff',
- 'reboot: System halted');
- ASSET_BR2_202311_AST2600_FLASH =3D Asset(
- ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
- 'images/ast2600-evb/buildroot-2023.11/flash.img'),
- 'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
-
- def test_arm_ast2600_evb_buildroot(self):
- self.set_machine('ast2600-evb')
-
- image_path =3D self.ASSET_BR2_202311_AST2600_FLASH.fetch()
-
- self.vm.add_args('-device',
- 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id=
=3Dtmp-test');
- self.vm.add_args('-device',
- 'ds1338,bus=3Daspeed.i2c.bus.3,address=3D0x32');
- self.vm.add_args('-device',
- 'i2c-echo,bus=3Daspeed.i2c.bus.3,address=3D0x42');
- self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
- 'ast2600-evb login:')
-
- exec_command_and_wait_for_pattern(self,
- 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
- 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon1/temp1_input', '0=
')
- self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
- property=3D'temperature', value=3D18000);
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon1/temp1_input', '1=
8000')
-
- exec_command_and_wait_for_pattern(self,
- 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_devic=
e',
- 'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
- year =3D time.strftime("%Y")
- exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', ye=
ar);
-
- exec_command_and_wait_for_pattern(self,
- 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_dev=
ice',
- 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x=
64');
- exec_command_and_wait_for_pattern(self,
- 'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
- exec_command_and_wait_for_pattern(self,
- 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
- '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
- self.do_test_arm_aspeed_buildroot_poweroff()
-
- ASSET_BR2_202302_AST2600_TPM_FLASH =3D Asset(
- ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
- 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
- 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
-
- @skipUnless(*has_cmd('swtpm'))
- def test_arm_ast2600_evb_buildroot_tpm(self):
- self.set_machine('ast2600-evb')
-
- image_path =3D self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
-
- tpmstate_dir =3D tempfile.TemporaryDirectory(prefix=3D"qemu_")
- socket =3D os.path.join(tpmstate_dir.name, 'swtpm-socket')
-
- # We must put the TPM state dir in /tmp/, not the build dir,
- # because some distros use AppArmor to lock down swtpm and
- # restrict the set of locations it can access files in.
- subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
- '--tpmstate', f'dir=3D{tpmstate_dir.name}',
- '--ctrl', f'type=3Dunixio,path=3D{socket}'])
-
- self.vm.add_args('-chardev', f'socket,id=3Dchrtpm,path=3D{socket}')
- self.vm.add_args('-tpmdev', 'emulator,id=3Dtpm0,chardev=3Dchrtpm')
- self.vm.add_args('-device',
- 'tpm-tis-i2c,tpmdev=3Dtpm0,bus=3Daspeed.i2c.bus.1=
2,address=3D0x2e')
- self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspe=
ed AST2600 EVB')
-
- exec_command_and_wait_for_pattern(self,
- 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_devic=
e',
- 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/tpm/tpm0/pcr-sha256/0',
- 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C43168=
8E0');
-
- self.do_test_arm_aspeed_buildroot_poweroff()
-
- def do_test_arm_aspeed_sdk_start(self, image):
- self.require_netdev('user')
- self.vm.set_console()
- self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format=
=3Draw',
- '-net', 'nic', '-net', 'user', '-snapshot')
- self.vm.launch()
-
- self.wait_for_console_pattern('U-Boot 2019.04')
- self.wait_for_console_pattern('## Loading kernel from FIT Image')
- self.wait_for_console_pattern('Starting kernel ...')
-
- ASSET_SDK_V806_AST2600_A2 =3D Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.0=
6/ast2600-a2-obmc.tar.gz',
- '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
-
- def test_arm_ast2600_evb_sdk(self):
- self.set_machine('ast2600-evb')
-
- image_path =3D self.ASSET_SDK_V806_AST2600_A2.fetch()
-
- archive_extract(image_path, self.workdir)
-
- self.vm.add_args('-device',
- 'tmp105,bus=3Daspeed.i2c.bus.5,address=3D0x4d,id=3Dtmp-test');
- self.vm.add_args('-device',
- 'ds1338,bus=3Daspeed.i2c.bus.5,address=3D0x32');
- self.do_test_arm_aspeed_sdk_start(
- self.workdir + '/ast2600-a2/image-bmc')
-
- self.wait_for_console_pattern('ast2600-a2 login:')
-
- exec_command_and_wait_for_pattern(self, 'root', 'Password:')
- exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a=
2:~#')
-
- exec_command_and_wait_for_pattern(self,
- 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
- 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
- self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
- property=3D'temperature', value=3D18000);
- exec_command_and_wait_for_pattern(self,
- 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
-
- exec_command_and_wait_for_pattern(self,
- 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_devic=
e',
- 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
- year =3D time.strftime("%Y")
- exec_command_and_wait_for_pattern(self,
- '/sbin/hwclock -f /dev/rtc1', year);
-
-
class AST2x00MachineMMC(LinuxKernelTest):
=20
ASSET_RAINIER_EMMC =3D Asset(
diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional=
/test_arm_aspeed_ast2600.py
new file mode 100644
index 000000000000..74d025e0fc76
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast2600.py
@@ -0,0 +1,143 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import time
+import tempfile
+import subprocess
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+from qemu_test import exec_command_and_wait_for_pattern
+from qemu_test import has_cmd
+from qemu_test.utils import archive_extract
+from unittest import skipUnless
+
+class AST2600Machine(AspeedTest):
+
+ ASSET_BR2_202311_AST2600_FLASH =3D Asset(
+ ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+ 'images/ast2600-evb/buildroot-2023.11/flash.img'),
+ 'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
+
+ def test_arm_ast2600_evb_buildroot(self):
+ self.set_machine('ast2600-evb')
+
+ image_path =3D self.ASSET_BR2_202311_AST2600_FLASH.fetch()
+
+ self.vm.add_args('-device',
+ 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id=
=3Dtmp-test');
+ self.vm.add_args('-device',
+ 'ds1338,bus=3Daspeed.i2c.bus.3,address=3D0x32');
+ self.vm.add_args('-device',
+ 'i2c-echo,bus=3Daspeed.i2c.bus.3,address=3D0x42');
+ self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
+ 'ast2600-evb login:')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
+ 'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon1/temp1_input', '0=
')
+ self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
+ property=3D'temperature', value=3D18000);
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon1/temp1_input', '1=
8000')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_devic=
e',
+ 'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
+ year =3D time.strftime("%Y")
+ exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', ye=
ar);
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_dev=
ice',
+ 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x=
64');
+ exec_command_and_wait_for_pattern(self,
+ 'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
+ exec_command_and_wait_for_pattern(self,
+ 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
+ '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
+ self.do_test_arm_aspeed_buildroot_poweroff()
+
+ ASSET_BR2_202302_AST2600_TPM_FLASH =3D Asset(
+ ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+ 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
+ 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
+
+ @skipUnless(*has_cmd('swtpm'))
+ def test_arm_ast2600_evb_buildroot_tpm(self):
+ self.set_machine('ast2600-evb')
+
+ image_path =3D self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
+
+ tpmstate_dir =3D tempfile.TemporaryDirectory(prefix=3D"qemu_")
+ socket =3D os.path.join(tpmstate_dir.name, 'swtpm-socket')
+
+ # We must put the TPM state dir in /tmp/, not the build dir,
+ # because some distros use AppArmor to lock down swtpm and
+ # restrict the set of locations it can access files in.
+ subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
+ '--tpmstate', f'dir=3D{tpmstate_dir.name}',
+ '--ctrl', f'type=3Dunixio,path=3D{socket}'])
+
+ self.vm.add_args('-chardev', f'socket,id=3Dchrtpm,path=3D{socket}')
+ self.vm.add_args('-tpmdev', 'emulator,id=3Dtpm0,chardev=3Dchrtpm')
+ self.vm.add_args('-device',
+ 'tpm-tis-i2c,tpmdev=3Dtpm0,bus=3Daspeed.i2c.bus.1=
2,address=3D0x2e')
+ self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspe=
ed AST2600 EVB')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_devic=
e',
+ 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/tpm/tpm0/pcr-sha256/0',
+ 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C43168=
8E0');
+
+ self.do_test_arm_aspeed_buildroot_poweroff()
+
+ ASSET_SDK_V806_AST2600_A2 =3D Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.0=
6/ast2600-a2-obmc.tar.gz',
+ '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
+
+ def test_arm_ast2600_evb_sdk(self):
+ self.set_machine('ast2600-evb')
+
+ image_path =3D self.ASSET_SDK_V806_AST2600_A2.fetch()
+
+ archive_extract(image_path, self.workdir)
+
+ self.vm.add_args('-device',
+ 'tmp105,bus=3Daspeed.i2c.bus.5,address=3D0x4d,id=3Dtmp-test');
+ self.vm.add_args('-device',
+ 'ds1338,bus=3Daspeed.i2c.bus.5,address=3D0x32');
+ self.do_test_arm_aspeed_sdk_start(
+ self.workdir + '/ast2600-a2/image-bmc')
+
+ self.wait_for_console_pattern('ast2600-a2 login:')
+
+ exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+ exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a=
2:~#')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
+ 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
+ self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test',
+ property=3D'temperature', value=3D18000);
+ exec_command_and_wait_for_pattern(self,
+ 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
+
+ exec_command_and_wait_for_pattern(self,
+ 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_devic=
e',
+ 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
+ year =3D time.strftime("%Y")
+ exec_command_and_wait_for_pattern(self,
+ '/sbin/hwclock -f /dev/rtc1', year);
+
+if __name__ =3D=3D '__main__':
+ AspeedTest.main()
--=20
2.47.1
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Subject: [PULL 13/24] tests/functional: Introduce a specific test for
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This simply moves the rainier-bmc test to a new test file. No changes
in the test. The test_arm_aspeed.py is deleted.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-7-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/functional/meson.build | 4 ++--
...m_aspeed.py =3D> test_arm_aspeed_rainier.py} | 22 +++++--------------
2 files changed, 7 insertions(+), 19 deletions(-)
rename tests/functional/{test_arm_aspeed.py =3D> test_arm_aspeed_rainier.p=
y} (71%)
mode change 100755 =3D> 100644
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index b5fd3bededde..96f2291a39bd 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -22,7 +22,7 @@ test_timeouts =3D {
'arm_aspeed_romulus' : 120,
'arm_aspeed_ast2500' : 480,
'arm_aspeed_ast2600' : 720,
- 'arm_aspeed' : 600,
+ 'arm_aspeed_rainier' : 240,
'arm_bpim2u' : 500,
'arm_collie' : 180,
'arm_orangepi' : 540,
@@ -69,12 +69,12 @@ tests_alpha_system_thorough =3D [
]
=20
tests_arm_system_thorough =3D [
- 'arm_aspeed',
'arm_aspeed_ast1030',
'arm_aspeed_palmetto',
'arm_aspeed_romulus',
'arm_aspeed_ast2500',
'arm_aspeed_ast2600',
+ 'arm_aspeed_rainier',
'arm_bpim2u',
'arm_canona1100',
'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_ar=
m_aspeed_rainier.py
old mode 100755
new mode 100644
similarity index 71%
rename from tests/functional/test_arm_aspeed.py
rename to tests/functional/test_arm_aspeed_rainier.py
index 8cf86795af3c..a60274926d6f
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed_rainier.py
@@ -1,25 +1,13 @@
#!/usr/bin/env python3
#
-# Functional test that boots the ASPEED SoCs with firmware
-#
-# Copyright (C) 2022 ASPEED Technology Inc
+# Functional test that boots the ASPEED machines
#
# SPDX-License-Identifier: GPL-2.0-or-later
=20
-import os
-import time
-import subprocess
-import tempfile
-
-from qemu_test import LinuxKernelTest, Asset
-from qemu_test import exec_command_and_wait_for_pattern
-from qemu_test import interrupt_interactive_console_until_pattern
-from qemu_test import has_cmd
-from qemu_test.utils import archive_extract
-from zipfile import ZipFile
-from unittest import skipUnless
+from qemu_test import Asset
+from aspeed import AspeedTest
=20
-class AST2x00MachineMMC(LinuxKernelTest):
+class RainierMachine(AspeedTest):
=20
ASSET_RAINIER_EMMC =3D Asset(
('https://fileserver.linaro.org/s/B6pJTwWEkzSDi36/download/'
@@ -49,4 +37,4 @@ def test_arm_aspeed_emmc_boot(self):
self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterpris=
e')
=20
if __name__ =3D=3D '__main__':
- LinuxKernelTest.main()
+ AspeedTest.main()
--=20
2.47.1
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Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>,
Thomas Huth <thuth@redhat.com>
Subject: [PULL 14/24] tests/functional: Move debian boot test from avocado
Date: Wed, 11 Dec 2024 07:30:48 +0100
Message-ID: <20241211063058.1222038-15-clg@redhat.com>
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This simply moves the debian boot test from the avocado testsuite to
the new functional testsuite. No changes in the test.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-8-clg@redhat.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/avocado/boot_linux_console.py | 26 ---------------------
tests/functional/test_arm_aspeed_rainier.py | 24 +++++++++++++++++++
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux=
_console.py
index 12e24bb05a75..738dd5a8c4bf 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -470,29 +470,3 @@ def test_arm_quanta_gsj_initrd(self):
self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
self.wait_for_console_pattern(
'Give root password for system maintenance')
-
- def test_arm_ast2600_debian(self):
- """
- :avocado: tags=3Darch:arm
- :avocado: tags=3Dmachine:rainier-bmc
- """
- deb_url =3D ('http://snapshot.debian.org/archive/debian/'
- '20220606T211338Z/'
- 'pool/main/l/linux/'
- 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
- deb_hash =3D '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660=
c8abe4dcdc0e'
- deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash,
- algorithm=3D'sha256')
- kernel_path =3D self.extract_from_deb(deb_path, '/boot/vmlinuz-5.1=
7.0-2-armmp')
- dtb_path =3D self.extract_from_deb(deb_path,
- '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainie=
r.dtb')
-
- self.vm.set_console()
- self.vm.add_args('-kernel', kernel_path,
- '-dtb', dtb_path,
- '-net', 'nic')
- self.vm.launch()
- self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00=
")
- self.wait_for_console_pattern("SMP: Total of 2 processors activate=
d")
- self.wait_for_console_pattern("No filesystem could mount root")
-
diff --git a/tests/functional/test_arm_aspeed_rainier.py b/tests/functional=
/test_arm_aspeed_rainier.py
index a60274926d6f..b856aea6dbd7 100644
--- a/tests/functional/test_arm_aspeed_rainier.py
+++ b/tests/functional/test_arm_aspeed_rainier.py
@@ -36,5 +36,29 @@ def test_arm_aspeed_emmc_boot(self):
self.wait_for_console_pattern('mmcblk0: p1 p2 p3 p4 p5 p6 p7')
self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterpris=
e')
=20
+ ASSET_DEBIAN_LINUX_ARMHF_DEB =3D Asset(
+ ('http://snapshot.debian.org/archive/debian/20220606T211338Z/p=
ool/main/l/linux/linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb'),
+ '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e')
+
+ def test_arm_debian_kernel_boot(self):
+ self.set_machine('rainier-bmc')
+
+ deb_path =3D self.ASSET_DEBIAN_LINUX_ARMHF_DEB.fetch()
+
+ kernel_path =3D self.extract_from_deb(deb_path, '/boot/vmlinuz-5.1=
7.0-2-armmp')
+ dtb_path =3D self.extract_from_deb(deb_path,
+ '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainie=
r.dtb')
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-net', 'nic')
+ self.vm.launch()
+
+ self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00=
")
+ self.wait_for_console_pattern("SMP: Total of 2 processors activate=
d")
+ self.wait_for_console_pattern("No filesystem could mount root")
+
+
if __name__ =3D=3D '__main__':
AspeedTest.main()
--=20
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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 15/24] test/qtest/aspeed_smc-test: Move testcases to
test_palmetto_bmc function
Date: Wed, 11 Dec 2024 07:30:49 +0100
Message-ID: <20241211063058.1222038-16-clg@redhat.com>
In-Reply-To: <20241211063058.1222038-1-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
So far, the test cases are used for testing SMC model with AST2400 BMC.
However, AST2400 is end off live and ASPEED is no longer support this SOC.
To test SMC model for AST2500, AST2600 and AST1030, move the test cases
from main to test_palmetto_bmc function.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-2-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 4673371d9539..ec1fa6ec15ac 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -610,14 +610,12 @@ static void test_write_block_protect_bottom_bit(void)
flash_reset();
}
=20
-int main(int argc, char **argv)
+static int test_palmetto_bmc(void)
{
g_autofree char *tmp_path =3D NULL;
int ret;
int fd;
=20
- g_test_init(&argc, &argv, NULL);
-
fd =3D g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
g_assert(fd >=3D 0);
ret =3D ftruncate(fd, FLASH_SIZE);
@@ -644,8 +642,18 @@ int main(int argc, char **argv)
=20
flash_reset();
ret =3D g_test_run();
-
qtest_quit(global_qtest);
unlink(tmp_path);
+
+ return ret;
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ ret =3D test_palmetto_bmc();
+
return ret;
}
--=20
2.47.1
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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 16/24] test/qtest/aspeed_smc-test: Introduce a new TestData to
test different BMC SOCs
Date: Wed, 11 Dec 2024 07:30:50 +0100
Message-ID: <20241211063058.1222038-17-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Currently, these test cases are only used for testing fmc_cs0 for AST2400.
To test others BMC SOCs, introduces a new TestData structure.
Users can set the spi base address, flash base address, jedesc id and so on
for different BMC SOCs and flash model testing.
Introduce new helper functions to make the test case more readable.
Set spi base address 0x1E620000, flash_base address 0x20000000
and jedec id 0x20ba19 for fmc_cs0 with n25q256a flash for AST2400
SMC model testing.
To pass the TestData into the test case, replace qtest_add_func with
qtest_add_data_func.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-3-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 546 +++++++++++++++++++---------------
1 file changed, 299 insertions(+), 247 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index ec1fa6ec15ac..4c62009605d0 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -43,9 +43,6 @@
#define CTRL_USERMODE 0x3
#define SR_WEL BIT(1)
=20
-#define ASPEED_FMC_BASE 0x1E620000
-#define ASPEED_FLASH_BASE 0x20000000
-
/*
* Flash commands
*/
@@ -65,11 +62,16 @@ enum {
ERASE_SECTOR =3D 0xd8,
};
=20
-#define FLASH_JEDEC 0x20ba19 /* n25q256a */
-#define FLASH_SIZE (32 * 1024 * 1024)
-
#define FLASH_PAGE_SIZE 256
=20
+typedef struct TestData {
+ QTestState *s;
+ uint64_t spi_base;
+ uint64_t flash_base;
+ uint32_t jedec_id;
+ char *tmp_path;
+} TestData;
+
/*
* Use an explicit bswap for the values read/wrote to the flash region
* as they are BE and the Aspeed CPU is LE.
@@ -79,275 +81,315 @@ static inline uint32_t make_be32(uint32_t data)
return bswap32(data);
}
=20
-static void spi_conf(uint32_t value)
+static inline void spi_writel(const TestData *data, uint64_t offset,
+ uint32_t value)
+{
+ qtest_writel(data->s, data->spi_base + offset, value);
+}
+
+static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
+{
+ return qtest_readl(data->s, data->spi_base + offset);
+}
+
+static inline void flash_writeb(const TestData *data, uint64_t offset,
+ uint8_t value)
+{
+ qtest_writeb(data->s, data->flash_base + offset, value);
+}
+
+static inline void flash_writel(const TestData *data, uint64_t offset,
+ uint32_t value)
+{
+ qtest_writel(data->s, data->flash_base + offset, value);
+}
+
+static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
{
- uint32_t conf =3D readl(ASPEED_FMC_BASE + R_CONF);
+ return qtest_readb(data->s, data->flash_base + offset);
+}
+
+static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
+{
+ return qtest_readl(data->s, data->flash_base + offset);
+}
+
+static void spi_conf(const TestData *data, uint32_t value)
+{
+ uint32_t conf =3D spi_readl(data, R_CONF);
=20
conf |=3D value;
- writel(ASPEED_FMC_BASE + R_CONF, conf);
+ spi_writel(data, R_CONF, conf);
}
=20
-static void spi_conf_remove(uint32_t value)
+static void spi_conf_remove(const TestData *data, uint32_t value)
{
- uint32_t conf =3D readl(ASPEED_FMC_BASE + R_CONF);
+ uint32_t conf =3D spi_readl(data, R_CONF);
=20
conf &=3D ~value;
- writel(ASPEED_FMC_BASE + R_CONF, conf);
+ spi_writel(data, R_CONF, conf);
}
=20
-static void spi_ce_ctrl(uint32_t value)
+static void spi_ce_ctrl(const TestData *data, uint32_t value)
{
- uint32_t conf =3D readl(ASPEED_FMC_BASE + R_CE_CTRL);
+ uint32_t conf =3D spi_readl(data, R_CE_CTRL);
=20
conf |=3D value;
- writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
+ spi_writel(data, R_CE_CTRL, conf);
}
=20
-static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
+static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t c=
md)
{
- uint32_t ctrl =3D readl(ASPEED_FMC_BASE + R_CTRL0);
+ uint32_t ctrl =3D spi_readl(data, R_CTRL0);
ctrl &=3D ~(CTRL_USERMODE | 0xff << 16);
ctrl |=3D mode | (cmd << 16);
- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+ spi_writel(data, R_CTRL0, ctrl);
}
=20
-static void spi_ctrl_start_user(void)
+static void spi_ctrl_start_user(const TestData *data)
{
- uint32_t ctrl =3D readl(ASPEED_FMC_BASE + R_CTRL0);
+ uint32_t ctrl =3D spi_readl(data, R_CTRL0);
=20
ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+ spi_writel(data, R_CTRL0, ctrl);
=20
ctrl &=3D ~CTRL_CE_STOP_ACTIVE;
- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+ spi_writel(data, R_CTRL0, ctrl);
}
=20
-static void spi_ctrl_stop_user(void)
+static void spi_ctrl_stop_user(const TestData *data)
{
- uint32_t ctrl =3D readl(ASPEED_FMC_BASE + R_CTRL0);
+ uint32_t ctrl =3D spi_readl(data, R_CTRL0);
=20
ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+ spi_writel(data, R_CTRL0, ctrl);
}
=20
-static void flash_reset(void)
+static void flash_reset(const TestData *data)
{
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(data, CONF_ENABLE_W0);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
- writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, BULK_ERASE);
- writeb(ASPEED_FLASH_BASE, WRDI);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(data);
+ flash_writeb(data, 0, RESET_ENABLE);
+ flash_writeb(data, 0, RESET_MEMORY);
+ flash_writeb(data, 0, WREN);
+ flash_writeb(data, 0, BULK_ERASE);
+ flash_writeb(data, 0, WRDI);
+ spi_ctrl_stop_user(data);
=20
- spi_conf_remove(CONF_ENABLE_W0);
+ spi_conf_remove(data, CONF_ENABLE_W0);
}
=20
-static void test_read_jedec(void)
+static void test_read_jedec(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t jedec =3D 0x0;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, JEDEC_READ);
- jedec |=3D readb(ASPEED_FLASH_BASE) << 16;
- jedec |=3D readb(ASPEED_FLASH_BASE) << 8;
- jedec |=3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, JEDEC_READ);
+ jedec |=3D flash_readb(test_data, 0) << 16;
+ jedec |=3D flash_readb(test_data, 0) << 8;
+ jedec |=3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
=20
- flash_reset();
+ flash_reset(test_data);
=20
- g_assert_cmphex(jedec, =3D=3D, FLASH_JEDEC);
+ g_assert_cmphex(jedec, =3D=3D, test_data->jedec_id);
}
=20
-static void read_page(uint32_t addr, uint32_t *page)
+static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
{
int i;
=20
- spi_ctrl_start_user();
+ spi_ctrl_start_user(data);
=20
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, READ);
- writel(ASPEED_FLASH_BASE, make_be32(addr));
+ flash_writeb(data, 0, EN_4BYTE_ADDR);
+ flash_writeb(data, 0, READ);
+ flash_writel(data, 0, make_be32(addr));
=20
/* Continuous read are supported */
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- page[i] =3D make_be32(readl(ASPEED_FLASH_BASE));
+ page[i] =3D make_be32(flash_readl(data, 0));
}
- spi_ctrl_stop_user();
+ spi_ctrl_stop_user(data);
}
=20
-static void read_page_mem(uint32_t addr, uint32_t *page)
+static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *p=
age)
{
int i;
=20
/* move out USER mode to use direct reads from the AHB bus */
- spi_ctrl_setmode(CTRL_READMODE, READ);
+ spi_ctrl_setmode(data, CTRL_READMODE, READ);
=20
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- page[i] =3D make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
+ page[i] =3D make_be32(flash_readl(data, addr + i * 4));
}
}
=20
-static void write_page_mem(uint32_t addr, uint32_t write_value)
+static void write_page_mem(const TestData *data, uint32_t addr,
+ uint32_t write_value)
{
- spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+ spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
=20
for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
+ flash_writel(data, addr + i * 4, write_value);
}
}
=20
-static void assert_page_mem(uint32_t addr, uint32_t expected_value)
+static void assert_page_mem(const TestData *data, uint32_t addr,
+ uint32_t expected_value)
{
uint32_t page[FLASH_PAGE_SIZE / 4];
- read_page_mem(addr, page);
+ read_page_mem(data, addr, page);
for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, expected_value);
}
}
=20
-static void test_erase_sector(void)
+static void test_erase_sector(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t some_page_addr =3D 0x600 * FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
/*
* Previous page should be full of 0xffs after backend is
* initialized
*/
- read_page(some_page_addr - FLASH_PAGE_SIZE, page);
+ read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, PP);
- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
=20
/* Fill the page with its own addresses */
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
+ flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
}
- spi_ctrl_stop_user();
+ spi_ctrl_stop_user(test_data);
=20
/* Check the page is correctly written */
- read_page(some_page_addr, page);
+ read_page(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
}
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, ERASE_SECTOR);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
+ spi_ctrl_stop_user(test_data);
=20
/* Check the page is erased */
- read_page(some_page_addr, page);
+ read_page(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_erase_all(void)
+static void test_erase_all(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
/*
* Previous page should be full of 0xffs after backend is
* initialized
*/
- read_page(some_page_addr - FLASH_PAGE_SIZE, page);
+ read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, PP);
- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
=20
/* Fill the page with its own addresses */
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
+ flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
}
- spi_ctrl_stop_user();
+ spi_ctrl_stop_user(test_data);
=20
/* Check the page is correctly written */
- read_page(some_page_addr, page);
+ read_page(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
}
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, BULK_ERASE);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ spi_ctrl_stop_user(test_data);
=20
/* Check the page is erased */
- read_page(some_page_addr, page);
+ read_page(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_write_page(void)
+static void test_write_page(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t my_page_addr =3D 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, PP);
- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
=20
/* Fill the page with its own addresses */
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
}
- spi_ctrl_stop_user();
+ spi_ctrl_stop_user(test_data);
=20
/* Check what was written */
- read_page(my_page_addr, page);
+ read_page(test_data, my_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
}
=20
/* Check some other page. It should be full of 0xff */
- read_page(some_page_addr, page);
+ read_page(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_read_page_mem(void)
+static void test_read_page_mem(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t my_page_addr =3D 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
@@ -357,40 +399,41 @@ static void test_read_page_mem(void)
* Enable 4BYTE mode for controller. This is should be strapped by
* HW for CE0 anyhow.
*/
- spi_ce_ctrl(1 << CRTL_EXTENDED0);
+ spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
=20
/* Enable 4BYTE mode for flash. */
- spi_conf(CONF_ENABLE_W0);
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, PP);
- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
+ spi_conf(test_data, CONF_ENABLE_W0);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
=20
/* Fill the page with its own addresses */
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
}
- spi_ctrl_stop_user();
- spi_conf_remove(CONF_ENABLE_W0);
+ spi_ctrl_stop_user(test_data);
+ spi_conf_remove(test_data, CONF_ENABLE_W0);
=20
/* Check what was written */
- read_page_mem(my_page_addr, page);
+ read_page_mem(test_data, my_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
}
=20
/* Check some other page. It should be full of 0xff */
- read_page_mem(some_page_addr, page);
+ read_page_mem(test_data, some_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_write_page_mem(void)
+static void test_write_page_mem(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t my_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
@@ -399,150 +442,153 @@ static void test_write_page_mem(void)
* Enable 4BYTE mode for controller. This is should be strapped by
* HW for CE0 anyhow.
*/
- spi_ce_ctrl(1 << CRTL_EXTENDED0);
+ spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
=20
/* Enable 4BYTE mode for flash. */
- spi_conf(CONF_ENABLE_W0);
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- spi_ctrl_stop_user();
+ spi_conf(test_data, CONF_ENABLE_W0);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
=20
/* move out USER mode to use direct writes to the AHB bus */
- spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+ spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
=20
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
+ flash_writel(test_data, my_page_addr + i * 4,
make_be32(my_page_addr + i * 4));
}
=20
/* Check what was written */
- read_page_mem(my_page_addr, page);
+ read_page_mem(test_data, my_page_addr, page);
for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_read_status_reg(void)
+static void test_read_status_reg(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint8_t r;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
g_assert(!qtest_qom_get_bool
- (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL);
g_assert(qtest_qom_get_bool
- (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WRDI);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WRDI);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
g_assert(!qtest_qom_get_bool
- (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_status_reg_write_protection(void)
+static void test_status_reg_write_protection(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint8_t r;
=20
- spi_conf(CONF_ENABLE_W0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
/* default case: WP# is high and SRWD is low -> status register writab=
le */
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
/* test ability to write SRWD */
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, SRWD);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, SRWD);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
=20
/* WP# high and SRWD high -> status register writable */
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
/* test ability to write SRWD */
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, 0);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, 0);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
g_assert_cmphex(r & SRWD, =3D=3D, 0);
=20
/* WP# low and SRWD low -> status register writable */
- qtest_set_irq_in(global_qtest,
+ qtest_set_irq_in(test_data->s,
"/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
/* test ability to write SRWD */
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, SRWD);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, SRWD);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
=20
/* WP# low and SRWD high -> status register NOT writable */
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0 , WREN);
/* test ability to write SRWD */
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, 0);
- writeb(ASPEED_FLASH_BASE, RDSR);
- r =3D readb(ASPEED_FLASH_BASE);
- spi_ctrl_stop_user();
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, 0);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
/* write is not successful */
g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
=20
- qtest_set_irq_in(global_qtest,
+ qtest_set_irq_in(test_data->s,
"/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_write_block_protect(void)
+static void test_write_block_protect(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t sector_size =3D 65536;
uint32_t n_sectors =3D 512;
=20
- spi_ce_ctrl(1 << CRTL_EXTENDED0);
- spi_conf(CONF_ENABLE_W0);
+ spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
uint32_t bp_bits =3D 0b0;
=20
for (int i =3D 0; i < 16; i++) {
bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, BULK_ERASE);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, bp_bits);
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, bp_bits);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
=20
uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
uint32_t protection_start =3D n_sectors - num_protected_sectors;
@@ -551,27 +597,28 @@ static void test_write_block_protect(void)
for (int sector =3D 0; sector < n_sectors; sector++) {
uint32_t addr =3D sector * sector_size;
=20
- assert_page_mem(addr, 0xffffffff);
- write_page_mem(addr, make_be32(0xabcdef12));
+ assert_page_mem(test_data, addr, 0xffffffff);
+ write_page_mem(test_data, addr, make_be32(0xabcdef12));
=20
uint32_t expected_value =3D protection_start <=3D sector
&& sector < protection_end
? 0xffffffff : 0xabcdef12;
=20
- assert_page_mem(addr, expected_value);
+ assert_page_mem(test_data, addr, expected_value);
}
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static void test_write_block_protect_bottom_bit(void)
+static void test_write_block_protect_bottom_bit(const void *data)
{
+ const TestData *test_data =3D (const TestData *)data;
uint32_t sector_size =3D 65536;
uint32_t n_sectors =3D 512;
=20
- spi_ce_ctrl(1 << CRTL_EXTENDED0);
- spi_conf(CONF_ENABLE_W0);
+ spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+ spi_conf(test_data, CONF_ENABLE_W0);
=20
/* top bottom bit is enabled */
uint32_t bp_bits =3D 0b00100 << 3;
@@ -579,15 +626,15 @@ static void test_write_block_protect_bottom_bit(void)
for (int i =3D 0; i < 16; i++) {
bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
=20
- spi_ctrl_start_user();
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, BULK_ERASE);
- writeb(ASPEED_FLASH_BASE, WREN);
- writeb(ASPEED_FLASH_BASE, WRSR);
- writeb(ASPEED_FLASH_BASE, bp_bits);
- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
- writeb(ASPEED_FLASH_BASE, WREN);
- spi_ctrl_stop_user();
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, bp_bits);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
=20
uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
uint32_t protection_start =3D 0;
@@ -596,64 +643,69 @@ static void test_write_block_protect_bottom_bit(void)
for (int sector =3D 0; sector < n_sectors; sector++) {
uint32_t addr =3D sector * sector_size;
=20
- assert_page_mem(addr, 0xffffffff);
- write_page_mem(addr, make_be32(0xabcdef12));
+ assert_page_mem(test_data, addr, 0xffffffff);
+ write_page_mem(test_data, addr, make_be32(0xabcdef12));
=20
uint32_t expected_value =3D protection_start <=3D sector
&& sector < protection_end
? 0xffffffff : 0xabcdef12;
=20
- assert_page_mem(addr, expected_value);
+ assert_page_mem(test_data, addr, expected_value);
}
}
=20
- flash_reset();
+ flash_reset(test_data);
}
=20
-static int test_palmetto_bmc(void)
+static void test_palmetto_bmc(TestData *data)
{
- g_autofree char *tmp_path =3D NULL;
int ret;
int fd;
=20
- fd =3D g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
+ fd =3D g_file_open_tmp("qtest.m25p80.n25q256a.XXXXXX", &data->tmp_path=
, NULL);
g_assert(fd >=3D 0);
- ret =3D ftruncate(fd, FLASH_SIZE);
+ ret =3D ftruncate(fd, 32 * 1024 * 1024);
g_assert(ret =3D=3D 0);
close(fd);
=20
- global_qtest =3D qtest_initf("-m 256 -machine palmetto-bmc "
- "-drive file=3D%s,format=3Draw,if=3Dmtd",
- tmp_path);
-
- qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec);
- qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector);
- qtest_add_func("/ast2400/smc/erase_all", test_erase_all);
- qtest_add_func("/ast2400/smc/write_page", test_write_page);
- qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
- qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
- qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
- qtest_add_func("/ast2400/smc/status_reg_write_protection",
- test_status_reg_write_protection);
- qtest_add_func("/ast2400/smc/write_block_protect",
- test_write_block_protect);
- qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
- test_write_block_protect_bottom_bit);
-
- flash_reset();
- ret =3D g_test_run();
- qtest_quit(global_qtest);
- unlink(tmp_path);
-
- return ret;
+ data->s =3D qtest_initf("-m 256 -machine palmetto-bmc "
+ "-drive file=3D%s,format=3Draw,if=3Dmtd",
+ data->tmp_path);
+
+ /* fmc cs0 with n25q256a flash */
+ data->flash_base =3D 0x20000000;
+ data->spi_base =3D 0x1E620000;
+ data->jedec_id =3D 0x20ba19;
+
+ qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
+ qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sect=
or);
+ qtest_add_data_func("/ast2400/smc/erase_all", data, test_erase_all);
+ qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2400/smc/read_page_mem",
+ data, test_read_page_mem);
+ qtest_add_data_func("/ast2400/smc/write_page_mem",
+ data, test_write_page_mem);
+ qtest_add_data_func("/ast2400/smc/read_status_reg",
+ data, test_read_status_reg);
+ qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
+ data, test_status_reg_write_protection);
+ qtest_add_data_func("/ast2400/smc/write_block_protect",
+ data, test_write_block_protect);
+ qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
+ data, test_write_block_protect_bottom_bit);
}
=20
int main(int argc, char **argv)
{
+ TestData palmetto_data;
int ret;
=20
g_test_init(&argc, &argv, NULL);
- ret =3D test_palmetto_bmc();
=20
+ test_palmetto_bmc(&palmetto_data);
+ ret =3D g_test_run();
+
+ qtest_quit(palmetto_data.s);
+ unlink(palmetto_data.tmp_path);
return ret;
}
--=20
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To: qemu-arm@nongnu.org,
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 17/24] test/qtest/aspeed_smc-test: Support to test all CE pins
Date: Wed, 11 Dec 2024 07:30:51 +0100
Message-ID: <20241211063058.1222038-18-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Currently, these test cases only support to test CE0. To test all CE pins,
introduces new ce and node members in TestData structure. The ce member is =
used
for saving the ce index and node member is used for saving the node path,
respectively.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-4-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 77 ++++++++++++++++++-----------------
1 file changed, 40 insertions(+), 37 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 4c62009605d0..b8ab20b43dd6 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -32,11 +32,11 @@
* ASPEED SPI Controller registers
*/
#define R_CONF 0x00
-#define CONF_ENABLE_W0 (1 << 16)
+#define CONF_ENABLE_W0 16
#define R_CE_CTRL 0x04
#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
#define R_CTRL0 0x10
-#define CTRL_CE_STOP_ACTIVE (1 << 2)
+#define CTRL_CE_STOP_ACTIVE BIT(2)
#define CTRL_READMODE 0x0
#define CTRL_FREADMODE 0x1
#define CTRL_WRITEMODE 0x2
@@ -70,6 +70,8 @@ typedef struct TestData {
uint64_t flash_base;
uint32_t jedec_id;
char *tmp_path;
+ uint8_t cs;
+ const char *node;
} TestData;
=20
/*
@@ -140,34 +142,37 @@ static void spi_ce_ctrl(const TestData *data, uint32_=
t value)
=20
static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t c=
md)
{
- uint32_t ctrl =3D spi_readl(data, R_CTRL0);
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
ctrl &=3D ~(CTRL_USERMODE | 0xff << 16);
ctrl |=3D mode | (cmd << 16);
- spi_writel(data, R_CTRL0, ctrl);
+ spi_writel(data, ctrl_reg, ctrl);
}
=20
static void spi_ctrl_start_user(const TestData *data)
{
- uint32_t ctrl =3D spi_readl(data, R_CTRL0);
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
=20
ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- spi_writel(data, R_CTRL0, ctrl);
+ spi_writel(data, ctrl_reg, ctrl);
=20
ctrl &=3D ~CTRL_CE_STOP_ACTIVE;
- spi_writel(data, R_CTRL0, ctrl);
+ spi_writel(data, ctrl_reg, ctrl);
}
=20
static void spi_ctrl_stop_user(const TestData *data)
{
- uint32_t ctrl =3D spi_readl(data, R_CTRL0);
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
=20
ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- spi_writel(data, R_CTRL0, ctrl);
+ spi_writel(data, ctrl_reg, ctrl);
}
=20
static void flash_reset(const TestData *data)
{
- spi_conf(data, CONF_ENABLE_W0);
+ spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
=20
spi_ctrl_start_user(data);
flash_writeb(data, 0, RESET_ENABLE);
@@ -177,7 +182,7 @@ static void flash_reset(const TestData *data)
flash_writeb(data, 0, WRDI);
spi_ctrl_stop_user(data);
=20
- spi_conf_remove(data, CONF_ENABLE_W0);
+ spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
}
=20
static void test_read_jedec(const void *data)
@@ -185,7 +190,7 @@ static void test_read_jedec(const void *data)
const TestData *test_data =3D (const TestData *)data;
uint32_t jedec =3D 0x0;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, JEDEC_READ);
@@ -255,7 +260,7 @@ static void test_erase_sector(const void *data)
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
/*
* Previous page should be full of 0xffs after backend is
@@ -307,7 +312,7 @@ static void test_erase_all(const void *data)
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
/*
* Previous page should be full of 0xffs after backend is
@@ -358,7 +363,7 @@ static void test_write_page(const void *data)
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, EN_4BYTE_ADDR);
@@ -396,13 +401,12 @@ static void test_read_page_mem(const void *data)
int i;
=20
/*
- * Enable 4BYTE mode for controller. This is should be strapped by
- * HW for CE0 anyhow.
+ * Enable 4BYTE mode for controller.
*/
- spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
=20
/* Enable 4BYTE mode for flash. */
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, EN_4BYTE_ADDR);
flash_writeb(test_data, 0, WREN);
@@ -414,7 +418,7 @@ static void test_read_page_mem(const void *data)
flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
}
spi_ctrl_stop_user(test_data);
- spi_conf_remove(test_data, CONF_ENABLE_W0);
+ spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
/* Check what was written */
read_page_mem(test_data, my_page_addr, page);
@@ -439,13 +443,12 @@ static void test_write_page_mem(const void *data)
int i;
=20
/*
- * Enable 4BYTE mode for controller. This is should be strapped by
- * HW for CE0 anyhow.
+ * Enable 4BYTE mode for controller.
*/
- spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
=20
/* Enable 4BYTE mode for flash. */
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, EN_4BYTE_ADDR);
flash_writeb(test_data, 0, WREN);
@@ -473,7 +476,7 @@ static void test_read_status_reg(const void *data)
const TestData *test_data =3D (const TestData *)data;
uint8_t r;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, RDSR);
@@ -482,7 +485,7 @@ static void test_read_status_reg(const void *data)
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
g_assert(!qtest_qom_get_bool
- (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, test_data->node, "write-enable"));
=20
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, WREN);
@@ -492,7 +495,7 @@ static void test_read_status_reg(const void *data)
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL);
g_assert(qtest_qom_get_bool
- (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, test_data->node, "write-enable"));
=20
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, WRDI);
@@ -502,7 +505,7 @@ static void test_read_status_reg(const void *data)
=20
g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
g_assert(!qtest_qom_get_bool
- (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl=
e"));
+ (test_data->s, test_data->node, "write-enable"));
=20
flash_reset(test_data);
}
@@ -512,7 +515,7 @@ static void test_status_reg_write_protection(const void=
*data)
const TestData *test_data =3D (const TestData *)data;
uint8_t r;
=20
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
/* default case: WP# is high and SRWD is low -> status register writab=
le */
spi_ctrl_start_user(test_data);
@@ -537,8 +540,7 @@ static void test_status_reg_write_protection(const void=
*data)
g_assert_cmphex(r & SRWD, =3D=3D, 0);
=20
/* WP# low and SRWD low -> status register writable */
- qtest_set_irq_in(test_data->s,
- "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
+ qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
spi_ctrl_start_user(test_data);
flash_writeb(test_data, 0, WREN);
/* test ability to write SRWD */
@@ -561,8 +563,7 @@ static void test_status_reg_write_protection(const void=
*data)
/* write is not successful */
g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
=20
- qtest_set_irq_in(test_data->s,
- "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
+ qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
flash_reset(test_data);
}
=20
@@ -572,8 +573,8 @@ static void test_write_block_protect(const void *data)
uint32_t sector_size =3D 65536;
uint32_t n_sectors =3D 512;
=20
- spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
uint32_t bp_bits =3D 0b0;
=20
@@ -617,8 +618,8 @@ static void test_write_block_protect_bottom_bit(const v=
oid *data)
uint32_t sector_size =3D 65536;
uint32_t n_sectors =3D 512;
=20
- spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
- spi_conf(test_data, CONF_ENABLE_W0);
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
=20
/* top bottom bit is enabled */
uint32_t bp_bits =3D 0b00100 << 3;
@@ -676,6 +677,8 @@ static void test_palmetto_bmc(TestData *data)
data->flash_base =3D 0x20000000;
data->spi_base =3D 0x1E620000;
data->jedec_id =3D 0x20ba19;
+ data->cs =3D 0;
+ data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
=20
qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sect=
or);
--=20
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To: qemu-arm@nongnu.org,
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 18/24] test/qtest/aspeed_smc-test: Introducing a "page_addr"
data field
Date: Wed, 11 Dec 2024 07:30:52 +0100
Message-ID: <20241211063058.1222038-19-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Currently, these test cases used the hardcode offset 0x1400000 (0x14000 * 2=
56)
which was beyond the 16MB flash size for flash page read/write command test=
ing.
However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose =
size
is 1MB. To test SoC flash models, introduces a new page_addr member in Test=
Data
structure, so users can set the offset for flash page read/write command
testing.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-5-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index b8ab20b43dd6..6db18451d245 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -72,6 +72,7 @@ typedef struct TestData {
char *tmp_path;
uint8_t cs;
const char *node;
+ uint32_t page_addr;
} TestData;
=20
/*
@@ -256,7 +257,7 @@ static void assert_page_mem(const TestData *data, uint3=
2_t addr,
static void test_erase_sector(const void *data)
{
const TestData *test_data =3D (const TestData *)data;
- uint32_t some_page_addr =3D 0x600 * FLASH_PAGE_SIZE;
+ uint32_t some_page_addr =3D test_data->page_addr;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
@@ -308,7 +309,7 @@ static void test_erase_sector(const void *data)
static void test_erase_all(const void *data)
{
const TestData *test_data =3D (const TestData *)data;
- uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
+ uint32_t some_page_addr =3D test_data->page_addr;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
@@ -358,8 +359,8 @@ static void test_erase_all(const void *data)
static void test_write_page(const void *data)
{
const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
- uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
@@ -395,8 +396,8 @@ static void test_write_page(const void *data)
static void test_read_page_mem(const void *data)
{
const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
- uint32_t some_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
@@ -438,7 +439,7 @@ static void test_read_page_mem(const void *data)
static void test_write_page_mem(const void *data)
{
const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D 0x15000 * FLASH_PAGE_SIZE;
+ uint32_t my_page_addr =3D test_data->page_addr;
uint32_t page[FLASH_PAGE_SIZE / 4];
int i;
=20
@@ -679,6 +680,8 @@ static void test_palmetto_bmc(TestData *data)
data->jedec_id =3D 0x20ba19;
data->cs =3D 0;
data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
+ /* beyond 16MB */
+ data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
=20
qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sect=
or);
--=20
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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 19/24] test/qtest/aspeed_smc-test: Support to test AST2500
Date: Wed, 11 Dec 2024 07:30:53 +0100
Message-ID: <20241211063058.1222038-20-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add test_ast2500_evb function and reused testcases for AST2500 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E620000, 0x20000000 and 0, respectively.
The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB,
so set jedec_id 0xc22019.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-6-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 6db18451d245..0171ecf4ed06 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -701,17 +701,57 @@ static void test_palmetto_bmc(TestData *data)
data, test_write_block_protect_bottom_bit);
}
=20
+static void test_ast2500_evb(TestData *data)
+{
+ int ret;
+ int fd;
+
+ fd =3D g_file_open_tmp("qtest.m25p80.mx25l25635e.XXXXXX",
+ &data->tmp_path, NULL);
+ g_assert(fd >=3D 0);
+ ret =3D ftruncate(fd, 32 * 1024 * 1024);
+ g_assert(ret =3D=3D 0);
+ close(fd);
+
+ data->s =3D qtest_initf("-machine ast2500-evb "
+ "-drive file=3D%s,format=3Draw,if=3Dmtd",
+ data->tmp_path);
+
+ /* fmc cs0 with mx25l25635e flash */
+ data->flash_base =3D 0x20000000;
+ data->spi_base =3D 0x1E620000;
+ data->jedec_id =3D 0xc22019;
+ data->cs =3D 0;
+ data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
+ /* beyond 16MB */
+ data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
+
+ qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
+ qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sect=
or);
+ qtest_add_data_func("/ast2500/smc/erase_all", data, test_erase_all);
+ qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2500/smc/read_page_mem",
+ data, test_read_page_mem);
+ qtest_add_data_func("/ast2500/smc/write_page_mem",
+ data, test_write_page_mem);
+ qtest_add_data_func("/ast2500/smc/read_status_reg",
+ data, test_read_status_reg);
+}
int main(int argc, char **argv)
{
TestData palmetto_data;
+ TestData ast2500_evb_data;
int ret;
=20
g_test_init(&argc, &argv, NULL);
=20
test_palmetto_bmc(&palmetto_data);
+ test_ast2500_evb(&ast2500_evb_data);
ret =3D g_test_run();
=20
qtest_quit(palmetto_data.s);
+ qtest_quit(ast2500_evb_data.s);
unlink(palmetto_data.tmp_path);
+ unlink(ast2500_evb_data.tmp_path);
return ret;
}
--=20
2.47.1
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 20/24] test/qtest/aspeed_smc-test: Support to test AST2600
Date: Wed, 11 Dec 2024 07:30:54 +0100
Message-ID: <20241211063058.1222038-21-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add test_ast2600_evb function and reused testcases for AST2600 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E620000, 0x20000000 and 0, respectively.
The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
so set jedec_id 0xc2253a.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-7-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 41 +++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 0171ecf4ed06..30f997679ce2 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -737,21 +737,62 @@ static void test_ast2500_evb(TestData *data)
qtest_add_data_func("/ast2500/smc/read_status_reg",
data, test_read_status_reg);
}
+
+static void test_ast2600_evb(TestData *data)
+{
+ int ret;
+ int fd;
+
+ fd =3D g_file_open_tmp("qtest.m25p80.mx66u51235f.XXXXXX",
+ &data->tmp_path, NULL);
+ g_assert(fd >=3D 0);
+ ret =3D ftruncate(fd, 64 * 1024 * 1024);
+ g_assert(ret =3D=3D 0);
+ close(fd);
+
+ data->s =3D qtest_initf("-machine ast2600-evb "
+ "-drive file=3D%s,format=3Draw,if=3Dmtd",
+ data->tmp_path);
+
+ /* fmc cs0 with mx66u51235f flash */
+ data->flash_base =3D 0x20000000;
+ data->spi_base =3D 0x1E620000;
+ data->jedec_id =3D 0xc2253a;
+ data->cs =3D 0;
+ data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
+ /* beyond 16MB */
+ data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
+
+ qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
+ qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sect=
or);
+ qtest_add_data_func("/ast2600/smc/erase_all", data, test_erase_all);
+ qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2600/smc/read_page_mem",
+ data, test_read_page_mem);
+ qtest_add_data_func("/ast2600/smc/write_page_mem",
+ data, test_write_page_mem);
+ qtest_add_data_func("/ast2600/smc/read_status_reg",
+ data, test_read_status_reg);
+}
int main(int argc, char **argv)
{
TestData palmetto_data;
TestData ast2500_evb_data;
+ TestData ast2600_evb_data;
int ret;
=20
g_test_init(&argc, &argv, NULL);
=20
test_palmetto_bmc(&palmetto_data);
test_ast2500_evb(&ast2500_evb_data);
+ test_ast2600_evb(&ast2600_evb_data);
ret =3D g_test_run();
=20
qtest_quit(palmetto_data.s);
qtest_quit(ast2500_evb_data.s);
+ qtest_quit(ast2600_evb_data.s);
unlink(palmetto_data.tmp_path);
unlink(ast2500_evb_data.tmp_path);
+ unlink(ast2600_evb_data.tmp_path);
return ret;
}
--=20
2.47.1
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 21/24] test/qtest/aspeed_smc-test: Support to test AST1030
Date: Wed, 11 Dec 2024 07:30:55 +0100
Message-ID: <20241211063058.1222038-22-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add test_ast1030_evb function and reused testcases for AST1030 testing.
The base address, flash base address and ce index of fmc_cs0 are
0x7E620000, 0x80000000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB,
so set jedec_id 0xef4014.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-8-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 42 +++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 30f997679ce2..c5c38e23c5b2 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -774,11 +774,50 @@ static void test_ast2600_evb(TestData *data)
qtest_add_data_func("/ast2600/smc/read_status_reg",
data, test_read_status_reg);
}
+
+static void test_ast1030_evb(TestData *data)
+{
+ int ret;
+ int fd;
+
+ fd =3D g_file_open_tmp("qtest.m25p80.w25q80bl.XXXXXX",
+ &data->tmp_path, NULL);
+ g_assert(fd >=3D 0);
+ ret =3D ftruncate(fd, 1 * 1024 * 1024);
+ g_assert(ret =3D=3D 0);
+ close(fd);
+
+ data->s =3D qtest_initf("-machine ast1030-evb "
+ "-drive file=3D%s,format=3Draw,if=3Dmtd",
+ data->tmp_path);
+
+ /* fmc cs0 with w25q80bl flash */
+ data->flash_base =3D 0x80000000;
+ data->spi_base =3D 0x7E620000;
+ data->jedec_id =3D 0xef4014;
+ data->cs =3D 0;
+ data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
+ /* beyond 512KB */
+ data->page_addr =3D 0x800 * FLASH_PAGE_SIZE;
+
+ qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
+ qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sect=
or);
+ qtest_add_data_func("/ast1030/smc/erase_all", data, test_erase_all);
+ qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast1030/smc/read_page_mem",
+ data, test_read_page_mem);
+ qtest_add_data_func("/ast1030/smc/write_page_mem",
+ data, test_write_page_mem);
+ qtest_add_data_func("/ast1030/smc/read_status_reg",
+ data, test_read_status_reg);
+}
+
int main(int argc, char **argv)
{
TestData palmetto_data;
TestData ast2500_evb_data;
TestData ast2600_evb_data;
+ TestData ast1030_evb_data;
int ret;
=20
g_test_init(&argc, &argv, NULL);
@@ -786,13 +825,16 @@ int main(int argc, char **argv)
test_palmetto_bmc(&palmetto_data);
test_ast2500_evb(&ast2500_evb_data);
test_ast2600_evb(&ast2600_evb_data);
+ test_ast1030_evb(&ast1030_evb_data);
ret =3D g_test_run();
=20
qtest_quit(palmetto_data.s);
qtest_quit(ast2500_evb_data.s);
qtest_quit(ast2600_evb_data.s);
+ qtest_quit(ast1030_evb_data.s);
unlink(palmetto_data.tmp_path);
unlink(ast2500_evb_data.tmp_path);
unlink(ast2600_evb_data.tmp_path);
+ unlink(ast1030_evb_data.tmp_path);
return ret;
}
--=20
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 22/24] test/qtest/aspeed_smc-test: Support write page command
with QPI mode
Date: Wed, 11 Dec 2024 07:30:56 +0100
Message-ID: <20241211063058.1222038-23-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add a new testcase for write page command with QPI mode testing.
Currently, only run this testcase for AST2500, AST2600 and AST1030.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-9-jamin_lin@aspeedte=
ch.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed_smc-test.c | 74 +++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index c5c38e23c5b2..59f3876cdc36 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -36,6 +36,7 @@
#define R_CE_CTRL 0x04
#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
#define R_CTRL0 0x10
+#define CTRL_IO_QUAD_IO BIT(31)
#define CTRL_CE_STOP_ACTIVE BIT(2)
#define CTRL_READMODE 0x0
#define CTRL_FREADMODE 0x1
@@ -62,6 +63,7 @@ enum {
ERASE_SECTOR =3D 0xd8,
};
=20
+#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28))
#define FLASH_PAGE_SIZE 256
=20
typedef struct TestData {
@@ -171,6 +173,18 @@ static void spi_ctrl_stop_user(const TestData *data)
spi_writel(data, ctrl_reg, ctrl);
}
=20
+static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
+{
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
+ uint32_t mode;
+
+ mode =3D value & CTRL_IO_MODE_MASK;
+ ctrl &=3D ~CTRL_IO_MODE_MASK;
+ ctrl |=3D mode;
+ spi_writel(data, ctrl_reg, ctrl);
+}
+
static void flash_reset(const TestData *data)
{
spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
@@ -659,6 +673,60 @@ static void test_write_block_protect_bottom_bit(const =
void *data)
flash_reset(test_data);
}
=20
+static void test_write_page_qpi(const void *data)
+{
+ const TestData *test_data =3D (const TestData *)data;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ uint32_t page_pattern[] =3D {
+ 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
+ };
+ int i;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
+
+ /* Set QPI mode */
+ spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
+
+ /* Fill the page pattern */
+ for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
+ flash_writel(test_data, 0, make_be32(page_pattern[i]));
+ }
+
+ /* Fill the page with its own addresses */
+ for (; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+ }
+
+ /* Restore io mode */
+ spi_ctrl_set_io_mode(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ /* Check what was written */
+ read_page(test_data, my_page_addr, page);
+ for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
+ g_assert_cmphex(page[i], =3D=3D, page_pattern[i]);
+ }
+ for (; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
+ }
+
+ /* Check some other page. It should be full of 0xff */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
static void test_palmetto_bmc(TestData *data)
{
int ret;
@@ -736,6 +804,8 @@ static void test_ast2500_evb(TestData *data)
data, test_write_page_mem);
qtest_add_data_func("/ast2500/smc/read_status_reg",
data, test_read_status_reg);
+ qtest_add_data_func("/ast2500/smc/write_page_qpi",
+ data, test_write_page_qpi);
}
=20
static void test_ast2600_evb(TestData *data)
@@ -773,6 +843,8 @@ static void test_ast2600_evb(TestData *data)
data, test_write_page_mem);
qtest_add_data_func("/ast2600/smc/read_status_reg",
data, test_read_status_reg);
+ qtest_add_data_func("/ast2600/smc/write_page_qpi",
+ data, test_write_page_qpi);
}
=20
static void test_ast1030_evb(TestData *data)
@@ -810,6 +882,8 @@ static void test_ast1030_evb(TestData *data)
data, test_write_page_mem);
qtest_add_data_func("/ast1030/smc/read_status_reg",
data, test_read_status_reg);
+ qtest_add_data_func("/ast1030/smc/write_page_qpi",
+ data, test_write_page_qpi);
}
=20
int main(int argc, char **argv)
--=20
2.47.1
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To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 23/24] test/qtest: Introduce a new aspeed-smc-utils.c to place
common testcases
Date: Wed, 11 Dec 2024 07:30:57 +0100
Message-ID: <20241211063058.1222038-24-clg@redhat.com>
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From: Jamin Lin <jamin_lin@aspeedtech.com>
The testcases for ASPEED SMC model were placed in aspeed_smc-test.c.
However, this test file only supports for ARM32. To support all ASPEED SOCs
such as AST2700 whose CPU architecture is aarch64, introduces a new
aspeed-smc-utils source file and move all common APIs and testcases
from aspeed_smc-test.c to aspeed-smc-utils.c.
Finally, users are able to re-used these testcase for AST2700 and future
ASPEED SOCs testing.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-10-jamin_lin@aspeedt=
ech.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/aspeed-smc-utils.h | 95 ++++
tests/qtest/aspeed-smc-utils.c | 686 ++++++++++++++++++++++++++++
tests/qtest/aspeed_smc-test.c | 800 +++------------------------------
tests/qtest/meson.build | 1 +
4 files changed, 841 insertions(+), 741 deletions(-)
create mode 100644 tests/qtest/aspeed-smc-utils.h
create mode 100644 tests/qtest/aspeed-smc-utils.c
diff --git a/tests/qtest/aspeed-smc-utils.h b/tests/qtest/aspeed-smc-utils.h
new file mode 100644
index 000000000000..b07870f3b8fa
--- /dev/null
+++ b/tests/qtest/aspeed-smc-utils.h
@@ -0,0 +1,95 @@
+/*
+ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
+ * Controller)
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a=
copy
+ * of this software and associated documentation files (the "Software"), t=
o deal
+ * in the Software without restriction, including without limitation the r=
ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se=
ll
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included=
in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS=
OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT=
HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING=
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS =
IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TESTS_ASPEED_SMC_UTILS_H
+#define TESTS_ASPEED_SMC_UTILS_H
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+
+/*
+ * ASPEED SPI Controller registers
+ */
+#define R_CONF 0x00
+#define CONF_ENABLE_W0 16
+#define R_CE_CTRL 0x04
+#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
+#define R_CTRL0 0x10
+#define CTRL_IO_QUAD_IO BIT(31)
+#define CTRL_CE_STOP_ACTIVE BIT(2)
+#define CTRL_READMODE 0x0
+#define CTRL_FREADMODE 0x1
+#define CTRL_WRITEMODE 0x2
+#define CTRL_USERMODE 0x3
+#define SR_WEL BIT(1)
+
+/*
+ * Flash commands
+ */
+enum {
+ JEDEC_READ =3D 0x9f,
+ RDSR =3D 0x5,
+ WRDI =3D 0x4,
+ BULK_ERASE =3D 0xc7,
+ READ =3D 0x03,
+ PP =3D 0x02,
+ WRSR =3D 0x1,
+ WREN =3D 0x6,
+ SRWD =3D 0x80,
+ RESET_ENABLE =3D 0x66,
+ RESET_MEMORY =3D 0x99,
+ EN_4BYTE_ADDR =3D 0xB7,
+ ERASE_SECTOR =3D 0xd8,
+};
+
+#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28))
+#define FLASH_PAGE_SIZE 256
+
+typedef struct AspeedSMCTestData {
+ QTestState *s;
+ uint64_t spi_base;
+ uint64_t flash_base;
+ uint32_t jedec_id;
+ char *tmp_path;
+ uint8_t cs;
+ const char *node;
+ uint32_t page_addr;
+} AspeedSMCTestData;
+
+void aspeed_smc_test_read_jedec(const void *data);
+void aspeed_smc_test_erase_sector(const void *data);
+void aspeed_smc_test_erase_all(const void *data);
+void aspeed_smc_test_write_page(const void *data);
+void aspeed_smc_test_read_page_mem(const void *data);
+void aspeed_smc_test_write_page_mem(const void *data);
+void aspeed_smc_test_read_status_reg(const void *data);
+void aspeed_smc_test_status_reg_write_protection(const void *data);
+void aspeed_smc_test_write_block_protect(const void *data);
+void aspeed_smc_test_write_block_protect_bottom_bit(const void *data);
+void aspeed_smc_test_write_page_qpi(const void *data);
+
+#endif /* TESTS_ASPEED_SMC_UTILS_H */
diff --git a/tests/qtest/aspeed-smc-utils.c b/tests/qtest/aspeed-smc-utils.c
new file mode 100644
index 000000000000..c27d09e767e5
--- /dev/null
+++ b/tests/qtest/aspeed-smc-utils.c
@@ -0,0 +1,686 @@
+/*
+ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
+ * Controller)
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a=
copy
+ * of this software and associated documentation files (the "Software"), t=
o deal
+ * in the Software without restriction, including without limitation the r=
ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se=
ll
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included=
in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS=
OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT=
HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING=
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS =
IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
+
+/*
+ * Use an explicit bswap for the values read/wrote to the flash region
+ * as they are BE and the Aspeed CPU is LE.
+ */
+static inline uint32_t make_be32(uint32_t data)
+{
+ return bswap32(data);
+}
+
+static inline void spi_writel(const AspeedSMCTestData *data, uint64_t offs=
et,
+ uint32_t value)
+{
+ qtest_writel(data->s, data->spi_base + offset, value);
+}
+
+static inline uint32_t spi_readl(const AspeedSMCTestData *data, uint64_t o=
ffset)
+{
+ return qtest_readl(data->s, data->spi_base + offset);
+}
+
+static inline void flash_writeb(const AspeedSMCTestData *data, uint64_t of=
fset,
+ uint8_t value)
+{
+ qtest_writeb(data->s, data->flash_base + offset, value);
+}
+
+static inline void flash_writel(const AspeedSMCTestData *data, uint64_t of=
fset,
+ uint32_t value)
+{
+ qtest_writel(data->s, data->flash_base + offset, value);
+}
+
+static inline uint8_t flash_readb(const AspeedSMCTestData *data,
+ uint64_t offset)
+{
+ return qtest_readb(data->s, data->flash_base + offset);
+}
+
+static inline uint32_t flash_readl(const AspeedSMCTestData *data,
+ uint64_t offset)
+{
+ return qtest_readl(data->s, data->flash_base + offset);
+}
+
+static void spi_conf(const AspeedSMCTestData *data, uint32_t value)
+{
+ uint32_t conf =3D spi_readl(data, R_CONF);
+
+ conf |=3D value;
+ spi_writel(data, R_CONF, conf);
+}
+
+static void spi_conf_remove(const AspeedSMCTestData *data, uint32_t value)
+{
+ uint32_t conf =3D spi_readl(data, R_CONF);
+
+ conf &=3D ~value;
+ spi_writel(data, R_CONF, conf);
+}
+
+static void spi_ce_ctrl(const AspeedSMCTestData *data, uint32_t value)
+{
+ uint32_t conf =3D spi_readl(data, R_CE_CTRL);
+
+ conf |=3D value;
+ spi_writel(data, R_CE_CTRL, conf);
+}
+
+static void spi_ctrl_setmode(const AspeedSMCTestData *data, uint8_t mode,
+ uint8_t cmd)
+{
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
+ ctrl &=3D ~(CTRL_USERMODE | 0xff << 16);
+ ctrl |=3D mode | (cmd << 16);
+ spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_start_user(const AspeedSMCTestData *data)
+{
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
+
+ ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+ spi_writel(data, ctrl_reg, ctrl);
+
+ ctrl &=3D ~CTRL_CE_STOP_ACTIVE;
+ spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_stop_user(const AspeedSMCTestData *data)
+{
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
+
+ ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+ spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_set_io_mode(const AspeedSMCTestData *data, uint32_t v=
alue)
+{
+ uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
+ uint32_t ctrl =3D spi_readl(data, ctrl_reg);
+ uint32_t mode;
+
+ mode =3D value & CTRL_IO_MODE_MASK;
+ ctrl &=3D ~CTRL_IO_MODE_MASK;
+ ctrl |=3D mode;
+ spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void flash_reset(const AspeedSMCTestData *data)
+{
+ spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
+
+ spi_ctrl_start_user(data);
+ flash_writeb(data, 0, RESET_ENABLE);
+ flash_writeb(data, 0, RESET_MEMORY);
+ flash_writeb(data, 0, WREN);
+ flash_writeb(data, 0, BULK_ERASE);
+ flash_writeb(data, 0, WRDI);
+ spi_ctrl_stop_user(data);
+
+ spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
+}
+
+static void read_page(const AspeedSMCTestData *data, uint32_t addr,
+ uint32_t *page)
+{
+ int i;
+
+ spi_ctrl_start_user(data);
+
+ flash_writeb(data, 0, EN_4BYTE_ADDR);
+ flash_writeb(data, 0, READ);
+ flash_writel(data, 0, make_be32(addr));
+
+ /* Continuous read are supported */
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ page[i] =3D make_be32(flash_readl(data, 0));
+ }
+ spi_ctrl_stop_user(data);
+}
+
+static void read_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+ uint32_t *page)
+{
+ int i;
+
+ /* move out USER mode to use direct reads from the AHB bus */
+ spi_ctrl_setmode(data, CTRL_READMODE, READ);
+
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ page[i] =3D make_be32(flash_readl(data, addr + i * 4));
+ }
+}
+
+static void write_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+ uint32_t write_value)
+{
+ spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
+
+ for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(data, addr + i * 4, write_value);
+ }
+}
+
+static void assert_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+ uint32_t expected_value)
+{
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ read_page_mem(data, addr, page);
+ for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, expected_value);
+ }
+}
+
+void aspeed_smc_test_read_jedec(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t jedec =3D 0x0;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, JEDEC_READ);
+ jedec |=3D flash_readb(test_data, 0) << 16;
+ jedec |=3D flash_readb(test_data, 0) << 8;
+ jedec |=3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ flash_reset(test_data);
+
+ g_assert_cmphex(jedec, =3D=3D, test_data->jedec_id);
+}
+
+void aspeed_smc_test_erase_sector(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t some_page_addr =3D test_data->page_addr;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ int i;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ /*
+ * Previous page should be full of 0xffs after backend is
+ * initialized
+ */
+ read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
+
+ /* Fill the page with its own addresses */
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
+ }
+ spi_ctrl_stop_user(test_data);
+
+ /* Check the page is correctly written */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
+ }
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, ERASE_SECTOR);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
+ spi_ctrl_stop_user(test_data);
+
+ /* Check the page is erased */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_erase_all(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t some_page_addr =3D test_data->page_addr;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ int i;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ /*
+ * Previous page should be full of 0xffs after backend is
+ * initialized
+ */
+ read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(some_page_addr));
+
+ /* Fill the page with its own addresses */
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
+ }
+ spi_ctrl_stop_user(test_data);
+
+ /* Check the page is correctly written */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
+ }
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ spi_ctrl_stop_user(test_data);
+
+ /* Check the page is erased */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ int i;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
+
+ /* Fill the page with its own addresses */
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+ }
+ spi_ctrl_stop_user(test_data);
+
+ /* Check what was written */
+ read_page(test_data, my_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
+ }
+
+ /* Check some other page. It should be full of 0xff */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_read_page_mem(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ int i;
+
+ /*
+ * Enable 4BYTE mode for controller.
+ */
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+
+ /* Enable 4BYTE mode for flash. */
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
+
+ /* Fill the page with its own addresses */
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+ }
+ spi_ctrl_stop_user(test_data);
+ spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ /* Check what was written */
+ read_page_mem(test_data, my_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
+ }
+
+ /* Check some other page. It should be full of 0xff */
+ read_page_mem(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page_mem(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ int i;
+
+ /*
+ * Enable 4BYTE mode for controller.
+ */
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+
+ /* Enable 4BYTE mode for flash. */
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
+
+ /* move out USER mode to use direct writes to the AHB bus */
+ spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
+
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, my_page_addr + i * 4,
+ make_be32(my_page_addr + i * 4));
+ }
+
+ /* Check what was written */
+ read_page_mem(test_data, my_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_read_status_reg(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint8_t r;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
+ g_assert(!qtest_qom_get_bool
+ (test_data->s, test_data->node, "write-enable"));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL);
+ g_assert(qtest_qom_get_bool
+ (test_data->s, test_data->node, "write-enable"));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WRDI);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
+ g_assert(!qtest_qom_get_bool
+ (test_data->s, test_data->node, "write-enable"));
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_status_reg_write_protection(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint8_t r;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ /* default case: WP# is high and SRWD is low -> status register writab=
le */
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ /* test ability to write SRWD */
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, SRWD);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+ g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
+
+ /* WP# high and SRWD high -> status register writable */
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ /* test ability to write SRWD */
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, 0);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+ g_assert_cmphex(r & SRWD, =3D=3D, 0);
+
+ /* WP# low and SRWD low -> status register writable */
+ qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ /* test ability to write SRWD */
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, SRWD);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+ g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
+
+ /* WP# low and SRWD high -> status register NOT writable */
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0 , WREN);
+ /* test ability to write SRWD */
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, 0);
+ flash_writeb(test_data, 0, RDSR);
+ r =3D flash_readb(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+ /* write is not successful */
+ g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
+
+ qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_block_protect(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t sector_size =3D 65536;
+ uint32_t n_sectors =3D 512;
+
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ uint32_t bp_bits =3D 0b0;
+
+ for (int i =3D 0; i < 16; i++) {
+ bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, bp_bits);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
+
+ uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
+ uint32_t protection_start =3D n_sectors - num_protected_sectors;
+ uint32_t protection_end =3D n_sectors;
+
+ for (int sector =3D 0; sector < n_sectors; sector++) {
+ uint32_t addr =3D sector * sector_size;
+
+ assert_page_mem(test_data, addr, 0xffffffff);
+ write_page_mem(test_data, addr, make_be32(0xabcdef12));
+
+ uint32_t expected_value =3D protection_start <=3D sector
+ && sector < protection_end
+ ? 0xffffffff : 0xabcdef12;
+
+ assert_page_mem(test_data, addr, expected_value);
+ }
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_block_protect_bottom_bit(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t sector_size =3D 65536;
+ uint32_t n_sectors =3D 512;
+
+ spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ /* top bottom bit is enabled */
+ uint32_t bp_bits =3D 0b00100 << 3;
+
+ for (int i =3D 0; i < 16; i++) {
+ bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, BULK_ERASE);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, WRSR);
+ flash_writeb(test_data, 0, bp_bits);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ spi_ctrl_stop_user(test_data);
+
+ uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
+ uint32_t protection_start =3D 0;
+ uint32_t protection_end =3D num_protected_sectors;
+
+ for (int sector =3D 0; sector < n_sectors; sector++) {
+ uint32_t addr =3D sector * sector_size;
+
+ assert_page_mem(test_data, addr, 0xffffffff);
+ write_page_mem(test_data, addr, make_be32(0xabcdef12));
+
+ uint32_t expected_value =3D protection_start <=3D sector
+ && sector < protection_end
+ ? 0xffffffff : 0xabcdef12;
+
+ assert_page_mem(test_data, addr, expected_value);
+ }
+ }
+
+ flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page_qpi(const void *data)
+{
+ const AspeedSMCTestData *test_data =3D (const AspeedSMCTestData *)data;
+ uint32_t my_page_addr =3D test_data->page_addr;
+ uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ uint32_t page_pattern[] =3D {
+ 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
+ };
+ int i;
+
+ spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+ spi_ctrl_start_user(test_data);
+ flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+ flash_writeb(test_data, 0, WREN);
+ flash_writeb(test_data, 0, PP);
+ flash_writel(test_data, 0, make_be32(my_page_addr));
+
+ /* Set QPI mode */
+ spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
+
+ /* Fill the page pattern */
+ for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
+ flash_writel(test_data, 0, make_be32(page_pattern[i]));
+ }
+
+ /* Fill the page with its own addresses */
+ for (; i < FLASH_PAGE_SIZE / 4; i++) {
+ flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+ }
+
+ /* Restore io mode */
+ spi_ctrl_set_io_mode(test_data, 0);
+ spi_ctrl_stop_user(test_data);
+
+ /* Check what was written */
+ read_page(test_data, my_page_addr, page);
+ for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
+ g_assert_cmphex(page[i], =3D=3D, page_pattern[i]);
+ }
+ for (; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
+ }
+
+ /* Check some other page. It should be full of 0xff */
+ read_page(test_data, some_page_addr, page);
+ for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
+ }
+
+ flash_reset(test_data);
+}
+
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 59f3876cdc36..4e1389385d85 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -27,707 +27,9 @@
#include "qemu/bswap.h"
#include "libqtest-single.h"
#include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
=20
-/*
- * ASPEED SPI Controller registers
- */
-#define R_CONF 0x00
-#define CONF_ENABLE_W0 16
-#define R_CE_CTRL 0x04
-#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
-#define R_CTRL0 0x10
-#define CTRL_IO_QUAD_IO BIT(31)
-#define CTRL_CE_STOP_ACTIVE BIT(2)
-#define CTRL_READMODE 0x0
-#define CTRL_FREADMODE 0x1
-#define CTRL_WRITEMODE 0x2
-#define CTRL_USERMODE 0x3
-#define SR_WEL BIT(1)
-
-/*
- * Flash commands
- */
-enum {
- JEDEC_READ =3D 0x9f,
- RDSR =3D 0x5,
- WRDI =3D 0x4,
- BULK_ERASE =3D 0xc7,
- READ =3D 0x03,
- PP =3D 0x02,
- WRSR =3D 0x1,
- WREN =3D 0x6,
- SRWD =3D 0x80,
- RESET_ENABLE =3D 0x66,
- RESET_MEMORY =3D 0x99,
- EN_4BYTE_ADDR =3D 0xB7,
- ERASE_SECTOR =3D 0xd8,
-};
-
-#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28))
-#define FLASH_PAGE_SIZE 256
-
-typedef struct TestData {
- QTestState *s;
- uint64_t spi_base;
- uint64_t flash_base;
- uint32_t jedec_id;
- char *tmp_path;
- uint8_t cs;
- const char *node;
- uint32_t page_addr;
-} TestData;
-
-/*
- * Use an explicit bswap for the values read/wrote to the flash region
- * as they are BE and the Aspeed CPU is LE.
- */
-static inline uint32_t make_be32(uint32_t data)
-{
- return bswap32(data);
-}
-
-static inline void spi_writel(const TestData *data, uint64_t offset,
- uint32_t value)
-{
- qtest_writel(data->s, data->spi_base + offset, value);
-}
-
-static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
-{
- return qtest_readl(data->s, data->spi_base + offset);
-}
-
-static inline void flash_writeb(const TestData *data, uint64_t offset,
- uint8_t value)
-{
- qtest_writeb(data->s, data->flash_base + offset, value);
-}
-
-static inline void flash_writel(const TestData *data, uint64_t offset,
- uint32_t value)
-{
- qtest_writel(data->s, data->flash_base + offset, value);
-}
-
-static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
-{
- return qtest_readb(data->s, data->flash_base + offset);
-}
-
-static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
-{
- return qtest_readl(data->s, data->flash_base + offset);
-}
-
-static void spi_conf(const TestData *data, uint32_t value)
-{
- uint32_t conf =3D spi_readl(data, R_CONF);
-
- conf |=3D value;
- spi_writel(data, R_CONF, conf);
-}
-
-static void spi_conf_remove(const TestData *data, uint32_t value)
-{
- uint32_t conf =3D spi_readl(data, R_CONF);
-
- conf &=3D ~value;
- spi_writel(data, R_CONF, conf);
-}
-
-static void spi_ce_ctrl(const TestData *data, uint32_t value)
-{
- uint32_t conf =3D spi_readl(data, R_CE_CTRL);
-
- conf |=3D value;
- spi_writel(data, R_CE_CTRL, conf);
-}
-
-static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t c=
md)
-{
- uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
- uint32_t ctrl =3D spi_readl(data, ctrl_reg);
- ctrl &=3D ~(CTRL_USERMODE | 0xff << 16);
- ctrl |=3D mode | (cmd << 16);
- spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_start_user(const TestData *data)
-{
- uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
- uint32_t ctrl =3D spi_readl(data, ctrl_reg);
-
- ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- spi_writel(data, ctrl_reg, ctrl);
-
- ctrl &=3D ~CTRL_CE_STOP_ACTIVE;
- spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_stop_user(const TestData *data)
-{
- uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
- uint32_t ctrl =3D spi_readl(data, ctrl_reg);
-
- ctrl |=3D CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
- spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
-{
- uint32_t ctrl_reg =3D R_CTRL0 + data->cs * 4;
- uint32_t ctrl =3D spi_readl(data, ctrl_reg);
- uint32_t mode;
-
- mode =3D value & CTRL_IO_MODE_MASK;
- ctrl &=3D ~CTRL_IO_MODE_MASK;
- ctrl |=3D mode;
- spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void flash_reset(const TestData *data)
-{
- spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
-
- spi_ctrl_start_user(data);
- flash_writeb(data, 0, RESET_ENABLE);
- flash_writeb(data, 0, RESET_MEMORY);
- flash_writeb(data, 0, WREN);
- flash_writeb(data, 0, BULK_ERASE);
- flash_writeb(data, 0, WRDI);
- spi_ctrl_stop_user(data);
-
- spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
-}
-
-static void test_read_jedec(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t jedec =3D 0x0;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, JEDEC_READ);
- jedec |=3D flash_readb(test_data, 0) << 16;
- jedec |=3D flash_readb(test_data, 0) << 8;
- jedec |=3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
-
- flash_reset(test_data);
-
- g_assert_cmphex(jedec, =3D=3D, test_data->jedec_id);
-}
-
-static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
-{
- int i;
-
- spi_ctrl_start_user(data);
-
- flash_writeb(data, 0, EN_4BYTE_ADDR);
- flash_writeb(data, 0, READ);
- flash_writel(data, 0, make_be32(addr));
-
- /* Continuous read are supported */
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- page[i] =3D make_be32(flash_readl(data, 0));
- }
- spi_ctrl_stop_user(data);
-}
-
-static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *p=
age)
-{
- int i;
-
- /* move out USER mode to use direct reads from the AHB bus */
- spi_ctrl_setmode(data, CTRL_READMODE, READ);
-
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- page[i] =3D make_be32(flash_readl(data, addr + i * 4));
- }
-}
-
-static void write_page_mem(const TestData *data, uint32_t addr,
- uint32_t write_value)
-{
- spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
-
- for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(data, addr + i * 4, write_value);
- }
-}
-
-static void assert_page_mem(const TestData *data, uint32_t addr,
- uint32_t expected_value)
-{
- uint32_t page[FLASH_PAGE_SIZE / 4];
- read_page_mem(data, addr, page);
- for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, expected_value);
- }
-}
-
-static void test_erase_sector(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t some_page_addr =3D test_data->page_addr;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- int i;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- /*
- * Previous page should be full of 0xffs after backend is
- * initialized
- */
- read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, PP);
- flash_writel(test_data, 0, make_be32(some_page_addr));
-
- /* Fill the page with its own addresses */
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
- }
- spi_ctrl_stop_user(test_data);
-
- /* Check the page is correctly written */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
- }
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, ERASE_SECTOR);
- flash_writel(test_data, 0, make_be32(some_page_addr));
- spi_ctrl_stop_user(test_data);
-
- /* Check the page is erased */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- flash_reset(test_data);
-}
-
-static void test_erase_all(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t some_page_addr =3D test_data->page_addr;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- int i;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- /*
- * Previous page should be full of 0xffs after backend is
- * initialized
- */
- read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, PP);
- flash_writel(test_data, 0, make_be32(some_page_addr));
-
- /* Fill the page with its own addresses */
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
- }
- spi_ctrl_stop_user(test_data);
-
- /* Check the page is correctly written */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, some_page_addr + i * 4);
- }
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, BULK_ERASE);
- spi_ctrl_stop_user(test_data);
-
- /* Check the page is erased */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- flash_reset(test_data);
-}
-
-static void test_write_page(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D test_data->page_addr;
- uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- int i;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, PP);
- flash_writel(test_data, 0, make_be32(my_page_addr));
-
- /* Fill the page with its own addresses */
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
- }
- spi_ctrl_stop_user(test_data);
-
- /* Check what was written */
- read_page(test_data, my_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
- }
-
- /* Check some other page. It should be full of 0xff */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- flash_reset(test_data);
-}
-
-static void test_read_page_mem(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D test_data->page_addr;
- uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- int i;
-
- /*
- * Enable 4BYTE mode for controller.
- */
- spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-
- /* Enable 4BYTE mode for flash. */
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, PP);
- flash_writel(test_data, 0, make_be32(my_page_addr));
-
- /* Fill the page with its own addresses */
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
- }
- spi_ctrl_stop_user(test_data);
- spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- /* Check what was written */
- read_page_mem(test_data, my_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
- }
-
- /* Check some other page. It should be full of 0xff */
- read_page_mem(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- flash_reset(test_data);
-}
-
-static void test_write_page_mem(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D test_data->page_addr;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- int i;
-
- /*
- * Enable 4BYTE mode for controller.
- */
- spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-
- /* Enable 4BYTE mode for flash. */
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- spi_ctrl_stop_user(test_data);
-
- /* move out USER mode to use direct writes to the AHB bus */
- spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
-
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, my_page_addr + i * 4,
- make_be32(my_page_addr + i * 4));
- }
-
- /* Check what was written */
- read_page_mem(test_data, my_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
- }
-
- flash_reset(test_data);
-}
-
-static void test_read_status_reg(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint8_t r;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
-
- g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
- g_assert(!qtest_qom_get_bool
- (test_data->s, test_data->node, "write-enable"));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
-
- g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL);
- g_assert(qtest_qom_get_bool
- (test_data->s, test_data->node, "write-enable"));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WRDI);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
-
- g_assert_cmphex(r & SR_WEL, =3D=3D, 0);
- g_assert(!qtest_qom_get_bool
- (test_data->s, test_data->node, "write-enable"));
-
- flash_reset(test_data);
-}
-
-static void test_status_reg_write_protection(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint8_t r;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- /* default case: WP# is high and SRWD is low -> status register writab=
le */
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- /* test ability to write SRWD */
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, SRWD);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
- g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
-
- /* WP# high and SRWD high -> status register writable */
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- /* test ability to write SRWD */
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, 0);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
- g_assert_cmphex(r & SRWD, =3D=3D, 0);
-
- /* WP# low and SRWD low -> status register writable */
- qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- /* test ability to write SRWD */
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, SRWD);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
- g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
-
- /* WP# low and SRWD high -> status register NOT writable */
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0 , WREN);
- /* test ability to write SRWD */
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, 0);
- flash_writeb(test_data, 0, RDSR);
- r =3D flash_readb(test_data, 0);
- spi_ctrl_stop_user(test_data);
- /* write is not successful */
- g_assert_cmphex(r & SRWD, =3D=3D, SRWD);
-
- qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
- flash_reset(test_data);
-}
-
-static void test_write_block_protect(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t sector_size =3D 65536;
- uint32_t n_sectors =3D 512;
-
- spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- uint32_t bp_bits =3D 0b0;
-
- for (int i =3D 0; i < 16; i++) {
- bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, BULK_ERASE);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, bp_bits);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- spi_ctrl_stop_user(test_data);
-
- uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
- uint32_t protection_start =3D n_sectors - num_protected_sectors;
- uint32_t protection_end =3D n_sectors;
-
- for (int sector =3D 0; sector < n_sectors; sector++) {
- uint32_t addr =3D sector * sector_size;
-
- assert_page_mem(test_data, addr, 0xffffffff);
- write_page_mem(test_data, addr, make_be32(0xabcdef12));
-
- uint32_t expected_value =3D protection_start <=3D sector
- && sector < protection_end
- ? 0xffffffff : 0xabcdef12;
-
- assert_page_mem(test_data, addr, expected_value);
- }
- }
-
- flash_reset(test_data);
-}
-
-static void test_write_block_protect_bottom_bit(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t sector_size =3D 65536;
- uint32_t n_sectors =3D 512;
-
- spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- /* top bottom bit is enabled */
- uint32_t bp_bits =3D 0b00100 << 3;
-
- for (int i =3D 0; i < 16; i++) {
- bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, BULK_ERASE);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, WRSR);
- flash_writeb(test_data, 0, bp_bits);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- spi_ctrl_stop_user(test_data);
-
- uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors=
) : 0;
- uint32_t protection_start =3D 0;
- uint32_t protection_end =3D num_protected_sectors;
-
- for (int sector =3D 0; sector < n_sectors; sector++) {
- uint32_t addr =3D sector * sector_size;
-
- assert_page_mem(test_data, addr, 0xffffffff);
- write_page_mem(test_data, addr, make_be32(0xabcdef12));
-
- uint32_t expected_value =3D protection_start <=3D sector
- && sector < protection_end
- ? 0xffffffff : 0xabcdef12;
-
- assert_page_mem(test_data, addr, expected_value);
- }
- }
-
- flash_reset(test_data);
-}
-
-static void test_write_page_qpi(const void *data)
-{
- const TestData *test_data =3D (const TestData *)data;
- uint32_t my_page_addr =3D test_data->page_addr;
- uint32_t some_page_addr =3D my_page_addr + FLASH_PAGE_SIZE;
- uint32_t page[FLASH_PAGE_SIZE / 4];
- uint32_t page_pattern[] =3D {
- 0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
- };
- int i;
-
- spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
- spi_ctrl_start_user(test_data);
- flash_writeb(test_data, 0, EN_4BYTE_ADDR);
- flash_writeb(test_data, 0, WREN);
- flash_writeb(test_data, 0, PP);
- flash_writel(test_data, 0, make_be32(my_page_addr));
-
- /* Set QPI mode */
- spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
-
- /* Fill the page pattern */
- for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
- flash_writel(test_data, 0, make_be32(page_pattern[i]));
- }
-
- /* Fill the page with its own addresses */
- for (; i < FLASH_PAGE_SIZE / 4; i++) {
- flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
- }
-
- /* Restore io mode */
- spi_ctrl_set_io_mode(test_data, 0);
- spi_ctrl_stop_user(test_data);
-
- /* Check what was written */
- read_page(test_data, my_page_addr, page);
- for (i =3D 0; i < ARRAY_SIZE(page_pattern); i++) {
- g_assert_cmphex(page[i], =3D=3D, page_pattern[i]);
- }
- for (; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, my_page_addr + i * 4);
- }
-
- /* Check some other page. It should be full of 0xff */
- read_page(test_data, some_page_addr, page);
- for (i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) {
- g_assert_cmphex(page[i], =3D=3D, 0xffffffff);
- }
-
- flash_reset(test_data);
-}
-
-static void test_palmetto_bmc(TestData *data)
+static void test_palmetto_bmc(AspeedSMCTestData *data)
{
int ret;
int fd;
@@ -751,25 +53,29 @@ static void test_palmetto_bmc(TestData *data)
/* beyond 16MB */
data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
=20
- qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
- qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sect=
or);
- qtest_add_data_func("/ast2400/smc/erase_all", data, test_erase_all);
- qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2400/smc/read_jedec",
+ data, aspeed_smc_test_read_jedec);
+ qtest_add_data_func("/ast2400/smc/erase_sector",
+ data, aspeed_smc_test_erase_sector);
+ qtest_add_data_func("/ast2400/smc/erase_all",
+ data, aspeed_smc_test_erase_all);
+ qtest_add_data_func("/ast2400/smc/write_page",
+ data, aspeed_smc_test_write_page);
qtest_add_data_func("/ast2400/smc/read_page_mem",
- data, test_read_page_mem);
+ data, aspeed_smc_test_read_page_mem);
qtest_add_data_func("/ast2400/smc/write_page_mem",
- data, test_write_page_mem);
+ data, aspeed_smc_test_write_page_mem);
qtest_add_data_func("/ast2400/smc/read_status_reg",
- data, test_read_status_reg);
+ data, aspeed_smc_test_read_status_reg);
qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
- data, test_status_reg_write_protection);
+ data, aspeed_smc_test_status_reg_write_protection);
qtest_add_data_func("/ast2400/smc/write_block_protect",
- data, test_write_block_protect);
+ data, aspeed_smc_test_write_block_protect);
qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
- data, test_write_block_protect_bottom_bit);
+ data, aspeed_smc_test_write_block_protect_bottom_b=
it);
}
=20
-static void test_ast2500_evb(TestData *data)
+static void test_ast2500_evb(AspeedSMCTestData *data)
{
int ret;
int fd;
@@ -794,21 +100,25 @@ static void test_ast2500_evb(TestData *data)
/* beyond 16MB */
data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
=20
- qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
- qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sect=
or);
- qtest_add_data_func("/ast2500/smc/erase_all", data, test_erase_all);
- qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2500/smc/read_jedec",
+ data, aspeed_smc_test_read_jedec);
+ qtest_add_data_func("/ast2500/smc/erase_sector",
+ data, aspeed_smc_test_erase_sector);
+ qtest_add_data_func("/ast2500/smc/erase_all",
+ data, aspeed_smc_test_erase_all);
+ qtest_add_data_func("/ast2500/smc/write_page",
+ data, aspeed_smc_test_write_page);
qtest_add_data_func("/ast2500/smc/read_page_mem",
- data, test_read_page_mem);
+ data, aspeed_smc_test_read_page_mem);
qtest_add_data_func("/ast2500/smc/write_page_mem",
- data, test_write_page_mem);
+ data, aspeed_smc_test_write_page_mem);
qtest_add_data_func("/ast2500/smc/read_status_reg",
- data, test_read_status_reg);
+ data, aspeed_smc_test_read_status_reg);
qtest_add_data_func("/ast2500/smc/write_page_qpi",
- data, test_write_page_qpi);
+ data, aspeed_smc_test_write_page_qpi);
}
=20
-static void test_ast2600_evb(TestData *data)
+static void test_ast2600_evb(AspeedSMCTestData *data)
{
int ret;
int fd;
@@ -833,21 +143,25 @@ static void test_ast2600_evb(TestData *data)
/* beyond 16MB */
data->page_addr =3D 0x14000 * FLASH_PAGE_SIZE;
=20
- qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
- qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sect=
or);
- qtest_add_data_func("/ast2600/smc/erase_all", data, test_erase_all);
- qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast2600/smc/read_jedec",
+ data, aspeed_smc_test_read_jedec);
+ qtest_add_data_func("/ast2600/smc/erase_sector",
+ data, aspeed_smc_test_erase_sector);
+ qtest_add_data_func("/ast2600/smc/erase_all",
+ data, aspeed_smc_test_erase_all);
+ qtest_add_data_func("/ast2600/smc/write_page",
+ data, aspeed_smc_test_write_page);
qtest_add_data_func("/ast2600/smc/read_page_mem",
- data, test_read_page_mem);
+ data, aspeed_smc_test_read_page_mem);
qtest_add_data_func("/ast2600/smc/write_page_mem",
- data, test_write_page_mem);
+ data, aspeed_smc_test_write_page_mem);
qtest_add_data_func("/ast2600/smc/read_status_reg",
- data, test_read_status_reg);
+ data, aspeed_smc_test_read_status_reg);
qtest_add_data_func("/ast2600/smc/write_page_qpi",
- data, test_write_page_qpi);
+ data, aspeed_smc_test_write_page_qpi);
}
=20
-static void test_ast1030_evb(TestData *data)
+static void test_ast1030_evb(AspeedSMCTestData *data)
{
int ret;
int fd;
@@ -872,26 +186,30 @@ static void test_ast1030_evb(TestData *data)
/* beyond 512KB */
data->page_addr =3D 0x800 * FLASH_PAGE_SIZE;
=20
- qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
- qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sect=
or);
- qtest_add_data_func("/ast1030/smc/erase_all", data, test_erase_all);
- qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
+ qtest_add_data_func("/ast1030/smc/read_jedec",
+ data, aspeed_smc_test_read_jedec);
+ qtest_add_data_func("/ast1030/smc/erase_sector",
+ data, aspeed_smc_test_erase_sector);
+ qtest_add_data_func("/ast1030/smc/erase_all",
+ data, aspeed_smc_test_erase_all);
+ qtest_add_data_func("/ast1030/smc/write_page",
+ data, aspeed_smc_test_write_page);
qtest_add_data_func("/ast1030/smc/read_page_mem",
- data, test_read_page_mem);
+ data, aspeed_smc_test_read_page_mem);
qtest_add_data_func("/ast1030/smc/write_page_mem",
- data, test_write_page_mem);
+ data, aspeed_smc_test_write_page_mem);
qtest_add_data_func("/ast1030/smc/read_status_reg",
- data, test_read_status_reg);
+ data, aspeed_smc_test_read_status_reg);
qtest_add_data_func("/ast1030/smc/write_page_qpi",
- data, test_write_page_qpi);
+ data, aspeed_smc_test_write_page_qpi);
}
=20
int main(int argc, char **argv)
{
- TestData palmetto_data;
- TestData ast2500_evb_data;
- TestData ast2600_evb_data;
- TestData ast1030_evb_data;
+ AspeedSMCTestData palmetto_data;
+ AspeedSMCTestData ast2500_evb_data;
+ AspeedSMCTestData ast2600_evb_data;
+ AspeedSMCTestData ast1030_evb_data;
int ret;
=20
g_test_init(&argc, &argv, NULL);
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index bd41c9da5fd9..f8b3907e370d 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -360,6 +360,7 @@ qtests =3D {
'virtio-net-failover': files('migration-helpers.c'),
'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
+ 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
}
=20
if vnc.found()
--=20
2.47.1
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Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PULL 24/24] test/qtest/ast2700-smc-test: Support to test AST2700
Date: Wed, 11 Dec 2024 07:30:58 +0100
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From: Jamin Lin <jamin_lin@aspeedtech.com>
Add test_ast2700_evb function and reused testcases which are from
aspeed_smc-test.c for AST2700 testing. The base address, flash base address
and ce index of fmc_cs0 are 0x14000000, 0x100000000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB,
so set jedec_id 0xef4021.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-11-jamin_lin@aspeedt=
ech.com
Signed-off-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
tests/qtest/ast2700-smc-test.c | 71 ++++++++++++++++++++++++++++++++++
tests/qtest/meson.build | 4 +-
2 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/ast2700-smc-test.c
diff --git a/tests/qtest/ast2700-smc-test.c b/tests/qtest/ast2700-smc-test.c
new file mode 100644
index 000000000000..d1c485630744
--- /dev/null
+++ b/tests/qtest/ast2700-smc-test.c
@@ -0,0 +1,71 @@
+/*
+ * QTest testcase for the M25P80 Flash using the ASPEED SPI Controller sin=
ce
+ * AST2700.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
+
+static void test_ast2700_evb(AspeedSMCTestData *data)
+{
+ int ret;
+ int fd;
+
+ fd =3D g_file_open_tmp("qtest.m25p80.w25q01jvq.XXXXXX",
+ &data->tmp_path, NULL);
+ g_assert(fd >=3D 0);
+ ret =3D ftruncate(fd, 128 * 1024 * 1024);
+ g_assert(ret =3D=3D 0);
+ close(fd);
+
+ data->s =3D qtest_initf("-machine ast2700-evb "
+ "-drive file=3D%s,format=3Draw,if=3Dmtd",
+ data->tmp_path);
+
+ /* fmc cs0 with w25q01jvq flash */
+ data->flash_base =3D 0x100000000;
+ data->spi_base =3D 0x14000000;
+ data->jedec_id =3D 0xef4021;
+ data->cs =3D 0;
+ data->node =3D "/machine/soc/fmc/ssi.0/child[0]";
+ /* beyond 64MB */
+ data->page_addr =3D 0x40000 * FLASH_PAGE_SIZE;
+
+ qtest_add_data_func("/ast2700/smc/read_jedec",
+ data, aspeed_smc_test_read_jedec);
+ qtest_add_data_func("/ast2700/smc/erase_sector",
+ data, aspeed_smc_test_erase_sector);
+ qtest_add_data_func("/ast2700/smc/erase_all",
+ data, aspeed_smc_test_erase_all);
+ qtest_add_data_func("/ast2700/smc/write_page",
+ data, aspeed_smc_test_write_page);
+ qtest_add_data_func("/ast2700/smc/read_page_mem",
+ data, aspeed_smc_test_read_page_mem);
+ qtest_add_data_func("/ast2700/smc/write_page_mem",
+ data, aspeed_smc_test_write_page_mem);
+ qtest_add_data_func("/ast2700/smc/read_status_reg",
+ data, aspeed_smc_test_read_status_reg);
+ qtest_add_data_func("/ast2700/smc/write_page_qpi",
+ data, aspeed_smc_test_write_page_qpi);
+}
+
+int main(int argc, char **argv)
+{
+ AspeedSMCTestData ast2700_evb_data;
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ test_ast2700_evb(&ast2700_evb_data);
+ ret =3D g_test_run();
+
+ qtest_quit(ast2700_evb_data.s);
+ unlink(ast2700_evb_data.tmp_path);
+ return ret;
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index f8b3907e370d..89db3ecf2ff7 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -214,7 +214,8 @@ qtests_aspeed =3D \
'aspeed_smc-test',
'aspeed_gpio-test']
qtests_aspeed64 =3D \
- ['ast2700-gpio-test']
+ ['ast2700-gpio-test',
+ 'ast2700-smc-test']
=20
qtests_stm32l4x5 =3D \
['stm32l4x5_exti-test',
@@ -361,6 +362,7 @@ qtests =3D {
'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
+ 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'),
}
=20
if vnc.found()
--=20
2.47.1