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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 01/10] target/arm: Move some TLBI insns to their own source
 file
Date: Tue, 10 Dec 2024 16:04:43 +0000
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target/arm/helper.c is very large and unwieldy.  One subset of code
that we can pull out into its own file is the cpreg arrays and
corresponding functions for the TLBI instructions.

Because these are instructions they are only relevant for TCG and we
can make the new file only be built for CONFIG_TCG.

In this commit we move the AArch32 instructions from:
 not_v7_cp_reginfo[]
 v7_cp_reginfo[]
 v7mp_cp_reginfo[]
 v8_cp_reginfo[]
into a new file target/arm/tcg/tlb-insns.c.

A few small functions are used both by functions we haven't yet moved
across and by functions we have already moved.  We temporarily make
these global with a prototype in cpregs.h; when the move of all TLBI
insns is complete these will return to being file-local.

For CONFIG_TCG, this is just moving code around.  For a KVM only
build, these cpregs will no longer be added to the cpregs hashtable
for the CPU.  However this should not be a behaviour change, because:
 * we never try to migration sync or otherwise include
   ARM_CP_NO_RAW cpregs
 * for migration we treat the kernel's list of system registers
   as the authoritative one, so these TLBI insns were never
   in it anyway
The no-tcg stub of define_tlb_insn_regs() therefore does nothing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  14 +++
 target/arm/internals.h     |   3 +
 target/arm/helper.c        | 231 ++--------------------------------
 target/arm/tcg-stubs.c     |   5 +
 target/arm/tcg/tlb-insns.c | 246 +++++++++++++++++++++++++++++++++++++
 target/arm/tcg/meson.build |   1 +
 6 files changed, 280 insertions(+), 220 deletions(-)
 create mode 100644 target/arm/tcg/tlb-insns.c

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index cc7c54378f4..26c27dc5cb6 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1134,4 +1134,18 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCP=
RegInfo *ri)
     return ri->opc1 =3D=3D 4 || ri->opc1 =3D=3D 5;
 }
=20
+/*
+ * Temporary declarations of functions until the move to tlb_insn_helper.c
+ * is complete and we can make the functions static again
+ */
+CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
+                           bool isread);
+CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
+                             bool isread);
+bool tlb_force_broadcast(CPUARMState *env);
+void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                       uint64_t value);
+void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e37f459af35..2adedb94777 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1727,6 +1727,9 @@ static inline uint64_t pauth_ptr_mask(ARMVAParameters=
 param)
 /* Add the cpreg definitions for debug related system registers */
 void define_debug_regs(ARMCPU *cpu);
=20
+/* Add the cpreg definitions for TLBI instructions */
+void define_tlb_insn_regs(ARMCPU *cpu);
+
 /* Effective value of MDCR_EL2 */
 static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f38eb054c06..6a9bf70f185 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -366,8 +366,8 @@ static CPAccessResult access_tacr(CPUARMState *env, con=
st ARMCPRegInfo *ri,
 }
=20
 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
-static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  bool isread)
+CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
+                           bool isread)
 {
     if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))=
 {
         return CP_ACCESS_TRAP_EL2;
@@ -376,8 +376,8 @@ static CPAccessResult access_ttlb(CPUARMState *env, con=
st ARMCPRegInfo *ri,
 }
=20
 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
-static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    bool isread)
+CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
+                             bool isread)
 {
     if (arm_current_el(env) =3D=3D 1 &&
         (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
@@ -455,104 +455,16 @@ static int alle1_tlbmask(CPUARMState *env)
             ARMMMUIdxBit_Stage2_S);
 }
=20
-
-/* IS variants of TLB operations must affect all cores */
-static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_all_cpus_synced(cs);
-}
-
-static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_all_cpus_synced(cs);
-}
-
-static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
-}
-
-static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
-}
-
 /*
  * Non-IS variants of TLB operations are upgraded to
  * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
  * force broadcast of these operations.
  */
-static bool tlb_force_broadcast(CPUARMState *env)
+bool tlb_force_broadcast(CPUARMState *env)
 {
     return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB);
 }
=20
-static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                          uint64_t value)
-{
-    /* Invalidate all (TLBIALL) */
-    CPUState *cs =3D env_cpu(env);
-
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_all_cpus_synced(cs);
-    } else {
-        tlb_flush(cs);
-    }
-}
-
-static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                          uint64_t value)
-{
-    /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
-    CPUState *cs =3D env_cpu(env);
-
-    value &=3D TARGET_PAGE_MASK;
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_page_all_cpus_synced(cs, value);
-    } else {
-        tlb_flush_page(cs, value);
-    }
-}
-
-static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                           uint64_t value)
-{
-    /* Invalidate by ASID (TLBIASID) */
-    CPUState *cs =3D env_cpu(env);
-
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_all_cpus_synced(cs);
-    } else {
-        tlb_flush(cs);
-    }
-}
-
-static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                           uint64_t value)
-{
-    /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
-    CPUState *cs =3D env_cpu(env);
-
-    value &=3D TARGET_PAGE_MASK;
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_page_all_cpus_synced(cs, value);
-    } else {
-        tlb_flush_page(cs, value);
-    }
-}
-
 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
 {
@@ -586,8 +498,8 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
 }
=20
-static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                              uint64_t value)
+void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                       uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
@@ -595,8 +507,8 @@ static void tlbimva_hyp_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
 }
=20
-static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                 uint64_t value)
+void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
@@ -605,24 +517,6 @@ static void tlbimva_hyp_is_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
                                              ARMMMUIdxBit_E2);
 }
=20
-static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    uint64_t pageaddr =3D (value & MAKE_64BIT_MASK(0, 28)) << 12;
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
-}
-
-static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    uint64_t pageaddr =3D (value & MAKE_64BIT_MASK(0, 28)) << 12;
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_St=
age2);
-}
-
 static const ARMCPRegInfo cp_reginfo[] =3D {
     /*
      * Define the secure and non-secure FCSE identifier CP registers
@@ -732,22 +626,6 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D {
      */
     { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0=
, .opc2 =3D 0,
       .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
-    /*
-     * MMU TLB control. Note that the wildcarding means we cover not just
-     * the unified TLB ops but also the dside/iside/inner-shareable varian=
ts.
-     */
-    { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
-      .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia=
ll_write,
-      .type =3D ARM_CP_NO_RAW },
-    { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
-      .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim=
va_write,
-      .type =3D ARM_CP_NO_RAW },
-    { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
-      .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia=
sid_write,
-      .type =3D ARM_CP_NO_RAW },
-    { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
-      .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim=
vaa_write,
-      .type =3D ARM_CP_NO_RAW },
     { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2,
       .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP },
     { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2,
@@ -2331,55 +2209,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {
       .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0,
       .fgt =3D FGT_ISR_EL1,
       .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read },
-    /* 32 bit ITLB invalidates */
-    { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
5, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiall_write },
-    { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
5, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimva_write },
-    { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 5, .opc2 =3D 2,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiasid_write },
-    /* 32 bit DTLB invalidates */
-    { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
6, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiall_write },
-    { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
6, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimva_write },
-    { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 6, .opc2 =3D 2,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiasid_write },
-    /* 32 bit TLB invalidates */
-    { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiall_write },
-    { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimva_write },
-    { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 2,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbiasid_write },
-    { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 3,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimvaa_write },
-};
-
-static const ARMCPRegInfo v7mp_cp_reginfo[] =3D {
-    /* 32 bit TLB invalidates, Inner Shareable */
-    { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 3, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbiall_is_write },
-    { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 3, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbimva_is_write },
-    { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 2,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbiasid_is_write },
-    { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 3,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbimvaa_is_write },
 };
=20
 static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D {
@@ -5833,42 +5662,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {
       .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]),
       .writefn =3D par_write },
 #endif
-    /* TLB invalidate last level of translation table walk */
-    { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbimva_is_write },
-    { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 7,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
-      .writefn =3D tlbimvaa_is_write },
-    { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimva_write },
-    { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 7, .opc2 =3D 7,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
-      .writefn =3D tlbimvaa_write },
-    { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D=
 7, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbimva_hyp_write },
-    { .name =3D "TLBIMVALHIS",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbimva_hyp_is_write },
-    { .name =3D "TLBIIPAS2",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiipas2_hyp_write },
-    { .name =3D "TLBIIPAS2IS",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiipas2is_hyp_write },
-    { .name =3D "TLBIIPAS2L",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiipas2_hyp_write },
-    { .name =3D "TLBIIPAS2LIS",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiipas2is_hyp_write },
     /* 32 bit cache operations */
     { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D=
 1, .opc2 =3D 0,
       .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab =
},
@@ -8734,6 +8527,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
     }
=20
+    define_tlb_insn_regs(cpu);
+
     if (arm_feature(env, ARM_FEATURE_V6)) {
         /* The ID registers all have impdef reset values */
         ARMCPRegInfo v6_idregs[] =3D {
@@ -8839,10 +8634,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_V6K)) {
         define_arm_cp_regs(cpu, v6k_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_V7MP) &&
-        !arm_feature(env, ARM_FEATURE_PMSA)) {
-        define_arm_cp_regs(cpu, v7mp_cp_reginfo);
-    }
     if (arm_feature(env, ARM_FEATURE_V7VE)) {
         define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
     }
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
index 152b172e243..f3f45d54f28 100644
--- a/target/arm/tcg-stubs.c
+++ b/target/arm/tcg-stubs.c
@@ -25,3 +25,8 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, =
uint32_t syndrome,
 void assert_hflags_rebuild_correctly(CPUARMState *env)
 {
 }
+
+/* TLBI insns are only used by TCG, so we don't need to do anything for KV=
M */
+void define_tlb_insn_regs(ARMCPU *cpu)
+{
+}
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
new file mode 100644
index 00000000000..cdf23352d7a
--- /dev/null
+++ b/target/arm/tcg/tlb-insns.c
@@ -0,0 +1,246 @@
+/*
+ * Helpers for TLBI insns
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "exec/exec-all.h"
+#include "cpu.h"
+#include "internals.h"
+#include "cpu-features.h"
+#include "cpregs.h"
+
+/* IS variants of TLB operations must affect all cores */
+static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_all_cpus_synced(cs);
+}
+
+static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_all_cpus_synced(cs);
+}
+
+static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
+}
+
+static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
+}
+
+static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    /* Invalidate all (TLBIALL) */
+    CPUState *cs =3D env_cpu(env);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_all_cpus_synced(cs);
+    } else {
+        tlb_flush(cs);
+    }
+}
+
+static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
+    CPUState *cs =3D env_cpu(env);
+
+    value &=3D TARGET_PAGE_MASK;
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_page_all_cpus_synced(cs, value);
+    } else {
+        tlb_flush_page(cs, value);
+    }
+}
+
+static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    /* Invalidate by ASID (TLBIASID) */
+    CPUState *cs =3D env_cpu(env);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_all_cpus_synced(cs);
+    } else {
+        tlb_flush(cs);
+    }
+}
+
+static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
+    CPUState *cs =3D env_cpu(env);
+
+    value &=3D TARGET_PAGE_MASK;
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_page_all_cpus_synced(cs, value);
+    } else {
+        tlb_flush_page(cs, value);
+    }
+}
+
+static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    uint64_t pageaddr =3D (value & MAKE_64BIT_MASK(0, 28)) << 12;
+
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
+}
+
+static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    uint64_t pageaddr =3D (value & MAKE_64BIT_MASK(0, 28)) << 12;
+
+    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_St=
age2);
+}
+
+static const ARMCPRegInfo tlbi_not_v7_cp_reginfo[] =3D {
+    /*
+     * MMU TLB control. Note that the wildcarding means we cover not just
+     * the unified TLB ops but also the dside/iside/inner-shareable varian=
ts.
+     */
+    { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
+      .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia=
ll_write,
+      .type =3D ARM_CP_NO_RAW },
+    { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
+      .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim=
va_write,
+      .type =3D ARM_CP_NO_RAW },
+    { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
+      .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia=
sid_write,
+      .type =3D ARM_CP_NO_RAW },
+    { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY,
+      .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim=
vaa_write,
+      .type =3D ARM_CP_NO_RAW },
+};
+
+static const ARMCPRegInfo tlbi_v7_cp_reginfo[] =3D {
+    /* 32 bit ITLB invalidates */
+    { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
5, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiall_write },
+    { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
5, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimva_write },
+    { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 5, .opc2 =3D 2,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiasid_write },
+    /* 32 bit DTLB invalidates */
+    { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
6, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiall_write },
+    { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
6, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimva_write },
+    { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 6, .opc2 =3D 2,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiasid_write },
+    /* 32 bit TLB invalidates */
+    { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiall_write },
+    { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimva_write },
+    { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 2,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbiasid_write },
+    { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 3,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimvaa_write },
+};
+
+static const ARMCPRegInfo tlbi_v7mp_cp_reginfo[] =3D {
+    /* 32 bit TLB invalidates, Inner Shareable */
+    { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 3, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbiall_is_write },
+    { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 3, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbimva_is_write },
+    { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 2,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbiasid_is_write },
+    { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 3,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbimvaa_is_write },
+};
+
+static const ARMCPRegInfo tlbi_v8_cp_reginfo[] =3D {
+    /* AArch32 TLB invalidate last level of translation table walk */
+    { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbimva_is_write },
+    { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 7,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
bis,
+      .writefn =3D tlbimvaa_is_write },
+    { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D =
7, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimva_write },
+    { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D=
 7, .opc2 =3D 7,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl=
b,
+      .writefn =3D tlbimvaa_write },
+    { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D=
 7, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbimva_hyp_write },
+    { .name =3D "TLBIMVALHIS",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbimva_hyp_is_write },
+    { .name =3D "TLBIIPAS2",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiipas2_hyp_write },
+    { .name =3D "TLBIIPAS2IS",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiipas2is_hyp_write },
+    { .name =3D "TLBIIPAS2L",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiipas2_hyp_write },
+    { .name =3D "TLBIIPAS2LIS",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiipas2is_hyp_write },
+};
+
+void define_tlb_insn_regs(ARMCPU *cpu)
+{
+    CPUARMState *env =3D &cpu->env;
+
+    if (!arm_feature(env, ARM_FEATURE_V7)) {
+        define_arm_cp_regs(cpu, tlbi_not_v7_cp_reginfo);
+    } else {
+        define_arm_cp_regs(cpu, tlbi_v7_cp_reginfo);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7MP) &&
+        !arm_feature(env, ARM_FEATURE_PMSA)) {
+        define_arm_cp_regs(cpu, tlbi_v7mp_cp_reginfo);
+    }
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        define_arm_cp_regs(cpu, tlbi_v8_cp_reginfo);
+    }
+}
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 508932a249f..09238989c5a 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -39,6 +39,7 @@ arm_ss.add(files(
   'op_helper.c',
   'tlb_helper.c',
   'vec_helper.c',
+  'tlb-insns.c',
 ))
=20
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 02/10] target/arm: Move TLBI insns for AArch32 EL2 to
 tlbi_insn_helper.c
Date: Tue, 10 Dec 2024 16:04:44 +0000
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Move the AArch32 TLBI insns for AArch32 EL2 to tlbi_insn_helper.c.
To keep this as an obviously pure code-movement, we retain the
same condition for registering tlbi_el2_cp_reginfo that we use for
el2_cp_reginfo. We'll be able to simplify this condition later,
since the need to define the reginfo for EL3-without-EL2 doesn't
apply for the TLBI ops specifically.

This move brings all the uses of tlbimva_hyp_write() and
tlbimva_hyp_is_write() back into a single file, so we can move those
also, and make them file-local again.

The helper alle1_tlbmask() is an exception to the pattern that we
only need to make these functions global temporarily, because once
this refactoring is complete it will be called by both code in
helper.c (vttbr_write()) and by code in tlb-insns.c.  We therefore
put its prototype in a permanent home in internals.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  4 --
 target/arm/internals.h     |  6 +++
 target/arm/helper.c        | 74 +--------------------------------
 target/arm/tcg/tlb-insns.c | 85 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 92 insertions(+), 77 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 26c27dc5cb6..851cd045b2c 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1143,9 +1143,5 @@ CPAccessResult access_ttlb(CPUARMState *env, const AR=
MCPRegInfo *ri,
 CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
                              bool isread);
 bool tlb_force_broadcast(CPUARMState *env);
-void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                       uint64_t value);
-void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                          uint64_t value);
=20
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 2adedb94777..c3a5b1385f1 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1820,4 +1820,10 @@ uint64_t gt_get_countervalue(CPUARMState *env);
  * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
  */
 uint64_t gt_virt_cnt_offset(CPUARMState *env);
+
+/*
+ * Return mask of ARMMMUIdxBit values corresponding to an "invalidate
+ * all EL1" scope; this covers stage 1 and stage 2.
+ */
+int alle1_tlbmask(CPUARMState *env);
 #endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6a9bf70f185..3c69225e1d9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -438,7 +438,7 @@ static void contextidr_write(CPUARMState *env, const AR=
MCPRegInfo *ri,
     raw_write(env, ri, value);
 }
=20
-static int alle1_tlbmask(CPUARMState *env)
+int alle1_tlbmask(CPUARMState *env)
 {
     /*
      * Note that the 'ALL' scope must invalidate both stage 1 and
@@ -465,58 +465,6 @@ bool tlb_force_broadcast(CPUARMState *env)
     return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB);
 }
=20
-static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
-}
-
-static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));
-}
-
-
-static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                              uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
-}
-
-static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                 uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
-}
-
-void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                       uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
-}
-
-void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                          uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             ARMMMUIdxBit_E2);
-}
-
 static const ARMCPRegInfo cp_reginfo[] =3D {
     /*
      * Define the secure and non-secure FCSE identifier CP registers
@@ -6248,26 +6196,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D {
     { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2,
       .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS,
       .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) },
-    { .name =3D "TLBIALLNSNH",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiall_nsnh_write },
-    { .name =3D "TLBIALLNSNHIS",
-      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiall_nsnh_is_write },
-    { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D =
7, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiall_hyp_write },
-    { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 0,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbiall_hyp_is_write },
-    { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D =
7, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbimva_hyp_write },
-    { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 1,
-      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
-      .writefn =3D tlbimva_hyp_is_write },
     { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64,
       .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
       .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index cdf23352d7a..66096093dcc 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -99,6 +99,25 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCP=
RegInfo *ri,
     }
 }
=20
+static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
+
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+}
+
+static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12);
+
+    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
+                                             ARMMMUIdxBit_E2);
+}
+
 static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                 uint64_t value)
 {
@@ -117,6 +136,39 @@ static void tlbiipas2is_hyp_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_St=
age2);
 }
=20
+static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                               uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
+}
+
+static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));
+}
+
+
+static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+}
+
+static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+}
+
 static const ARMCPRegInfo tlbi_not_v7_cp_reginfo[] =3D {
     /*
      * MMU TLB control. Note that the wildcarding means we cover not just
@@ -227,6 +279,29 @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] =3D {
       .writefn =3D tlbiipas2is_hyp_write },
 };
=20
+static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D {
+    { .name =3D "TLBIALLNSNH",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiall_nsnh_write },
+    { .name =3D "TLBIALLNSNHIS",
+      .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiall_nsnh_is_write },
+    { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D =
7, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiall_hyp_write },
+    { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 0,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbiall_hyp_is_write },
+    { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D =
7, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbimva_hyp_write },
+    { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 1,
+      .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
+      .writefn =3D tlbimva_hyp_is_write },
+};
+
 void define_tlb_insn_regs(ARMCPU *cpu)
 {
     CPUARMState *env =3D &cpu->env;
@@ -243,4 +318,14 @@ void define_tlb_insn_regs(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_V8)) {
         define_arm_cp_regs(cpu, tlbi_v8_cp_reginfo);
     }
+    /*
+     * We retain the existing logic for when to register these TLBI
+     * ops (i.e. matching the condition for el2_cp_reginfo[] in
+     * helper.c), but we will be able to simplify this later.
+     */
+    if (arm_feature(env, ARM_FEATURE_EL2)
+        || (arm_feature(env, ARM_FEATURE_EL3)
+            && arm_feature(env, ARM_FEATURE_V8))) {
+        define_arm_cp_regs(cpu, tlbi_el2_cp_reginfo);
+    }
 }
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 03/10] target/arm: Move AArch64 TLBI insns from
 v8_cp_reginfo[]
Date: Tue, 10 Dec 2024 16:04:45 +0000
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Move the AArch64 TLBI insns that are declared in v8_cp_reginfo[]
into tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  11 +++
 target/arm/helper.c        | 182 +++----------------------------------
 target/arm/tcg/tlb-insns.c | 160 ++++++++++++++++++++++++++++++++
 3 files changed, 182 insertions(+), 171 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 851cd045b2c..a14f5bb6c98 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1143,5 +1143,16 @@ CPAccessResult access_ttlb(CPUARMState *env, const A=
RMCPRegInfo *ri,
 CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
                              bool isread);
 bool tlb_force_broadcast(CPUARMState *env);
+int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
+                       uint64_t addr);
+int vae1_tlbbits(CPUARMState *env, uint64_t addr);
+int vae1_tlbmask(CPUARMState *env);
+int ipas2e1_tlbmask(CPUARMState *env, int64_t value);
+void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                               uint64_t value);
+void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value);
+void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                            uint64_t value);
=20
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3c69225e1d9..cc7da7f1159 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4685,7 +4685,7 @@ static CPAccessResult access_tocu(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
  * Page D4-1736 (DDI0487A.b)
  */
=20
-static int vae1_tlbmask(CPUARMState *env)
+int vae1_tlbmask(CPUARMState *env)
 {
     uint64_t hcr =3D arm_hcr_el2_eff(env);
     uint16_t mask;
@@ -4721,8 +4721,8 @@ static int vae2_tlbmask(CPUARMState *env)
 }
=20
 /* Return 56 if TBI is enabled, 64 otherwise. */
-static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
-                              uint64_t addr)
+int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
+                       uint64_t addr)
 {
     uint64_t tcr =3D regime_tcr(env, mmu_idx);
     int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx);
@@ -4731,7 +4731,7 @@ static int tlbbits_for_regime(CPUARMState *env, ARMMM=
UIdx mmu_idx,
     return (tbi >> select) & 1 ? 56 : 64;
 }
=20
-static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
+int vae1_tlbbits(CPUARMState *env, uint64_t addr)
 {
     uint64_t hcr =3D arm_hcr_el2_eff(env);
     ARMMMUIdx mmu_idx;
@@ -4767,8 +4767,8 @@ static int vae2_tlbbits(CPUARMState *env, uint64_t ad=
dr)
     return tlbbits_for_regime(env, mmu_idx, addr);
 }
=20
-static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo=
 *ri,
-                                      uint64_t value)
+void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                               uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     int mask =3D vae1_tlbmask(env);
@@ -4776,19 +4776,6 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *e=
nv, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
 }
=20
-static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae1_tlbmask(env);
-
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
-    } else {
-        tlb_flush_by_mmuidx(cs, mask);
-    }
-}
-
 static int e2_tlbmask(CPUARMState *env)
 {
     return (ARMMMUIdxBit_E20_0 |
@@ -4797,15 +4784,6 @@ static int e2_tlbmask(CPUARMState *env)
             ARMMMUIdxBit_E2);
 }
=20
-static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D alle1_tlbmask(env);
-
-    tlb_flush_by_mmuidx(cs, mask);
-}
-
 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                   uint64_t value)
 {
@@ -4824,8 +4802,8 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c=
onst ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
 }
=20
-static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
+void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     int mask =3D alle1_tlbmask(env);
@@ -4881,8 +4859,8 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
 }
=20
-static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
-                                   uint64_t value)
+void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                            uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     int mask =3D vae1_tlbmask(env);
@@ -4892,27 +4870,6 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env,=
 const ARMCPRegInfo *ri,
     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
 }
=20
-static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                 uint64_t value)
-{
-    /*
-     * Invalidate by VA, EL1&0 (AArch64 version).
-     * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
-     * since we don't support flush-for-specific-ASID-only or
-     * flush-last-level-only.
-     */
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae1_tlbmask(env);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-    int bits =3D vae1_tlbbits(env, pageaddr);
-
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, =
bits);
-    } else {
-        tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
-    }
-}
-
 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
                                    uint64_t value)
 {
@@ -4935,7 +4892,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
                                                   ARMMMUIdxBit_E3, bits);
 }
=20
-static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
+int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
 {
     /*
      * The MSB of value is the NS field, which only applies if SEL2
@@ -4948,30 +4905,6 @@ static int ipas2e1_tlbmask(CPUARMState *env, int64_t=
 value)
             : ARMMMUIdxBit_Stage2);
 }
=20
-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D ipas2e1_tlbmask(env, value);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-
-    if (tlb_force_broadcast(env)) {
-        tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
-    } else {
-        tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
-    }
-}
-
-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo=
 *ri,
-                                      uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D ipas2e1_tlbmask(env, value);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
-}
-
 #ifdef TARGET_AARCH64
 typedef struct {
     uint64_t base;
@@ -5462,99 +5395,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {
       .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2,
       .fgt =3D FGT_DCCISW,
       .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP },
-    /* TLBI operations */
-    { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVMALLE1IS,
-      .writefn =3D tlbi_aa64_vmalle1is_write },
-    { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVAE1IS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIASIDE1IS,
-      .writefn =3D tlbi_aa64_vmalle1is_write },
-    { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVAAE1IS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVALE1IS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVAALE1IS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIVMALLE1,
-      .writefn =3D tlbi_aa64_vmalle1_write },
-    { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIVAE1,
-      .writefn =3D tlbi_aa64_vae1_write },
-    { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIASIDE1,
-      .writefn =3D tlbi_aa64_vmalle1_write },
-    { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIVAAE1,
-      .writefn =3D tlbi_aa64_vae1_write },
-    { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIVALE1,
-      .writefn =3D tlbi_aa64_vae1_write },
-    { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIVAALE1,
-      .writefn =3D tlbi_aa64_vae1_write },
-    { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ipas2e1is_write },
-    { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ipas2e1is_write },
-    { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1is_write },
-    { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1is_write },
-    { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ipas2e1_write },
-    { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ipas2e1_write },
-    { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1_write },
-    { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1is_write },
 #ifndef CONFIG_USER_ONLY
     /* 64 bit address translation operations */
     { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64,
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 66096093dcc..ff7698e31b6 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -169,6 +169,73 @@ static void tlbiall_hyp_is_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
 }
=20
+static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae1_tlbmask(env);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+    } else {
+        tlb_flush_by_mmuidx(cs, mask);
+    }
+}
+
+static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D alle1_tlbmask(env);
+
+    tlb_flush_by_mmuidx(cs, mask);
+}
+
+static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 uint64_t value)
+{
+    /*
+     * Invalidate by VA, EL1&0 (AArch64 version).
+     * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
+     * since we don't support flush-for-specific-ASID-only or
+     * flush-last-level-only.
+     */
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae1_tlbmask(env);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+    int bits =3D vae1_tlbbits(env, pageaddr);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, =
bits);
+    } else {
+        tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
+    }
+}
+
+static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D ipas2e1_tlbmask(env, value);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+
+    if (tlb_force_broadcast(env)) {
+        tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+    } else {
+        tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
+    }
+}
+
+static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo=
 *ri,
+                                      uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D ipas2e1_tlbmask(env, value);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+
+    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+}
+
 static const ARMCPRegInfo tlbi_not_v7_cp_reginfo[] =3D {
     /*
      * MMU TLB control. Note that the wildcarding means we cover not just
@@ -277,6 +344,99 @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] =3D {
       .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
       .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
       .writefn =3D tlbiipas2is_hyp_write },
+    /* AArch64 TLBI operations */
+    { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVMALLE1IS,
+      .writefn =3D tlbi_aa64_vmalle1is_write },
+    { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVAE1IS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIASIDE1IS,
+      .writefn =3D tlbi_aa64_vmalle1is_write },
+    { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVAAE1IS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVALE1IS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVAALE1IS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIVMALLE1,
+      .writefn =3D tlbi_aa64_vmalle1_write },
+    { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIVAE1,
+      .writefn =3D tlbi_aa64_vae1_write },
+    { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIASIDE1,
+      .writefn =3D tlbi_aa64_vmalle1_write },
+    { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIVAAE1,
+      .writefn =3D tlbi_aa64_vae1_write },
+    { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIVALE1,
+      .writefn =3D tlbi_aa64_vae1_write },
+    { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIVAALE1,
+      .writefn =3D tlbi_aa64_vae1_write },
+    { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ipas2e1is_write },
+    { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ipas2e1is_write },
+    { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1is_write },
+    { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1is_write },
+    { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ipas2e1_write },
+    { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ipas2e1_write },
+    { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1_write },
+    { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1is_write },
 };
=20
 static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D {
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 04/10] target/arm: Move the AArch64 EL2 TLBI insns
Date: Tue, 10 Dec 2024 16:04:46 +0000
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Content-Type: text/plain; charset="utf-8"

Move the AArch64 EL2 TLBI insn definitions that were
in el2_cp_reginfo[] across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  7 +++++
 target/arm/helper.c        | 61 ++++----------------------------------
 target/arm/tcg/tlb-insns.c | 49 ++++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 55 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index a14f5bb6c98..57446ae1b52 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1146,13 +1146,20 @@ bool tlb_force_broadcast(CPUARMState *env);
 int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
                        uint64_t addr);
 int vae1_tlbbits(CPUARMState *env, uint64_t addr);
+int vae2_tlbbits(CPUARMState *env, uint64_t addr);
 int vae1_tlbmask(CPUARMState *env);
+int vae2_tlbmask(CPUARMState *env);
 int ipas2e1_tlbmask(CPUARMState *env, int64_t value);
+int e2_tlbmask(CPUARMState *env);
 void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value);
 void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value);
 void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value);
+void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value);
+void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                            uint64_t value);
=20
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cc7da7f1159..6942d2f2fb3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4705,7 +4705,7 @@ int vae1_tlbmask(CPUARMState *env)
     return mask;
 }
=20
-static int vae2_tlbmask(CPUARMState *env)
+int vae2_tlbmask(CPUARMState *env)
 {
     uint64_t hcr =3D arm_hcr_el2_eff(env);
     uint16_t mask;
@@ -4748,7 +4748,7 @@ int vae1_tlbbits(CPUARMState *env, uint64_t addr)
     return tlbbits_for_regime(env, mmu_idx, addr);
 }
=20
-static int vae2_tlbbits(CPUARMState *env, uint64_t addr)
+int vae2_tlbbits(CPUARMState *env, uint64_t addr)
 {
     uint64_t hcr =3D arm_hcr_el2_eff(env);
     ARMMMUIdx mmu_idx;
@@ -4776,7 +4776,7 @@ void tlbi_aa64_vmalle1is_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
 }
=20
-static int e2_tlbmask(CPUARMState *env)
+int e2_tlbmask(CPUARMState *env)
 {
     return (ARMMMUIdxBit_E20_0 |
             ARMMMUIdxBit_E20_2 |
@@ -4784,15 +4784,6 @@ static int e2_tlbmask(CPUARMState *env)
             ARMMMUIdxBit_E2);
 }
=20
-static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D e2_tlbmask(env);
-
-    tlb_flush_by_mmuidx(cs, mask);
-}
-
 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                   uint64_t value)
 {
@@ -4811,8 +4802,8 @@ void tlbi_aa64_alle1is_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
 }
=20
-static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
+void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     int mask =3D e2_tlbmask(env);
@@ -4828,22 +4819,6 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env=
, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
 }
=20
-static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                 uint64_t value)
-{
-    /*
-     * Invalidate by VA, EL2
-     * Currently handles both VAE2 and VALE2, since we don't support
-     * flush-last-level-only.
-     */
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae2_tlbmask(env);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-    int bits =3D vae2_tlbbits(env, pageaddr);
-
-    tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
-}
-
 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -4870,7 +4845,7 @@ void tlbi_aa64_vae1is_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
 }
=20
-static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
+void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                    uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
@@ -6036,30 +6011,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D {
     { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2,
       .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS,
       .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) },
-    { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_alle2_write },
-    { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2_write },
-    { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2_write },
-    { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_alle2is_write },
-    { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2is_write },
-    { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
     /*
      * Unlike the other EL2-related AT operations, these must
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index ff7698e31b6..1eebb6055ce 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -191,6 +191,31 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs, mask);
 }
=20
+static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D e2_tlbmask(env);
+
+    tlb_flush_by_mmuidx(cs, mask);
+}
+
+static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 uint64_t value)
+{
+    /*
+     * Invalidate by VA, EL2
+     * Currently handles both VAE2 and VALE2, since we don't support
+     * flush-last-level-only.
+     */
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae2_tlbmask(env);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+    int bits =3D vae2_tlbbits(env, pageaddr);
+
+    tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
+}
+
 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -460,6 +485,30 @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D {
     { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =
=3D 3, .opc2 =3D 1,
       .type =3D ARM_CP_NO_RAW, .access =3D PL2_W,
       .writefn =3D tlbimva_hyp_is_write },
+    { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_alle2_write },
+    { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2_write },
+    { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2_write },
+    { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_alle2is_write },
+    { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2is_write },
+    { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2is_write },
 };
=20
 void define_tlb_insn_regs(ARMCPU *cpu)
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 05/10] target/arm: Move AArch64 EL3 TLBI insns
Date: Tue, 10 Dec 2024 16:04:47 +0000
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Move the AArch64 EL3 TLBI insns from el3_cp_reginfo[] across
to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  4 +++
 target/arm/helper.c        | 56 +++-----------------------------------
 target/arm/tcg/tlb-insns.c | 54 ++++++++++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 52 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 57446ae1b52..722ac5bb884 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1161,5 +1161,9 @@ void tlbi_aa64_alle2is_write(CPUARMState *env, const =
ARMCPRegInfo *ri,
                              uint64_t value);
 void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value);
+void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                            uint64_t value);
+void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value);
=20
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6942d2f2fb3..baeabb5ec73 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4784,15 +4784,6 @@ int e2_tlbmask(CPUARMState *env)
             ARMMMUIdxBit_E2);
 }
=20
-static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    ARMCPU *cpu =3D env_archcpu(env);
-    CPUState *cs =3D CPU(cpu);
-
-    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
-}
-
 void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value)
 {
@@ -4811,29 +4802,14 @@ void tlbi_aa64_alle2is_write(CPUARMState *env, cons=
t ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
 }
=20
-static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
+void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                             uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
=20
     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
 }
=20
-static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                 uint64_t value)
-{
-    /*
-     * Invalidate by VA, EL3
-     * Currently handles both VAE3 and VALE3, since we don't support
-     * flush-last-level-only.
-     */
-    ARMCPU *cpu =3D env_archcpu(env);
-    CPUState *cs =3D CPU(cpu);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
-}
-
 void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
 {
@@ -4856,8 +4832,8 @@ void tlbi_aa64_vae2is_write(CPUARMState *env, const A=
RMCPRegInfo *ri,
     tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
 }
=20
-static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
-                                   uint64_t value)
+void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                            uint64_t value)
 {
     CPUState *cs =3D env_cpu(env);
     uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
@@ -6223,30 +6199,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D {
       .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1,
       .access =3D PL3_RW, .type =3D ARM_CP_CONST,
       .resetvalue =3D 0 },
-    { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle3is_write },
-    { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3is_write },
-    { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3is_write },
-    { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle3_write },
-    { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3_write },
-    { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3_write },
 };
=20
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 1eebb6055ce..528265404de 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -200,6 +200,15 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs, mask);
 }
=20
+static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    ARMCPU *cpu =3D env_archcpu(env);
+    CPUState *cs =3D CPU(cpu);
+
+    tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
+}
+
 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -216,6 +225,21 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
     tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
 }
=20
+static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 uint64_t value)
+{
+    /*
+     * Invalidate by VA, EL3
+     * Currently handles both VAE3 and VALE3, since we don't support
+     * flush-last-level-only.
+     */
+    ARMCPU *cpu =3D env_archcpu(env);
+    CPUState *cs =3D CPU(cpu);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+
+    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
+}
+
 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -511,6 +535,33 @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] =3D {
       .writefn =3D tlbi_aa64_vae2is_write },
 };
=20
+static const ARMCPRegInfo tlbi_el3_cp_reginfo[] =3D {
+    { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle3is_write },
+    { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3is_write },
+    { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3is_write },
+    { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle3_write },
+    { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3_write },
+    { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3_write },
+};
+
 void define_tlb_insn_regs(ARMCPU *cpu)
 {
     CPUARMState *env =3D &cpu->env;
@@ -537,4 +588,7 @@ void define_tlb_insn_regs(ARMCPU *cpu)
             && arm_feature(env, ARM_FEATURE_V8))) {
         define_arm_cp_regs(cpu, tlbi_el2_cp_reginfo);
     }
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo);
+    }
 }
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 06/10] target/arm: Move TLBI range insns
Date: Tue, 10 Dec 2024 16:04:48 +0000
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Move the TLBI invalidate-range insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |   2 +
 target/arm/helper.c        | 330 +------------------------------------
 target/arm/tcg/tlb-insns.c | 329 ++++++++++++++++++++++++++++++++++++
 3 files changed, 333 insertions(+), 328 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 722ac5bb884..fe838bcfd97 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1142,6 +1142,8 @@ CPAccessResult access_ttlb(CPUARMState *env, const AR=
MCPRegInfo *ri,
                            bool isread);
 CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
                              bool isread);
+CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
+                             bool isread);
 bool tlb_force_broadcast(CPUARMState *env);
 int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
                        uint64_t addr);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index baeabb5ec73..376aa9aecd5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -388,8 +388,8 @@ CPAccessResult access_ttlbis(CPUARMState *env, const AR=
MCPRegInfo *ri,
=20
 #ifdef TARGET_AARCH64
 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
-static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    bool isread)
+CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
+                             bool isread)
 {
     if (arm_current_el(env) =3D=3D 1 &&
         (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
@@ -4856,202 +4856,6 @@ int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
             : ARMMMUIdxBit_Stage2);
 }
=20
-#ifdef TARGET_AARCH64
-typedef struct {
-    uint64_t base;
-    uint64_t length;
-} TLBIRange;
-
-static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
-{
-    /*
-     * Note that the TLBI range TG field encoding differs from both
-     * TG0 and TG1 encodings.
-     */
-    switch (tg) {
-    case 1:
-        return Gran4K;
-    case 2:
-        return Gran16K;
-    case 3:
-        return Gran64K;
-    default:
-        return GranInvalid;
-    }
-}
-
-static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
-                                     uint64_t value)
-{
-    unsigned int page_size_granule, page_shift, num, scale, exponent;
-    /* Extract one bit to represent the va selector in use. */
-    uint64_t select =3D sextract64(value, 36, 1);
-    ARMVAParameters param =3D aa64_va_parameters(env, select, mmuidx, true=
, false);
-    TLBIRange ret =3D { };
-    ARMGranuleSize gran;
-
-    page_size_granule =3D extract64(value, 46, 2);
-    gran =3D tlbi_range_tg_to_gran_size(page_size_granule);
-
-    /* The granule encoded in value must match the granule in use. */
-    if (gran !=3D param.gran) {
-        qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\=
n",
-                      page_size_granule);
-        return ret;
-    }
-
-    page_shift =3D arm_granule_bits(gran);
-    num =3D extract64(value, 39, 5);
-    scale =3D extract64(value, 44, 2);
-    exponent =3D (5 * scale) + 1;
-
-    ret.length =3D (num + 1) << (exponent + page_shift);
-
-    if (param.select) {
-        ret.base =3D sextract64(value, 0, 37);
-    } else {
-        ret.base =3D extract64(value, 0, 37);
-    }
-    if (param.ds) {
-        /*
-         * With DS=3D1, BaseADDR is always shifted 16 so that it is able
-         * to address all 52 va bits.  The input address is perforce
-         * aligned on a 64k boundary regardless of translation granule.
-         */
-        page_shift =3D 16;
-    }
-    ret.base <<=3D page_shift;
-
-    return ret;
-}
-
-static void do_rvae_write(CPUARMState *env, uint64_t value,
-                          int idxmap, bool synced)
-{
-    ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap);
-    TLBIRange range;
-    int bits;
-
-    range =3D tlbi_aa64_get_range(env, one_idx, value);
-    bits =3D tlbbits_for_regime(env, one_idx, range.base);
-
-    if (synced) {
-        tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
-                                                  range.base,
-                                                  range.length,
-                                                  idxmap,
-                                                  bits);
-    } else {
-        tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
-                                  range.length, idxmap, bits);
-    }
-}
-
-static void tlbi_aa64_rvae1_write(CPUARMState *env,
-                                  const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    /*
-     * Invalidate by VA range, EL1&0.
-     * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
-     * since we don't support flush-for-specific-ASID-only or
-     * flush-last-level-only.
-     */
-
-    do_rvae_write(env, value, vae1_tlbmask(env),
-                  tlb_force_broadcast(env));
-}
-
-static void tlbi_aa64_rvae1is_write(CPUARMState *env,
-                                    const ARMCPRegInfo *ri,
-                                    uint64_t value)
-{
-    /*
-     * Invalidate by VA range, Inner/Outer Shareable EL1&0.
-     * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
-     * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
-     * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
-     * shareable specific flushes.
-     */
-
-    do_rvae_write(env, value, vae1_tlbmask(env), true);
-}
-
-static void tlbi_aa64_rvae2_write(CPUARMState *env,
-                                  const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    /*
-     * Invalidate by VA range, EL2.
-     * Currently handles all of RVAE2 and RVALE2,
-     * since we don't support flush-for-specific-ASID-only or
-     * flush-last-level-only.
-     */
-
-    do_rvae_write(env, value, vae2_tlbmask(env),
-                  tlb_force_broadcast(env));
-
-
-}
-
-static void tlbi_aa64_rvae2is_write(CPUARMState *env,
-                                    const ARMCPRegInfo *ri,
-                                    uint64_t value)
-{
-    /*
-     * Invalidate by VA range, Inner/Outer Shareable, EL2.
-     * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
-     * since we don't support flush-for-specific-ASID-only,
-     * flush-last-level-only or inner/outer shareable specific flushes.
-     */
-
-    do_rvae_write(env, value, vae2_tlbmask(env), true);
-
-}
-
-static void tlbi_aa64_rvae3_write(CPUARMState *env,
-                                  const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    /*
-     * Invalidate by VA range, EL3.
-     * Currently handles all of RVAE3 and RVALE3,
-     * since we don't support flush-for-specific-ASID-only or
-     * flush-last-level-only.
-     */
-
-    do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env));
-}
-
-static void tlbi_aa64_rvae3is_write(CPUARMState *env,
-                                    const ARMCPRegInfo *ri,
-                                    uint64_t value)
-{
-    /*
-     * Invalidate by VA range, EL3, Inner/Outer Shareable.
-     * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
-     * since we don't support flush-for-specific-ASID-only,
-     * flush-last-level-only or inner/outer specific flushes.
-     */
-
-    do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
-}
-
-static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
-                                     uint64_t value)
-{
-    do_rvae_write(env, value, ipas2e1_tlbmask(env, value),
-                  tlb_force_broadcast(env));
-}
-
-static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
-                                       const ARMCPRegInfo *ri,
-                                       uint64_t value)
-{
-    do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true);
-}
-#endif
-
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo=
 *ri,
                                       bool isread)
 {
@@ -7312,133 +7116,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D {
       .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) },
 };
=20
-static const ARMCPRegInfo tlbirange_reginfo[] =3D {
-    { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAE1IS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAAE1IS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-   { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVALE1IS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAALE1IS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAE1OS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAAE1OS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-   { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVALE1OS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIRVAALE1OS,
-      .writefn =3D tlbi_aa64_rvae1is_write },
-    { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIRVAE1,
-      .writefn =3D tlbi_aa64_rvae1_write },
-    { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIRVAAE1,
-      .writefn =3D tlbi_aa64_rvae1_write },
-   { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIRVALE1,
-      .writefn =3D tlbi_aa64_rvae1_write },
-    { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
-      .fgt =3D FGT_TLBIRVAALE1,
-      .writefn =3D tlbi_aa64_rvae1_write },
-    { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ripas2e1is_write },
-    { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ripas2e1is_write },
-    { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2is_write },
-   { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2is_write },
-    { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ripas2e1_write },
-    { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_ripas2e1_write },
-   { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2is_write },
-   { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2is_write },
-    { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2_write },
-   { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_rvae2_write },
-   { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3is_write },
-   { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3is_write },
-   { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3is_write },
-   { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3is_write },
-   { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3_write },
-   { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_rvae3_write },
-};
-
 static const ARMCPRegInfo tlbios_reginfo[] =3D {
     { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64,
       .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
@@ -9389,9 +9066,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_rndr, cpu)) {
         define_arm_cp_regs(cpu, rndr_reginfo);
     }
-    if (cpu_isar_feature(aa64_tlbirange, cpu)) {
-        define_arm_cp_regs(cpu, tlbirange_reginfo);
-    }
     if (cpu_isar_feature(aa64_tlbios, cpu)) {
         define_arm_cp_regs(cpu, tlbios_reginfo);
     }
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 528265404de..a273c6f4b58 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -6,6 +6,7 @@
  * SPDX-License-Identifier: GPL-2.0-or-later
  */
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "exec/exec-all.h"
 #include "cpu.h"
 #include "internals.h"
@@ -562,6 +563,329 @@ static const ARMCPRegInfo tlbi_el3_cp_reginfo[] =3D {
       .writefn =3D tlbi_aa64_vae3_write },
 };
=20
+#ifdef TARGET_AARCH64
+typedef struct {
+    uint64_t base;
+    uint64_t length;
+} TLBIRange;
+
+static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
+{
+    /*
+     * Note that the TLBI range TG field encoding differs from both
+     * TG0 and TG1 encodings.
+     */
+    switch (tg) {
+    case 1:
+        return Gran4K;
+    case 2:
+        return Gran16K;
+    case 3:
+        return Gran64K;
+    default:
+        return GranInvalid;
+    }
+}
+
+static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
+                                     uint64_t value)
+{
+    unsigned int page_size_granule, page_shift, num, scale, exponent;
+    /* Extract one bit to represent the va selector in use. */
+    uint64_t select =3D sextract64(value, 36, 1);
+    ARMVAParameters param =3D aa64_va_parameters(env, select, mmuidx, true=
, false);
+    TLBIRange ret =3D { };
+    ARMGranuleSize gran;
+
+    page_size_granule =3D extract64(value, 46, 2);
+    gran =3D tlbi_range_tg_to_gran_size(page_size_granule);
+
+    /* The granule encoded in value must match the granule in use. */
+    if (gran !=3D param.gran) {
+        qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\=
n",
+                      page_size_granule);
+        return ret;
+    }
+
+    page_shift =3D arm_granule_bits(gran);
+    num =3D extract64(value, 39, 5);
+    scale =3D extract64(value, 44, 2);
+    exponent =3D (5 * scale) + 1;
+
+    ret.length =3D (num + 1) << (exponent + page_shift);
+
+    if (param.select) {
+        ret.base =3D sextract64(value, 0, 37);
+    } else {
+        ret.base =3D extract64(value, 0, 37);
+    }
+    if (param.ds) {
+        /*
+         * With DS=3D1, BaseADDR is always shifted 16 so that it is able
+         * to address all 52 va bits.  The input address is perforce
+         * aligned on a 64k boundary regardless of translation granule.
+         */
+        page_shift =3D 16;
+    }
+    ret.base <<=3D page_shift;
+
+    return ret;
+}
+
+static void do_rvae_write(CPUARMState *env, uint64_t value,
+                          int idxmap, bool synced)
+{
+    ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap);
+    TLBIRange range;
+    int bits;
+
+    range =3D tlbi_aa64_get_range(env, one_idx, value);
+    bits =3D tlbbits_for_regime(env, one_idx, range.base);
+
+    if (synced) {
+        tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
+                                                  range.base,
+                                                  range.length,
+                                                  idxmap,
+                                                  bits);
+    } else {
+        tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
+                                  range.length, idxmap, bits);
+    }
+}
+
+static void tlbi_aa64_rvae1_write(CPUARMState *env,
+                                  const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    /*
+     * Invalidate by VA range, EL1&0.
+     * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
+     * since we don't support flush-for-specific-ASID-only or
+     * flush-last-level-only.
+     */
+
+    do_rvae_write(env, value, vae1_tlbmask(env),
+                  tlb_force_broadcast(env));
+}
+
+static void tlbi_aa64_rvae1is_write(CPUARMState *env,
+                                    const ARMCPRegInfo *ri,
+                                    uint64_t value)
+{
+    /*
+     * Invalidate by VA range, Inner/Outer Shareable EL1&0.
+     * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
+     * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
+     * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
+     * shareable specific flushes.
+     */
+
+    do_rvae_write(env, value, vae1_tlbmask(env), true);
+}
+
+static void tlbi_aa64_rvae2_write(CPUARMState *env,
+                                  const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    /*
+     * Invalidate by VA range, EL2.
+     * Currently handles all of RVAE2 and RVALE2,
+     * since we don't support flush-for-specific-ASID-only or
+     * flush-last-level-only.
+     */
+
+    do_rvae_write(env, value, vae2_tlbmask(env),
+                  tlb_force_broadcast(env));
+
+
+}
+
+static void tlbi_aa64_rvae2is_write(CPUARMState *env,
+                                    const ARMCPRegInfo *ri,
+                                    uint64_t value)
+{
+    /*
+     * Invalidate by VA range, Inner/Outer Shareable, EL2.
+     * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
+     * since we don't support flush-for-specific-ASID-only,
+     * flush-last-level-only or inner/outer shareable specific flushes.
+     */
+
+    do_rvae_write(env, value, vae2_tlbmask(env), true);
+
+}
+
+static void tlbi_aa64_rvae3_write(CPUARMState *env,
+                                  const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    /*
+     * Invalidate by VA range, EL3.
+     * Currently handles all of RVAE3 and RVALE3,
+     * since we don't support flush-for-specific-ASID-only or
+     * flush-last-level-only.
+     */
+
+    do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env));
+}
+
+static void tlbi_aa64_rvae3is_write(CPUARMState *env,
+                                    const ARMCPRegInfo *ri,
+                                    uint64_t value)
+{
+    /*
+     * Invalidate by VA range, EL3, Inner/Outer Shareable.
+     * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
+     * since we don't support flush-for-specific-ASID-only,
+     * flush-last-level-only or inner/outer specific flushes.
+     */
+
+    do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
+}
+
+static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo =
*ri,
+                                     uint64_t value)
+{
+    do_rvae_write(env, value, ipas2e1_tlbmask(env, value),
+                  tlb_force_broadcast(env));
+}
+
+static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
+                                       const ARMCPRegInfo *ri,
+                                       uint64_t value)
+{
+    do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true);
+}
+
+static const ARMCPRegInfo tlbirange_reginfo[] =3D {
+    { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAE1IS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAAE1IS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+   { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVALE1IS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAALE1IS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAE1OS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAAE1OS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+   { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVALE1OS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIRVAALE1OS,
+      .writefn =3D tlbi_aa64_rvae1is_write },
+    { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIRVAE1,
+      .writefn =3D tlbi_aa64_rvae1_write },
+    { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIRVAAE1,
+      .writefn =3D tlbi_aa64_rvae1_write },
+   { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIRVALE1,
+      .writefn =3D tlbi_aa64_rvae1_write },
+    { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA=
W,
+      .fgt =3D FGT_TLBIRVAALE1,
+      .writefn =3D tlbi_aa64_rvae1_write },
+    { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ripas2e1is_write },
+    { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ripas2e1is_write },
+    { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2is_write },
+   { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2is_write },
+    { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ripas2e1_write },
+    { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_ripas2e1_write },
+   { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2is_write },
+   { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2is_write },
+    { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2_write },
+   { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_rvae2_write },
+   { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3is_write },
+   { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3is_write },
+   { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3is_write },
+   { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3is_write },
+   { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3_write },
+   { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_rvae3_write },
+};
+#endif
+
 void define_tlb_insn_regs(ARMCPU *cpu)
 {
     CPUARMState *env =3D &cpu->env;
@@ -591,4 +915,9 @@ void define_tlb_insn_regs(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         define_arm_cp_regs(cpu, tlbi_el3_cp_reginfo);
     }
+#ifdef TARGET_AARCH64
+    if (cpu_isar_feature(aa64_tlbirange, cpu)) {
+        define_arm_cp_regs(cpu, tlbirange_reginfo);
+    }
+#endif
 }
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 07/10] target/arm: Move the TLBI OS insns to tlb-insns.c.
Date: Tue, 10 Dec 2024 16:04:49 +0000
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Move the TLBI OS insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c        | 80 --------------------------------------
 target/arm/tcg/tlb-insns.c | 80 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+), 80 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 376aa9aecd5..3f7d56e809f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7116,83 +7116,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D {
       .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) },
 };
=20
-static const ARMCPRegInfo tlbios_reginfo[] =3D {
-    { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVMALLE1OS,
-      .writefn =3D tlbi_aa64_vmalle1is_write },
-    { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
-      .fgt =3D FGT_TLBIVAE1OS,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIASIDE1OS,
-      .writefn =3D tlbi_aa64_vmalle1is_write },
-    { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVAAE1OS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVALE1OS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7,
-      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
-      .fgt =3D FGT_TLBIVAALE1OS,
-      .writefn =3D tlbi_aa64_vae1is_write },
-    { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_alle2is_write },
-    { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2is_write },
-   { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1is_write },
-    { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-      .writefn =3D tlbi_aa64_vae2is_write },
-    { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6,
-      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle1is_write },
-    { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0,
-      .access =3D PL2_W, .type =3D ARM_CP_NOP },
-    { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3,
-      .access =3D PL2_W, .type =3D ARM_CP_NOP },
-    { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4,
-      .access =3D PL2_W, .type =3D ARM_CP_NOP },
-    { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7,
-      .access =3D PL2_W, .type =3D ARM_CP_NOP },
-    { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_alle3is_write },
-    { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3is_write },
-    { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_vae3is_write },
-};
-
 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     Error *err =3D NULL;
@@ -9066,9 +8989,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_rndr, cpu)) {
         define_arm_cp_regs(cpu, rndr_reginfo);
     }
-    if (cpu_isar_feature(aa64_tlbios, cpu)) {
-        define_arm_cp_regs(cpu, tlbios_reginfo);
-    }
     /* Data Cache clean instructions up to PoP */
     if (cpu_isar_feature(aa64_dcpop, cpu)) {
         define_one_arm_cp_reg(cpu, dcpop_reg);
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index a273c6f4b58..45ebfc512f9 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -884,6 +884,83 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D {
       .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
       .writefn =3D tlbi_aa64_rvae3_write },
 };
+
+static const ARMCPRegInfo tlbios_reginfo[] =3D {
+    { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVMALLE1OS,
+      .writefn =3D tlbi_aa64_vmalle1is_write },
+    { .name =3D "TLBI_VAE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
+      .fgt =3D FGT_TLBIVAE1OS,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIASIDE1OS,
+      .writefn =3D tlbi_aa64_vmalle1is_write },
+    { .name =3D "TLBI_VAAE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 3,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVAAE1OS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_VALE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVALE1OS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_VAALE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 7,
+      .access =3D PL1_W, .accessfn =3D access_ttlbos, .type =3D ARM_CP_NO_=
RAW,
+      .fgt =3D FGT_TLBIVAALE1OS,
+      .writefn =3D tlbi_aa64_vae1is_write },
+    { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_alle2is_write },
+    { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2is_write },
+   { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1is_write },
+    { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
+      .writefn =3D tlbi_aa64_vae2is_write },
+    { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6,
+      .access =3D PL2_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle1is_write },
+    { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0,
+      .access =3D PL2_W, .type =3D ARM_CP_NOP },
+    { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3,
+      .access =3D PL2_W, .type =3D ARM_CP_NOP },
+    { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4,
+      .access =3D PL2_W, .type =3D ARM_CP_NOP },
+    { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7,
+      .access =3D PL2_W, .type =3D ARM_CP_NOP },
+    { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_alle3is_write },
+    { .name =3D "TLBI_VAE3OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 1,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3is_write },
+    { .name =3D "TLBI_VALE3OS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_vae3is_write },
+};
 #endif
=20
 void define_tlb_insn_regs(ARMCPU *cpu)
@@ -919,5 +996,8 @@ void define_tlb_insn_regs(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_tlbirange, cpu)) {
         define_arm_cp_regs(cpu, tlbirange_reginfo);
     }
+    if (cpu_isar_feature(aa64_tlbios, cpu)) {
+        define_arm_cp_regs(cpu, tlbios_reginfo);
+    }
 #endif
 }
--=20
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Subject: [PATCH 08/10] target/arm: Move small helper functions to tlb-insns.c
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The remaining functions that we temporarily made global are now
used only from callsits in tlb-insns.c; move them across and
make them file-local again.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h        |  34 ------
 target/arm/helper.c        | 220 -------------------------------------
 target/arm/tcg/tlb-insns.c | 220 +++++++++++++++++++++++++++++++++++++
 3 files changed, 220 insertions(+), 254 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fe838bcfd97..cc7c54378f4 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1134,38 +1134,4 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCP=
RegInfo *ri)
     return ri->opc1 =3D=3D 4 || ri->opc1 =3D=3D 5;
 }
=20
-/*
- * Temporary declarations of functions until the move to tlb_insn_helper.c
- * is complete and we can make the functions static again
- */
-CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
-                           bool isread);
-CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
-                             bool isread);
-CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
-                             bool isread);
-bool tlb_force_broadcast(CPUARMState *env);
-int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
-                       uint64_t addr);
-int vae1_tlbbits(CPUARMState *env, uint64_t addr);
-int vae2_tlbbits(CPUARMState *env, uint64_t addr);
-int vae1_tlbmask(CPUARMState *env);
-int vae2_tlbmask(CPUARMState *env);
-int ipas2e1_tlbmask(CPUARMState *env, int64_t value);
-int e2_tlbmask(CPUARMState *env);
-void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value);
-void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value);
-void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value);
-void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value);
-void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value);
-void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value);
-void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value);
-
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3f7d56e809f..cd9f8650316 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -365,40 +365,6 @@ static CPAccessResult access_tacr(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     return CP_ACCESS_OK;
 }
=20
-/* Check for traps from EL1 due to HCR_EL2.TTLB. */
-CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
-                           bool isread)
-{
-    if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))=
 {
-        return CP_ACCESS_TRAP_EL2;
-    }
-    return CP_ACCESS_OK;
-}
-
-/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
-CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
-                             bool isread)
-{
-    if (arm_current_el(env) =3D=3D 1 &&
-        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
-        return CP_ACCESS_TRAP_EL2;
-    }
-    return CP_ACCESS_OK;
-}
-
-#ifdef TARGET_AARCH64
-/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
-CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
-                             bool isread)
-{
-    if (arm_current_el(env) =3D=3D 1 &&
-        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
-        return CP_ACCESS_TRAP_EL2;
-    }
-    return CP_ACCESS_OK;
-}
-#endif
-
 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t =
value)
 {
     ARMCPU *cpu =3D env_archcpu(env);
@@ -455,16 +421,6 @@ int alle1_tlbmask(CPUARMState *env)
             ARMMMUIdxBit_Stage2_S);
 }
=20
-/*
- * Non-IS variants of TLB operations are upgraded to
- * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
- * force broadcast of these operations.
- */
-bool tlb_force_broadcast(CPUARMState *env)
-{
-    return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB);
-}
-
 static const ARMCPRegInfo cp_reginfo[] =3D {
     /*
      * Define the secure and non-secure FCSE identifier CP registers
@@ -4680,182 +4636,6 @@ static CPAccessResult access_tocu(CPUARMState *env,=
 const ARMCPRegInfo *ri,
     return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
 }
=20
-/*
- * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru=
ctions
- * Page D4-1736 (DDI0487A.b)
- */
-
-int vae1_tlbmask(CPUARMState *env)
-{
-    uint64_t hcr =3D arm_hcr_el2_eff(env);
-    uint16_t mask;
-
-    assert(arm_feature(env, ARM_FEATURE_AARCH64));
-
-    if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
-        mask =3D ARMMMUIdxBit_E20_2 |
-               ARMMMUIdxBit_E20_2_PAN |
-               ARMMMUIdxBit_E20_0;
-    } else {
-        /* This is AArch64 only, so we don't need to touch the EL30_x TLBs=
 */
-        mask =3D ARMMMUIdxBit_E10_1 |
-               ARMMMUIdxBit_E10_1_PAN |
-               ARMMMUIdxBit_E10_0;
-    }
-    return mask;
-}
-
-int vae2_tlbmask(CPUARMState *env)
-{
-    uint64_t hcr =3D arm_hcr_el2_eff(env);
-    uint16_t mask;
-
-    if (hcr & HCR_E2H) {
-        mask =3D ARMMMUIdxBit_E20_2 |
-               ARMMMUIdxBit_E20_2_PAN |
-               ARMMMUIdxBit_E20_0;
-    } else {
-        mask =3D ARMMMUIdxBit_E2;
-    }
-    return mask;
-}
-
-/* Return 56 if TBI is enabled, 64 otherwise. */
-int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
-                       uint64_t addr)
-{
-    uint64_t tcr =3D regime_tcr(env, mmu_idx);
-    int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx);
-    int select =3D extract64(addr, 55, 1);
-
-    return (tbi >> select) & 1 ? 56 : 64;
-}
-
-int vae1_tlbbits(CPUARMState *env, uint64_t addr)
-{
-    uint64_t hcr =3D arm_hcr_el2_eff(env);
-    ARMMMUIdx mmu_idx;
-
-    assert(arm_feature(env, ARM_FEATURE_AARCH64));
-
-    /* Only the regime of the mmu_idx below is significant. */
-    if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
-        mmu_idx =3D ARMMMUIdx_E20_0;
-    } else {
-        mmu_idx =3D ARMMMUIdx_E10_0;
-    }
-
-    return tlbbits_for_regime(env, mmu_idx, addr);
-}
-
-int vae2_tlbbits(CPUARMState *env, uint64_t addr)
-{
-    uint64_t hcr =3D arm_hcr_el2_eff(env);
-    ARMMMUIdx mmu_idx;
-
-    /*
-     * Only the regime of the mmu_idx below is significant.
-     * Regime EL2&0 has two ranges with separate TBI configuration, while =
EL2
-     * only has one.
-     */
-    if (hcr & HCR_E2H) {
-        mmu_idx =3D ARMMMUIdx_E20_2;
-    } else {
-        mmu_idx =3D ARMMMUIdx_E2;
-    }
-
-    return tlbbits_for_regime(env, mmu_idx, addr);
-}
-
-void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae1_tlbmask(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
-}
-
-int e2_tlbmask(CPUARMState *env)
-{
-    return (ARMMMUIdxBit_E20_0 |
-            ARMMMUIdxBit_E20_2 |
-            ARMMMUIdxBit_E20_2_PAN |
-            ARMMMUIdxBit_E2);
-}
-
-void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D alle1_tlbmask(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
-}
-
-void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D e2_tlbmask(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
-}
-
-void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                             uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
-}
-
-void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae1_tlbmask(env);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-    int bits =3D vae1_tlbbits(env, pageaddr);
-
-    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
-}
-
-void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                   uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    int mask =3D vae2_tlbmask(env);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-    int bits =3D vae2_tlbbits(env, pageaddr);
-
-    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
-}
-
-void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
-    int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
-
-    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                                  ARMMMUIdxBit_E3, bits);
-}
-
-int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
-{
-    /*
-     * The MSB of value is the NS field, which only applies if SEL2
-     * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
-     */
-    return (value >=3D 0
-            && cpu_isar_feature(aa64_sel2, env_archcpu(env))
-            && arm_is_secure_below_el3(env)
-            ? ARMMMUIdxBit_Stage2_S
-            : ARMMMUIdxBit_Stage2);
-}
-
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo=
 *ri,
                                       bool isread)
 {
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 45ebfc512f9..51b4756e31e 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -13,6 +13,40 @@
 #include "cpu-features.h"
 #include "cpregs.h"
=20
+/* Check for traps from EL1 due to HCR_EL2.TTLB. */
+static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))=
 {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    return CP_ACCESS_OK;
+}
+
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
+static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    bool isread)
+{
+    if (arm_current_el(env) =3D=3D 1 &&
+        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    return CP_ACCESS_OK;
+}
+
+#ifdef TARGET_AARCH64
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
+static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    bool isread)
+{
+    if (arm_current_el(env) =3D=3D 1 &&
+        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    return CP_ACCESS_OK;
+}
+#endif
+
 /* IS variants of TLB operations must affect all cores */
 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t value)
@@ -46,6 +80,16 @@ static void tlbimvaa_is_write(CPUARMState *env, const AR=
MCPRegInfo *ri,
     tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
 }
=20
+/*
+ * Non-IS variants of TLB operations are upgraded to
+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
+ * force broadcast of these operations.
+ */
+static bool tlb_force_broadcast(CPUARMState *env)
+{
+    return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB);
+}
+
 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           uint64_t value)
 {
@@ -170,6 +214,102 @@ static void tlbiall_hyp_is_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
 }
=20
+/*
+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru=
ctions
+ * Page D4-1736 (DDI0487A.b)
+ */
+
+static int vae1_tlbmask(CPUARMState *env)
+{
+    uint64_t hcr =3D arm_hcr_el2_eff(env);
+    uint16_t mask;
+
+    assert(arm_feature(env, ARM_FEATURE_AARCH64));
+
+    if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+        mask =3D ARMMMUIdxBit_E20_2 |
+               ARMMMUIdxBit_E20_2_PAN |
+               ARMMMUIdxBit_E20_0;
+    } else {
+        /* This is AArch64 only, so we don't need to touch the EL30_x TLBs=
 */
+        mask =3D ARMMMUIdxBit_E10_1 |
+               ARMMMUIdxBit_E10_1_PAN |
+               ARMMMUIdxBit_E10_0;
+    }
+    return mask;
+}
+
+static int vae2_tlbmask(CPUARMState *env)
+{
+    uint64_t hcr =3D arm_hcr_el2_eff(env);
+    uint16_t mask;
+
+    if (hcr & HCR_E2H) {
+        mask =3D ARMMMUIdxBit_E20_2 |
+               ARMMMUIdxBit_E20_2_PAN |
+               ARMMMUIdxBit_E20_0;
+    } else {
+        mask =3D ARMMMUIdxBit_E2;
+    }
+    return mask;
+}
+
+/* Return 56 if TBI is enabled, 64 otherwise. */
+static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
+                       uint64_t addr)
+{
+    uint64_t tcr =3D regime_tcr(env, mmu_idx);
+    int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx);
+    int select =3D extract64(addr, 55, 1);
+
+    return (tbi >> select) & 1 ? 56 : 64;
+}
+
+static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
+{
+    uint64_t hcr =3D arm_hcr_el2_eff(env);
+    ARMMMUIdx mmu_idx;
+
+    assert(arm_feature(env, ARM_FEATURE_AARCH64));
+
+    /* Only the regime of the mmu_idx below is significant. */
+    if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) {
+        mmu_idx =3D ARMMMUIdx_E20_0;
+    } else {
+        mmu_idx =3D ARMMMUIdx_E10_0;
+    }
+
+    return tlbbits_for_regime(env, mmu_idx, addr);
+}
+
+static int vae2_tlbbits(CPUARMState *env, uint64_t addr)
+{
+    uint64_t hcr =3D arm_hcr_el2_eff(env);
+    ARMMMUIdx mmu_idx;
+
+    /*
+     * Only the regime of the mmu_idx below is significant.
+     * Regime EL2&0 has two ranges with separate TBI configuration, while =
EL2
+     * only has one.
+     */
+    if (hcr & HCR_E2H) {
+        mmu_idx =3D ARMMMUIdx_E20_2;
+    } else {
+        mmu_idx =3D ARMMMUIdx_E2;
+    }
+
+    return tlbbits_for_regime(env, mmu_idx, addr);
+}
+
+static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo=
 *ri,
+                                      uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae1_tlbmask(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+}
+
 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
                                     uint64_t value)
 {
@@ -183,6 +323,14 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, =
const ARMCPRegInfo *ri,
     }
 }
=20
+static int e2_tlbmask(CPUARMState *env)
+{
+    return (ARMMMUIdxBit_E20_0 |
+            ARMMMUIdxBit_E20_2 |
+            ARMMMUIdxBit_E20_2_PAN |
+            ARMMMUIdxBit_E2);
+}
+
 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                   uint64_t value)
 {
@@ -210,6 +358,32 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, co=
nst ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
 }
=20
+static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D alle1_tlbmask(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+}
+
+static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D e2_tlbmask(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+}
+
+static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
+}
+
 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -241,6 +415,17 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
 }
=20
+static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
+                                   uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae1_tlbmask(env);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+    int bits =3D vae1_tlbbits(env, pageaddr);
+
+    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
+}
+
 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
@@ -262,6 +447,41 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, con=
st ARMCPRegInfo *ri,
     }
 }
=20
+static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
+                                   uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    int mask =3D vae2_tlbmask(env);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+    int bits =3D vae2_tlbbits(env, pageaddr);
+
+    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits=
);
+}
+
+static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r=
i,
+                                   uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+    uint64_t pageaddr =3D sextract64(value << 12, 0, 56);
+    int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
+
+    tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
+                                                  ARMMMUIdxBit_E3, bits);
+}
+
+static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
+{
+    /*
+     * The MSB of value is the NS field, which only applies if SEL2
+     * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
+     */
+    return (value >=3D 0
+            && cpu_isar_feature(aa64_sel2, env_archcpu(env))
+            && arm_is_secure_below_el3(env)
+            ? ARMMMUIdxBit_Stage2_S
+            : ARMMMUIdxBit_Stage2);
+}
+
 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
                                     uint64_t value)
 {
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 09/10] target/arm: Move RME TLB insns to tlb-insns.c
Date: Tue, 10 Dec 2024 16:04:51 +0000
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Move the FEAT_RME specific TLB insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c        | 38 --------------------------------
 target/arm/tcg/tlb-insns.c | 45 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+), 38 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index cd9f8650316..910ae62c476 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6525,14 +6525,6 @@ static const ARMCPRegInfo sme_reginfo[] =3D {
       .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
 };
=20
-static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush(cs);
-}
-
 static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
@@ -6550,14 +6542,6 @@ static void gpccr_reset(CPUARMState *env, const ARMC=
PRegInfo *ri)
                                      env_archcpu(env)->reset_l0gptsz);
 }
=20
-static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
-                                    uint64_t value)
-{
-    CPUState *cs =3D env_cpu(env);
-
-    tlb_flush_all_cpus_synced(cs);
-}
-
 static const ARMCPRegInfo rme_reginfo[] =3D {
     { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64,
       .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6,
@@ -6569,28 +6553,6 @@ static const ARMCPRegInfo rme_reginfo[] =3D {
     { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64,
       .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5,
       .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar=
_el3) },
-    { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_paall_write },
-    { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_paallos_write },
-    /*
-     * QEMU does not have a way to invalidate by physical address, thus
-     * invalidating a range of physical addresses is accomplished by
-     * flushing all tlb entries in the outer shareable domain,
-     * just like PAALLOS.
-     */
-    { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_paallos_write },
-    { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64,
-      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3,
-      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
-      .writefn =3D tlbi_aa64_paallos_write },
     { .name =3D "DC_CIPAPA", .state =3D ARM_CP_STATE_AA64,
       .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 1,
       .access =3D PL3_W, .type =3D ARM_CP_NOP },
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index 51b4756e31e..d20d32624da 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -1181,6 +1181,48 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D {
       .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
       .writefn =3D tlbi_aa64_vae3is_write },
 };
+
+static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush(cs);
+}
+
+static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *=
ri,
+                                    uint64_t value)
+{
+    CPUState *cs =3D env_cpu(env);
+
+    tlb_flush_all_cpus_synced(cs);
+}
+
+static const ARMCPRegInfo tlbi_rme_reginfo[] =3D {
+    { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_paall_write },
+    { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_paallos_write },
+    /*
+     * QEMU does not have a way to invalidate by physical address, thus
+     * invalidating a range of physical addresses is accomplished by
+     * flushing all tlb entries in the outer shareable domain,
+     * just like PAALLOS.
+     */
+    { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_paallos_write },
+    { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64,
+      .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3,
+      .access =3D PL3_W, .type =3D ARM_CP_NO_RAW,
+      .writefn =3D tlbi_aa64_paallos_write },
+};
+
 #endif
=20
 void define_tlb_insn_regs(ARMCPU *cpu)
@@ -1219,5 +1261,8 @@ void define_tlb_insn_regs(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_tlbios, cpu)) {
         define_arm_cp_regs(cpu, tlbios_reginfo);
     }
+    if (cpu_isar_feature(aa64_rme, cpu)) {
+        define_arm_cp_regs(cpu, tlbi_rme_reginfo);
+    }
 #endif
 }
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org,
	qemu-devel@nongnu.org
Subject: [PATCH 10/10] target/arm: Simplify condition for
 tlbi_el2_cp_reginfo[]
Date: Tue, 10 Dec 2024 16:04:52 +0000
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We currently register the tlbi_el2_cp_reginfo[] TLBI insns if EL2 is
implemented, or if EL3 and v8 is implemented.  This is a copy of the
logic used for el2_cp_reginfo[], but for the specific case of the
TLBI insns we can simplify it.  This is because we do not need the
"if EL2 does not exist but EL3 does then EL2 registers should exist
and be RAZ/WI" handling here: all our cpregs are for instructions,
which UNDEF when EL3 exists and EL2 does not.

Simplify the condition down to just "if EL2 exists".
This is not a behaviour change because:
 * for AArch64 insns we marked them with ARM_CP_EL3_NO_EL2_UNDEF,
   which meant that define_arm_cp_regs() would ignore them if
   EL2 wasn't present
 * for AArch32 insns, the .access =3D PL2_W meant that if EL2
   was not present the only way to get at them was from AArch32
   EL3; but we have no CPUs which have ARM_FEATURE_V8 but
   start in AArch32

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/tlb-insns.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index d20d32624da..0f67294edc4 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -1246,9 +1246,7 @@ void define_tlb_insn_regs(ARMCPU *cpu)
      * ops (i.e. matching the condition for el2_cp_reginfo[] in
      * helper.c), but we will be able to simplify this later.
      */
-    if (arm_feature(env, ARM_FEATURE_EL2)
-        || (arm_feature(env, ARM_FEATURE_EL3)
-            && arm_feature(env, ARM_FEATURE_V8))) {
+    if (arm_feature(env, ARM_FEATURE_EL2)) {
         define_arm_cp_regs(cpu, tlbi_el2_cp_reginfo);
     }
     if (arm_feature(env, ARM_FEATURE_EL3)) {
--=20
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