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Mon, 09 Dec 2024 22:57:07 -0800 (PST)
From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>, qemu-devel@nongnu.org,
=?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= <fbarrat@linux.ibm.com>,
Chalapathi V <chalapathi.v@linux.ibm.com>,
Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Subject: [PATCH] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5
Date: Tue, 10 Dec 2024 16:56:59 +1000
Message-ID: <20241210065659.1322405-1-npiggin@gmail.com>
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Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.
skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.
In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/pci-host/pnv_phb4.h | 5 ++++
include/hw/ppc/pnv_xscom.h | 4 +++
hw/pci-host/pnv_phb4_pec.c | 55 +++++++++++++++++++++++++++++++++-
hw/ppc/pnv.c | 8 +++++
4 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 8abee78e4d4..8a80c0c667a 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -13,6 +13,7 @@
#include "hw/pci-host/pnv_phb.h"
#include "hw/pci/pci_bus.h"
#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_nest_pervasive.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"
=20
@@ -174,6 +175,9 @@ struct PnvPhb4PecState {
uint32_t index;
uint32_t chip_id;
=20
+ /* Pervasive chiplet control */
+ PnvNestChipletPervasive nest_pervasive;
+
/* Nest registers, excuding per-stack */
#define PHB4_PEC_NEST_REGS_COUNT 0xf
uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
@@ -196,6 +200,7 @@ struct PnvPhb4PecState {
struct PnvPhb4PecClass {
DeviceClass parent_class;
=20
+ uint32_t (*xscom_cplt_base)(PnvPhb4PecState *pec);
uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec);
uint32_t xscom_nest_size;
uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec);
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 648388a5995..a927aea1c09 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -126,6 +126,8 @@ struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_PEC_PCI_BASE 0xd010800
#define PNV9_XSCOM_PEC_PCI_SIZE 0x200
=20
+#define PNV9_XSCOM_PEC_NEST_CPLT_BASE 0x0d000000
+
/* XSCOM PCI "pass-through" window to PHB SCOM */
#define PNV9_XSCOM_PEC_PCI_STK0 0x100
#define PNV9_XSCOM_PEC_PCI_STK1 0x140
@@ -197,6 +199,8 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
=20
+#define PNV10_XSCOM_PEC_NEST_CPLT_BASE 0x08000000
+
#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */
#define PNV10_XSCOM_PEC_PCI_SIZE 0x200
=20
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index ce8e228f987..533c8a26131 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -197,6 +197,9 @@ static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecSt=
ate *pec,
return phb;
}
=20
+#define XPEC_P9_PCI_LANE_CFG PPC_BITMASK(10, 11)
+#define XPEC_P10_PCI_LANE_CFG PPC_BITMASK(0, 1)
+
static void pnv_pec_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecState *pec =3D PNV_PHB4_PEC(dev);
@@ -211,6 +214,43 @@ static void pnv_pec_realize(DeviceState *dev, Error **=
errp)
=20
pec->num_phbs =3D pecc->num_phbs[pec->index];
=20
+ /* Pervasive chiplet */
+ object_initialize_child(OBJECT(pec), "nest-pervasive-common",
+ &pec->nest_pervasive,
+ TYPE_PNV_NEST_CHIPLET_PERVASIVE);
+ if (!qdev_realize(DEVICE(&pec->nest_pervasive), NULL, errp)) {
+ return;
+ }
+
+ /* Set up pervasive chiplet registers */
+ /*
+ * Most registers are not set up, this just sets the PCI CONF1 link-wi=
dth
+ * field because skiboot probes it.
+ */
+ if (pecc->version =3D=3D PNV_PHB4_VERSION) {
+ /*
+ * On P9, PEC2 has configurable 1/2/3-furcation).
+ * Make it trifurcated (x8, x4, x4) to match pnv_pec_num_phbs.
+ */
+ if (pec->index =3D=3D 2) {
+ pec->nest_pervasive.control_regs.cplt_cfg1 =3D
+ SETFIELD(XPEC_P9_PCI_LANE_CFG,
+ pec->nest_pervasive.control_regs.cplt_cfg1,
+ 0b10);
+ }
+ } else if (pecc->version =3D=3D PNV_PHB5_VERSION) {
+ /*
+ * On P10, both PECs are configurable 1/2/3-furcation).
+ * Both are trifurcated to match pnv_phb5_pec_num_stacks.
+ */
+ pec->nest_pervasive.control_regs.cplt_cfg1 =3D
+ SETFIELD(XPEC_P10_PCI_LANE_CFG,
+ pec->nest_pervasive.control_regs.cplt_cfg1,
+ 0b10);
+ } else {
+ g_assert_not_reached();
+ }
+
/* Create PHBs if running with defaults */
if (defaults_enabled()) {
g_assert(pec->num_phbs <=3D MAX_PHBS_PER_PEC);
@@ -291,9 +331,16 @@ static Property pnv_pec_properties[] =3D {
DEFINE_PROP_END_OF_LIST(),
};
=20
+#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL
+
+static uint32_t pnv_pec_xscom_cplt_base(PnvPhb4PecState *pec)
+{
+ return PNV9_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->ind=
ex;
+}
+
static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
{
- return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
+ return PNV9_XSCOM_PEC_PCI_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
}
=20
static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
@@ -322,6 +369,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void=
*data)
device_class_set_props(dc, pnv_pec_properties);
dc->user_creatable =3D false;
=20
+ pecc->xscom_cplt_base =3D pnv_pec_xscom_cplt_base;
pecc->xscom_nest_base =3D pnv_pec_xscom_nest_base;
pecc->xscom_pci_base =3D pnv_pec_xscom_pci_base;
pecc->xscom_nest_size =3D PNV9_XSCOM_PEC_NEST_SIZE;
@@ -350,6 +398,10 @@ static const TypeInfo pnv_pec_type_info =3D {
/*
* POWER10 definitions
*/
+static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->in=
dex;
+}
=20
static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
{
@@ -374,6 +426,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass,=
void *data)
static const char compat[] =3D "ibm,power10-pbcq";
static const char stk_compat[] =3D "ibm,power10-phb-stack";
=20
+ pecc->xscom_cplt_base =3D pnv_phb5_pec_xscom_cplt_base;
pecc->xscom_nest_base =3D pnv_phb5_pec_xscom_nest_base;
pecc->xscom_pci_base =3D pnv_phb5_pec_xscom_pci_base;
pecc->xscom_nest_size =3D PNV10_XSCOM_PEC_NEST_SIZE;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 22c67e82aa7..820eabf30a8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1755,6 +1755,7 @@ static void pnv_chip_power9_pec_realize(PnvChip *chip=
, Error **errp)
for (i =3D 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec =3D &chip9->pecs[i];
PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec);
+ uint32_t pec_cplt_base;
uint32_t pec_nest_base;
uint32_t pec_pci_base;
=20
@@ -1767,9 +1768,12 @@ static void pnv_chip_power9_pec_realize(PnvChip *chi=
p, Error **errp)
return;
}
=20
+ pec_cplt_base =3D pecc->xscom_cplt_base(pec);
pec_nest_base =3D pecc->xscom_nest_base(pec);
pec_pci_base =3D pecc->xscom_pci_base(pec);
=20
+ pnv_xscom_add_subregion(chip, pec_cplt_base,
+ &pec->nest_pervasive.xscom_ctrl_regs_mr);
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
}
@@ -2030,6 +2034,7 @@ static void pnv_chip_power10_phb_realize(PnvChip *chi=
p, Error **errp)
for (i =3D 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec =3D &chip10->pecs[i];
PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec);
+ uint32_t pec_cplt_base;
uint32_t pec_nest_base;
uint32_t pec_pci_base;
=20
@@ -2042,9 +2047,12 @@ static void pnv_chip_power10_phb_realize(PnvChip *ch=
ip, Error **errp)
return;
}
=20
+ pec_cplt_base =3D pecc->xscom_cplt_base(pec);
pec_nest_base =3D pecc->xscom_nest_base(pec);
pec_pci_base =3D pecc->xscom_pci_base(pec);
=20
+ pnv_xscom_add_subregion(chip, pec_cplt_base,
+ &pec->nest_pervasive.xscom_ctrl_regs_mr);
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
}
--=20
2.45.2