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Mon, 09 Dec 2024 19:05:01 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH 1/9] ppc/pnv/homer: Fix OCC registers Date: Tue, 10 Dec 2024 13:04:41 +1000 Message-ID: <20241210030451.1306608-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241210030451.1306608-1-npiggin@gmail.com> References: <20241210030451.1306608-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733800013747116600 Content-Type: text/plain; charset="utf-8" The HOMER OCC registers seem to have bitrotted and fail for various reasons on powernv8, 9, and 10. The major problems are that POWER8 has the wrong version value and its pstate ordering is incorrect. POWER9/10 have not set the OCC state to active. Non-zero chips are also set to OCC slaves for POWER9/10. Unfortunately skiboot has also bitrotted and requires fixes that are not yet in the bios files to run. With a patched skiboot, before this change, powernv9/10 report: [ 0.262050394,3] OCC: Chip: 0: OCC not active [ 0.262128603,3] OCC: Initialization on all chips did not complete(timed= out) powernv8 reports: [ 0.173572100,3] OCC: Unknown OCC-OPAL interface version. [ 0.173812059,3] OCC: Initialization on all chips did not complete(timed= out) After this patch, all report: [ 0.176815668,5] OCC: All Chip Rdy after 0 ms Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_homer.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index f9a203d11d0..9aedc08cc00 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -70,21 +70,24 @@ static uint64_t pnv_power8_homer_read(void *opaque, hwa= ddr addr, PnvHomer *homer =3D PNV_HOMER(opaque); =20 switch (addr) { - case PNV8_OCC_PSTATE_VERSION: - case PNV8_OCC_PSTATE_MIN: - case PNV8_OCC_PSTATE_ID_ZERO: - return 0; case PNV8_OCC_PSTATE_VALID: + return 1; case PNV8_OCC_PSTATE_THROTTLE: + return 0; + case PNV8_OCC_PSTATE_VERSION: + return 0x02; + case PNV8_OCC_PSTATE_MIN: + return -2; case PNV8_OCC_PSTATE_NOM: case PNV8_OCC_PSTATE_TURBO: - case PNV8_OCC_PSTATE_ID_ONE: + return -1; + case PNV8_OCC_PSTATE_ULTRA_TURBO: + return 0; + case PNV8_OCC_PSTATE_ID_ZERO: + return 0; case PNV8_OCC_VDD_VOLTAGE_IDENTIFIER: case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER: return 1; - case PNV8_OCC_PSTATE_ULTRA_TURBO: - case PNV8_OCC_PSTATE_ID_TWO: - return 2; case PNV8_OCC_PSTATE_DATA: return 0x1000000000000000; /* P8 frequency for 0, 1, and 2 pstates */ @@ -92,6 +95,10 @@ static uint64_t pnv_power8_homer_read(void *opaque, hwad= dr addr, case PNV8_OCC_PSTATE_ONE_FREQUENCY: case PNV8_OCC_PSTATE_TWO_FREQUENCY: return 3000; + case PNV8_OCC_PSTATE_ID_ONE: + return -1; + case PNV8_OCC_PSTATE_ID_TWO: + return -2; } /* pstate table core max array */ if (core_max_array(homer, addr)) { @@ -192,11 +199,12 @@ static const TypeInfo pnv_homer_power8_type_info =3D { =20 /* P9 Pstate table */ =20 +#define PNV9_OCC_PSTATE_VALID 0xe2000 #define PNV9_OCC_PSTATE_ID_ZERO 0xe2018 #define PNV9_OCC_PSTATE_ID_ONE 0xe2020 #define PNV9_OCC_PSTATE_ID_TWO 0xe2028 #define PNV9_OCC_PSTATE_DATA 0xe2000 -#define PNV9_OCC_PSTATE_DATA_AREA 0xe2008 +#define PNV9_OCC_PSTATE_MINOR_VERSION 0xe2008 #define PNV9_OCC_PSTATE_MIN 0xe2003 #define PNV9_OCC_PSTATE_NOM 0xe2004 #define PNV9_OCC_PSTATE_TURBO 0xe2005 @@ -211,7 +219,7 @@ static const TypeInfo pnv_homer_power8_type_info =3D { #define PNV9_OCC_PSTATE_TWO_FREQUENCY 0xe202c #define PNV9_OCC_ROLE_MASTER_OR_SLAVE 0xe2002 #define PNV9_CORE_MAX_BASE 0xe2819 - +#define PNV9_DYNAMIC_DATA_STATE 0xe2b80 =20 static uint64_t pnv_power9_homer_read(void *opaque, hwaddr addr, unsigned size) @@ -219,11 +227,17 @@ static uint64_t pnv_power9_homer_read(void *opaque, h= waddr addr, PnvHomer *homer =3D PNV_HOMER(opaque); =20 switch (addr) { + case PNV9_OCC_PSTATE_VALID: + return 1; case PNV9_OCC_MAX_PSTATE_ULTRA_TURBO: case PNV9_OCC_PSTATE_ID_ZERO: return 0; - case PNV9_OCC_PSTATE_DATA: case PNV9_OCC_ROLE_MASTER_OR_SLAVE: + if (homer->chip->chip_id =3D=3D 0) { + return 0x1; /* master */ + } else { + return 0x0; /* slave */ + } case PNV9_OCC_PSTATE_NOM: case PNV9_OCC_PSTATE_TURBO: case PNV9_OCC_PSTATE_ID_ONE: @@ -241,10 +255,13 @@ static uint64_t pnv_power9_homer_read(void *opaque, h= waddr addr, return 3000; case PNV9_OCC_PSTATE_MAJOR_VERSION: return 0x90; + case PNV9_OCC_PSTATE_MINOR_VERSION: + return 0x01; case PNV9_CHIP_HOMER_BASE: - case PNV9_OCC_PSTATE_DATA_AREA: case PNV9_CHIP_HOMER_IMAGE_POINTER: return 0x1000000000000000; + case PNV9_DYNAMIC_DATA_STATE: + return 0x03; /* active */ } /* pstate table core max array */ if (core_max_array(homer, addr)) { --=20 2.45.2 From nobody Tue Apr 15 22:27:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 09 Dec 2024 19:05:04 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH 2/9] ppc/pnv/homer: Make dummy reads return 0 Date: Tue, 10 Dec 2024 13:04:42 +1000 Message-ID: <20241210030451.1306608-3-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241210030451.1306608-1-npiggin@gmail.com> References: <20241210030451.1306608-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733799991549116600 Content-Type: text/plain; charset="utf-8" HOMER memory implements some dummy registers that return a nonsense value to satisfy skiboot accesses caused by "SLW" init and register save/restore programming that has never worked under QEMU: [ 0.265000943,3] SLW: Failed to set HRMOR for CPU 0,RC=3D0x1 [ 0.265356988,3] Disabling deep stop states To simplify a later change to implement HOMER as a RAM area, make these return zero, which has the same result. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_homer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index 9aedc08cc00..658b0186a38 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -89,7 +89,7 @@ static uint64_t pnv_power8_homer_read(void *opaque, hwadd= r addr, case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER: return 1; case PNV8_OCC_PSTATE_DATA: - return 0x1000000000000000; + return 0; /* P8 frequency for 0, 1, and 2 pstates */ case PNV8_OCC_PSTATE_ZERO_FREQUENCY: case PNV8_OCC_PSTATE_ONE_FREQUENCY: @@ -259,7 +259,7 @@ static uint64_t pnv_power9_homer_read(void *opaque, hwa= ddr addr, return 0x01; case PNV9_CHIP_HOMER_BASE: case PNV9_CHIP_HOMER_IMAGE_POINTER: - return 0x1000000000000000; + return 0; case PNV9_DYNAMIC_DATA_STATE: return 0x03; /* active */ } --=20 2.45.2 From nobody Tue Apr 15 22:27:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 09 Dec 2024 19:05:08 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH 3/9] ppc/pnv/occ: Fix common area sensor offsets Date: Tue, 10 Dec 2024 13:04:43 +1000 Message-ID: <20241210030451.1306608-4-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241210030451.1306608-1-npiggin@gmail.com> References: <20241210030451.1306608-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733799975558116600 Content-Type: text/plain; charset="utf-8" The commit to fix the OCC common area sensor mappings didn't update the register offsets to match. Before this change, skiboot reports: [ 0.347100086,3] OCC: Chip 0 sensor data invalid Afterward, there is no error and the sensor_groups directory appears under /sys/firmware/opal/. The SLW_IMAGE_BASE address looks like a workaround to intercept firmware memory accesses, but that does not seem to be required now (and would have been broken by the OCC common area region mapping change anyway). So it can be removed. Fixes: 3a1b70b66b5cb4 ("ppc/pnv: Fix OCC common area region mapping") Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 48123ceae17..c6681a035a7 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -32,22 +32,21 @@ #define OCB_OCI_OCCMISC_OR 0x4022 =20 /* OCC sensors */ -#define OCC_SENSOR_DATA_BLOCK_OFFSET 0x580000 -#define OCC_SENSOR_DATA_VALID 0x580001 -#define OCC_SENSOR_DATA_VERSION 0x580002 -#define OCC_SENSOR_DATA_READING_VERSION 0x580004 -#define OCC_SENSOR_DATA_NR_SENSORS 0x580008 -#define OCC_SENSOR_DATA_NAMES_OFFSET 0x580010 -#define OCC_SENSOR_DATA_READING_PING_OFFSET 0x580014 -#define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x58000c -#define OCC_SENSOR_DATA_NAME_LENGTH 0x58000d -#define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x580023 -#define OCC_SENSOR_LOC_CORE 0x580022 -#define OCC_SENSOR_LOC_GPU 0x580020 -#define OCC_SENSOR_TYPE_POWER 0x580003 -#define OCC_SENSOR_NAME 0x580005 -#define HWMON_SENSORS_MASK 0x58001e -#define SLW_IMAGE_BASE 0x0 +#define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 +#define OCC_SENSOR_DATA_VALID 0x0001 +#define OCC_SENSOR_DATA_VERSION 0x0002 +#define OCC_SENSOR_DATA_READING_VERSION 0x0004 +#define OCC_SENSOR_DATA_NR_SENSORS 0x0008 +#define OCC_SENSOR_DATA_NAMES_OFFSET 0x0010 +#define OCC_SENSOR_DATA_READING_PING_OFFSET 0x0014 +#define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x000c +#define OCC_SENSOR_DATA_NAME_LENGTH 0x000d +#define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x0023 +#define OCC_SENSOR_LOC_CORE 0x0022 +#define OCC_SENSOR_LOC_GPU 0x0020 +#define OCC_SENSOR_TYPE_POWER 0x0003 +#define OCC_SENSOR_NAME 0x0005 +#define HWMON_SENSORS_MASK 0x001e =20 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) { @@ -129,8 +128,6 @@ static uint64_t pnv_occ_common_area_read(void *opaque, = hwaddr addr, case HWMON_SENSORS_MASK: case OCC_SENSOR_LOC_GPU: return 0x8e00; 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Mon, 09 Dec 2024 19:05:11 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH 4/9] ppc/pnv/homer: class-based base and size Date: Tue, 10 Dec 2024 13:04:44 +1000 Message-ID: <20241210030451.1306608-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241210030451.1306608-1-npiggin@gmail.com> References: <20241210030451.1306608-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733799973906116600 Content-Type: text/plain; charset="utf-8" Put HOMER memory region base and size into the class, to allow more code-reuse between different machines in later changes. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv.h | 6 ++--- include/hw/ppc/pnv_homer.h | 7 +++++- hw/ppc/pnv_homer.c | 46 +++++++++++++++++++++++++++----------- 3 files changed, 41 insertions(+), 18 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fcb6699150c..d8fca079f2f 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -205,9 +205,8 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) =20 -#define PNV9_HOMER_SIZE 0x0000000000400000ull #define PNV9_HOMER_BASE(chip) \ - (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) + (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) =20 /* * POWER10 MMIO base addresses - 16TB stride per chip @@ -250,8 +249,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) =20 -#define PNV10_HOMER_SIZE 0x0000000000400000ull #define PNV10_HOMER_BASE(chip) \ - (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE) + (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) =20 #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h index b1c5d498dc5..5ffc0c97afe 100644 --- a/include/hw/ppc/pnv_homer.h +++ b/include/hw/ppc/pnv_homer.h @@ -42,15 +42,20 @@ struct PnvHomer { PnvChip *chip; MemoryRegion pba_regs; MemoryRegion regs; + hwaddr base; }; =20 =20 struct PnvHomerClass { DeviceClass parent_class; =20 + /* Get base address of HOMER memory */ + hwaddr (*get_base)(PnvChip *chip); + /* Size of HOMER memory */ + int size; + int pba_size; const MemoryRegionOps *pba_ops; - int homer_size; const MemoryRegionOps *homer_ops; =20 hwaddr core_max_base; diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index 658b0186a38..fda022adfc3 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -138,16 +138,16 @@ static uint64_t pnv_homer_power8_pba_read(void *opaqu= e, hwaddr addr, unsigned size) { PnvHomer *homer =3D PNV_HOMER(opaque); - PnvChip *chip =3D homer->chip; + PnvHomerClass *hmrc =3D PNV_HOMER_GET_CLASS(homer); uint32_t reg =3D addr >> 3; uint64_t val =3D 0; =20 switch (reg) { case PBA_BAR0: - val =3D PNV_HOMER_BASE(chip); + val =3D homer->base; break; case PBA_BARMASK0: /* P8 homer region mask */ - val =3D (PNV_HOMER_SIZE - 1) & 0x300000; + val =3D (hmrc->size - 1) & 0x300000; break; case PBA_BAR3: /* P8 occ common area */ val =3D PNV_OCC_COMMON_AREA_BASE; @@ -179,13 +179,19 @@ static const MemoryRegionOps pnv_homer_power8_pba_ops= =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static hwaddr pnv_homer_power8_get_base(PnvChip *chip) +{ + return PNV_HOMER_BASE(chip); +} + static void pnv_homer_power8_class_init(ObjectClass *klass, void *data) { PnvHomerClass *homer =3D PNV_HOMER_CLASS(klass); =20 + homer->get_base =3D pnv_homer_power8_get_base; + homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power8_pba_ops; - homer->homer_size =3D PNV_HOMER_SIZE; homer->homer_ops =3D &pnv_power8_homer_ops; homer->core_max_base =3D PNV8_CORE_MAX_BASE; } @@ -291,16 +297,16 @@ static uint64_t pnv_homer_power9_pba_read(void *opaqu= e, hwaddr addr, unsigned size) { PnvHomer *homer =3D PNV_HOMER(opaque); - PnvChip *chip =3D homer->chip; + PnvHomerClass *hmrc =3D PNV_HOMER_GET_CLASS(homer); uint32_t reg =3D addr >> 3; uint64_t val =3D 0; =20 switch (reg) { case PBA_BAR0: - val =3D PNV9_HOMER_BASE(chip); + val =3D homer->base; break; case PBA_BARMASK0: /* P9 homer region mask */ - val =3D (PNV9_HOMER_SIZE - 1) & 0x300000; + val =3D (hmrc->size - 1) & 0x300000; break; case PBA_BAR2: /* P9 occ common area */ val =3D PNV9_OCC_COMMON_AREA_BASE; @@ -332,13 +338,19 @@ static const MemoryRegionOps pnv_homer_power9_pba_ops= =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static hwaddr pnv_homer_power9_get_base(PnvChip *chip) +{ + return PNV9_HOMER_BASE(chip); +} + static void pnv_homer_power9_class_init(ObjectClass *klass, void *data) { PnvHomerClass *homer =3D PNV_HOMER_CLASS(klass); =20 + homer->get_base =3D pnv_homer_power9_get_base; + homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV9_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power9_pba_ops; - homer->homer_size =3D PNV9_HOMER_SIZE; homer->homer_ops =3D &pnv_power9_homer_ops; homer->core_max_base =3D PNV9_CORE_MAX_BASE; } @@ -354,16 +366,16 @@ static uint64_t pnv_homer_power10_pba_read(void *opaq= ue, hwaddr addr, unsigned size) { PnvHomer *homer =3D PNV_HOMER(opaque); - PnvChip *chip =3D homer->chip; + PnvHomerClass *hmrc =3D PNV_HOMER_GET_CLASS(homer); uint32_t reg =3D addr >> 3; uint64_t val =3D 0; =20 switch (reg) { case PBA_BAR0: - val =3D PNV10_HOMER_BASE(chip); + val =3D homer->base; break; case PBA_BARMASK0: /* P10 homer region mask */ - val =3D (PNV10_HOMER_SIZE - 1) & 0x300000; + val =3D (hmrc->size - 1) & 0x300000; break; case PBA_BAR2: /* P10 occ common area */ val =3D PNV10_OCC_COMMON_AREA_BASE; @@ -395,13 +407,19 @@ static const MemoryRegionOps pnv_homer_power10_pba_op= s =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static hwaddr pnv_homer_power10_get_base(PnvChip *chip) +{ + return PNV10_HOMER_BASE(chip); +} + static void pnv_homer_power10_class_init(ObjectClass *klass, void *data) { PnvHomerClass *homer =3D PNV_HOMER_CLASS(klass); =20 + homer->get_base =3D pnv_homer_power10_get_base; + homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV10_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power10_pba_ops; - homer->homer_size =3D PNV10_HOMER_SIZE; homer->homer_ops =3D &pnv_power9_homer_ops; /* TODO */ homer->core_max_base =3D PNV9_CORE_MAX_BASE; } @@ -424,9 +442,11 @@ static void pnv_homer_realize(DeviceState *dev, Error = **errp) homer, "xscom-pba", hmrc->pba_size); =20 /* homer region */ + homer->base =3D hmrc->get_base(homer->chip); + memory_region_init_io(&homer->regs, OBJECT(dev), hmrc->homer_ops, homer, "homer-main-memory", - hmrc->homer_size); + hmrc->size); } =20 static Property pnv_homer_properties[] =3D { --=20 2.45.2 From nobody Tue Apr 15 22:27:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1733800001; cv=none; d=zohomail.com; s=zohoarc; b=Rd7PSho+9iZDbj1ihBcB3UbvjQN3Py/URRw4ANW5a9O/aeeFdbEMb1X4iJj1WR/EaSt3byfe9p8AyzvDEMNparW9J2edq0VELovgTB/Bo/V3Uuotg87FP+t/Q4f3DaQQx+c61bgyHDLalgEOmcz0ryO2K4p+3lCKaW43kFar7FE= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733800001554116600 Content-Type: text/plain; charset="utf-8" Use defines for the OCCMISC register bits, and add a comment about the IRQ request bit, which QEMU may not model quite correctly. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index c6681a035a7..5424d87ee97 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -30,6 +30,7 @@ #define OCB_OCI_OCCMISC 0x4020 #define OCB_OCI_OCCMISC_AND 0x4021 #define OCB_OCI_OCCMISC_OR 0x4022 +#define OCCMISC_PSI_IRQ PPC_BIT(0) =20 /* OCC sensors */ #define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 @@ -50,13 +51,16 @@ =20 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) { - bool irq_state; - - val &=3D 0xffff000000000000ull; + val &=3D PPC_BITMASK(0, 18); /* Mask out unimplemented bits */ =20 occ->occmisc =3D val; - irq_state =3D !!(val >> 63); - qemu_set_irq(occ->psi_irq, irq_state); + + /* + * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear + * how that is handled in PSI so it is level-triggered here, which is = not + * really correct (but skiboot is okay with it). + */ + qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); 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Mon, 09 Dec 2024 19:05:17 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH 6/9] ppc/pnv: Make HOMER memory a RAM region Date: Tue, 10 Dec 2024 13:04:46 +1000 Message-ID: <20241210030451.1306608-7-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241210030451.1306608-1-npiggin@gmail.com> References: <20241210030451.1306608-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=npiggin@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733799977771116600 The HOMER is a region of memory used by host and firmware and microconrollers. It has very little logic by itself, just some BAR registers. Users of this memory should operate on it rather than have HOMER implement them with MMIO registers, which is not the right model. This change switches the implementation of HOMER from MMIO to RAM, and moves the OCC register implementation to in-memory structure accesses performed by the OCC model. This has the downside that access to unimplemented regions of HOMER are no longer flagged. Perhaps that could be done by adding a memory region for HOMER, and ram subregions under that for each implemented part. But for now this takes the simpler approach. Note: This brings some data structure definitions from skiboot, which does not match QEMU coding style but is not changed to make comparisons and updates simpler. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_homer.h | 5 +- include/hw/ppc/pnv_occ.h | 6 + hw/ppc/pnv.c | 87 ++++---- hw/ppc/pnv_homer.c | 203 +---------------- hw/ppc/pnv_occ.c | 433 ++++++++++++++++++++++++++++++++++++- 5 files changed, 488 insertions(+), 246 deletions(-) diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h index 5ffc0c97afe..a6f2710fa16 100644 --- a/include/hw/ppc/pnv_homer.h +++ b/include/hw/ppc/pnv_homer.h @@ -41,7 +41,7 @@ struct PnvHomer { =20 PnvChip *chip; MemoryRegion pba_regs; - MemoryRegion regs; + MemoryRegion mem; hwaddr base; }; =20 @@ -56,9 +56,6 @@ struct PnvHomerClass { =20 int pba_size; const MemoryRegionOps *pba_ops; - const MemoryRegionOps *homer_ops; - - hwaddr core_max_base; }; =20 #endif /* PPC_PNV_HOMER_H */ diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index df321244e3b..f9948609808 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -46,6 +46,9 @@ struct PnvOCC { =20 qemu_irq psi_irq; =20 + /* OCCs operate on regions of HOMER memory */ + PnvHomer *homer; + MemoryRegion xscom_regs; MemoryRegion sram_regs; }; @@ -53,6 +56,9 @@ struct PnvOCC { struct PnvOCCClass { DeviceClass parent_class; =20 + hwaddr opal_shared_memory_offset; /* offset in HOMER */ + uint8_t opal_shared_memory_version; + int xscom_size; const MemoryRegionOps *xscom_ops; }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f0f0d7567da..ef26eedefd6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1556,19 +1556,7 @@ static void pnv_chip_power8_realize(DeviceState *dev= , Error **errp) return; } =20 - /* Create the simplified OCC model */ - if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { - return; - } - pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); - qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, - qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); - - /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(c= hip), - &chip8->occ.sram_regs); - - /* HOMER */ + /* HOMER (must be created before OCC) */ object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), &error_abort); if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { @@ -1576,10 +1564,19 @@ static void pnv_chip_power8_realize(DeviceState *de= v, Error **errp) } /* Homer Xscom region */ pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_re= gs); + /* Homer RAM region */ + memory_region_add_subregion(get_system_memory(), chip8->homer.base, + &chip8->homer.mem); =20 - /* Homer mmio region */ - memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), - &chip8->homer.regs); + /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip8->occ), "homer", + OBJECT(&chip8->homer), &error_abort); + if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_re= gs); + qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, + qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); =20 /* PHB controllers */ for (i =3D 0; i < chip8->num_phbs; i++) { @@ -1860,18 +1857,6 @@ static void pnv_chip_power9_realize(DeviceState *dev= , Error **errp) pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, &chip9->chiptod.xscom_regs); =20 - /* Create the simplified OCC model */ - if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { - return; - } - pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_r= egs); - qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( - DEVICE(psi9), PSIHB9_IRQ_OCC)); - - /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(= chip), - &chip9->occ.sram_regs); - /* SBE */ if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { return; @@ -1883,7 +1868,7 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( DEVICE(psi9), PSIHB9_IRQ_PSU)); =20 - /* HOMER */ + /* HOMER (must be created before OCC) */ object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), &error_abort); if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { @@ -1891,10 +1876,19 @@ static void pnv_chip_power9_realize(DeviceState *de= v, Error **errp) } /* Homer Xscom region */ pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_r= egs); + /* Homer RAM region */ + memory_region_add_subregion(get_system_memory(), chip9->homer.base, + &chip9->homer.mem); =20 - /* Homer mmio region */ - memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), - &chip9->homer.regs); + /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip9->occ), "homer", + OBJECT(&chip9->homer), &error_abort); + if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_r= egs); + qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( + DEVICE(psi9), PSIHB9_IRQ_OCC)); =20 /* PEC PHBs */ pnv_chip_power9_pec_realize(chip, &local_err); @@ -2137,7 +2131,22 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, &chip10->chiptod.xscom_regs); =20 + /* HOMER (must be created before OCC) */ + object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), + &error_abort); + if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { + return; + } + /* Homer Xscom region */ + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, + &chip10->homer.pba_regs); + /* Homer RAM region */ + memory_region_add_subregion(get_system_memory(), chip10->homer.base, + &chip10->homer.mem); + /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip10->occ), "homer", + OBJECT(&chip10->homer), &error_abort); if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { return; } @@ -2162,20 +2171,6 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); =20 - /* HOMER */ - object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), - &error_abort); - if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { - return; - } - /* Homer Xscom region */ - pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, - &chip10->homer.pba_regs); - - /* Homer mmio region */ - memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip= ), - &chip10->homer.regs); - /* N1 chiplet */ if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { return; diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index fda022adfc3..9d6218f4bc4 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -29,101 +29,6 @@ #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_xscom.h" =20 - -static bool core_max_array(PnvHomer *homer, hwaddr addr) -{ - int i; - PnvHomerClass *hmrc =3D PNV_HOMER_GET_CLASS(homer); - - for (i =3D 0; i <=3D homer->chip->nr_cores; i++) { - if (addr =3D=3D (hmrc->core_max_base + i)) { - return true; - } - } - return false; -} - -/* P8 Pstate table */ - -#define PNV8_OCC_PSTATE_VERSION 0x1f8001 -#define PNV8_OCC_PSTATE_MIN 0x1f8003 -#define PNV8_OCC_PSTATE_VALID 0x1f8000 -#define PNV8_OCC_PSTATE_THROTTLE 0x1f8002 -#define PNV8_OCC_PSTATE_NOM 0x1f8004 -#define PNV8_OCC_PSTATE_TURBO 0x1f8005 -#define PNV8_OCC_PSTATE_ULTRA_TURBO 0x1f8006 -#define PNV8_OCC_PSTATE_DATA 0x1f8008 -#define PNV8_OCC_PSTATE_ID_ZERO 0x1f8010 -#define PNV8_OCC_PSTATE_ID_ONE 0x1f8018 -#define PNV8_OCC_PSTATE_ID_TWO 0x1f8020 -#define PNV8_OCC_VDD_VOLTAGE_IDENTIFIER 0x1f8012 -#define PNV8_OCC_VCS_VOLTAGE_IDENTIFIER 0x1f8013 -#define PNV8_OCC_PSTATE_ZERO_FREQUENCY 0x1f8014 -#define PNV8_OCC_PSTATE_ONE_FREQUENCY 0x1f801c -#define PNV8_OCC_PSTATE_TWO_FREQUENCY 0x1f8024 -#define PNV8_CORE_MAX_BASE 0x1f8810 - - -static uint64_t pnv_power8_homer_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvHomer *homer =3D PNV_HOMER(opaque); - - switch (addr) { - case PNV8_OCC_PSTATE_VALID: - return 1; - case PNV8_OCC_PSTATE_THROTTLE: - return 0; - case PNV8_OCC_PSTATE_VERSION: - return 0x02; - case PNV8_OCC_PSTATE_MIN: - return -2; - case PNV8_OCC_PSTATE_NOM: - case PNV8_OCC_PSTATE_TURBO: - return -1; - case PNV8_OCC_PSTATE_ULTRA_TURBO: - return 0; - case PNV8_OCC_PSTATE_ID_ZERO: - return 0; - case PNV8_OCC_VDD_VOLTAGE_IDENTIFIER: - case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER: - return 1; - case PNV8_OCC_PSTATE_DATA: - return 0; - /* P8 frequency for 0, 1, and 2 pstates */ - case PNV8_OCC_PSTATE_ZERO_FREQUENCY: - case PNV8_OCC_PSTATE_ONE_FREQUENCY: - case PNV8_OCC_PSTATE_TWO_FREQUENCY: - return 3000; - case PNV8_OCC_PSTATE_ID_ONE: - return -1; - case PNV8_OCC_PSTATE_ID_TWO: - return -2; - } - /* pstate table core max array */ - if (core_max_array(homer, addr)) { - return 1; - } - return 0; -} - -static void pnv_power8_homer_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - /* callback function defined to homer write */ - return; -} - -static const MemoryRegionOps pnv_power8_homer_ops =3D { - .read =3D pnv_power8_homer_read, - .write =3D pnv_power8_homer_write, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 1, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - /* P8 PBA BARs */ #define PBA_BAR0 0x00 #define PBA_BAR1 0x01 @@ -192,8 +97,6 @@ static void pnv_homer_power8_class_init(ObjectClass *kla= ss, void *data) homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power8_pba_ops; - homer->homer_ops =3D &pnv_power8_homer_ops; - homer->core_max_base =3D PNV8_CORE_MAX_BASE; } =20 static const TypeInfo pnv_homer_power8_type_info =3D { @@ -203,96 +106,6 @@ static const TypeInfo pnv_homer_power8_type_info =3D { .class_init =3D pnv_homer_power8_class_init, }; =20 -/* P9 Pstate table */ - -#define PNV9_OCC_PSTATE_VALID 0xe2000 -#define PNV9_OCC_PSTATE_ID_ZERO 0xe2018 -#define PNV9_OCC_PSTATE_ID_ONE 0xe2020 -#define PNV9_OCC_PSTATE_ID_TWO 0xe2028 -#define PNV9_OCC_PSTATE_DATA 0xe2000 -#define PNV9_OCC_PSTATE_MINOR_VERSION 0xe2008 -#define PNV9_OCC_PSTATE_MIN 0xe2003 -#define PNV9_OCC_PSTATE_NOM 0xe2004 -#define PNV9_OCC_PSTATE_TURBO 0xe2005 -#define PNV9_OCC_PSTATE_ULTRA_TURBO 0xe2818 -#define PNV9_OCC_MAX_PSTATE_ULTRA_TURBO 0xe2006 -#define PNV9_OCC_PSTATE_MAJOR_VERSION 0xe2001 -#define PNV9_OCC_OPAL_RUNTIME_DATA 0xe2b85 -#define PNV9_CHIP_HOMER_IMAGE_POINTER 0x200008 -#define PNV9_CHIP_HOMER_BASE 0x0 -#define PNV9_OCC_PSTATE_ZERO_FREQUENCY 0xe201c -#define PNV9_OCC_PSTATE_ONE_FREQUENCY 0xe2024 -#define PNV9_OCC_PSTATE_TWO_FREQUENCY 0xe202c -#define PNV9_OCC_ROLE_MASTER_OR_SLAVE 0xe2002 -#define PNV9_CORE_MAX_BASE 0xe2819 -#define PNV9_DYNAMIC_DATA_STATE 0xe2b80 - -static uint64_t pnv_power9_homer_read(void *opaque, hwaddr addr, - unsigned size) -{ - PnvHomer *homer =3D PNV_HOMER(opaque); - - switch (addr) { - case PNV9_OCC_PSTATE_VALID: - return 1; - case PNV9_OCC_MAX_PSTATE_ULTRA_TURBO: - case PNV9_OCC_PSTATE_ID_ZERO: - return 0; - case PNV9_OCC_ROLE_MASTER_OR_SLAVE: - if (homer->chip->chip_id =3D=3D 0) { - return 0x1; /* master */ - } else { - return 0x0; /* slave */ - } - case PNV9_OCC_PSTATE_NOM: - case PNV9_OCC_PSTATE_TURBO: - case PNV9_OCC_PSTATE_ID_ONE: - case PNV9_OCC_PSTATE_ULTRA_TURBO: - case PNV9_OCC_OPAL_RUNTIME_DATA: - return 1; - case PNV9_OCC_PSTATE_MIN: - case PNV9_OCC_PSTATE_ID_TWO: - return 2; - - /* 3000 khz frequency for 0, 1, and 2 pstates */ - case PNV9_OCC_PSTATE_ZERO_FREQUENCY: - case PNV9_OCC_PSTATE_ONE_FREQUENCY: - case PNV9_OCC_PSTATE_TWO_FREQUENCY: - return 3000; - case PNV9_OCC_PSTATE_MAJOR_VERSION: - return 0x90; - case PNV9_OCC_PSTATE_MINOR_VERSION: - return 0x01; - case PNV9_CHIP_HOMER_BASE: - case PNV9_CHIP_HOMER_IMAGE_POINTER: - return 0; - case PNV9_DYNAMIC_DATA_STATE: - return 0x03; /* active */ - } - /* pstate table core max array */ - if (core_max_array(homer, addr)) { - return 1; - } - return 0; -} - -static void pnv_power9_homer_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - /* callback function defined to homer write */ - return; -} - -static const MemoryRegionOps pnv_power9_homer_ops =3D { - .read =3D pnv_power9_homer_read, - .write =3D pnv_power9_homer_write, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 8, - .impl.min_access_size =3D 1, - .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr, unsigned size) { @@ -351,8 +164,6 @@ static void pnv_homer_power9_class_init(ObjectClass *kl= ass, void *data) homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV9_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power9_pba_ops; - homer->homer_ops =3D &pnv_power9_homer_ops; - homer->core_max_base =3D PNV9_CORE_MAX_BASE; } =20 static const TypeInfo pnv_homer_power9_type_info =3D { @@ -420,8 +231,6 @@ static void pnv_homer_power10_class_init(ObjectClass *k= lass, void *data) homer->size =3D PNV_HOMER_SIZE; homer->pba_size =3D PNV10_XSCOM_PBA_SIZE; homer->pba_ops =3D &pnv_homer_power10_pba_ops; - homer->homer_ops =3D &pnv_power9_homer_ops; /* TODO */ - homer->core_max_base =3D PNV9_CORE_MAX_BASE; } =20 static const TypeInfo pnv_homer_power10_type_info =3D { @@ -435,18 +244,22 @@ static void pnv_homer_realize(DeviceState *dev, Error= **errp) { PnvHomer *homer =3D PNV_HOMER(dev); PnvHomerClass *hmrc =3D PNV_HOMER_GET_CLASS(homer); + char homer_str[32]; =20 assert(homer->chip); =20 pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops, homer, "xscom-pba", hmrc->pba_size); =20 - /* homer region */ + /* Homer RAM region */ homer->base =3D hmrc->get_base(homer->chip); =20 - memory_region_init_io(&homer->regs, OBJECT(dev), - hmrc->homer_ops, homer, "homer-main-memory", - hmrc->size); + snprintf(homer_str, sizeof(homer_str), "homer-chip%d->memory", + homer->chip->chip_id); + if (!memory_region_init_ram(&homer->mem, OBJECT(homer), + homer_str, hmrc->size, errp)) { + return; + } } =20 static Property pnv_homer_properties[] =3D { diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 5424d87ee97..918b08ba2ff 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -24,9 +24,13 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_occ.h" =20 +#define P8_HOMER_OPAL_DATA_OFFSET 0x1F8000 +#define P9_HOMER_OPAL_DATA_OFFSET 0x0E2000 + #define OCB_OCI_OCCMISC 0x4020 #define OCB_OCI_OCCMISC_AND 0x4021 #define OCB_OCI_OCCMISC_OR 0x4022 @@ -166,7 +170,11 @@ const MemoryRegionOps pnv_occ_sram_ops =3D { static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) { PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->desc =3D "PowerNV OCC Controller (POWER8)"; + poc->opal_shared_memory_offset =3D P8_HOMER_OPAL_DATA_OFFSET; + poc->opal_shared_memory_version =3D 0x02; poc->xscom_size =3D PNV_XSCOM_OCC_SIZE; poc->xscom_ops =3D &pnv_occ_power8_xscom_ops; } @@ -239,8 +247,11 @@ static void pnv_occ_power9_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->desc =3D "PowerNV OCC Controller (POWER9)"; + poc->opal_shared_memory_offset =3D P9_HOMER_OPAL_DATA_OFFSET; + poc->opal_shared_memory_version =3D 0x90; poc->xscom_size =3D PNV9_XSCOM_OCC_SIZE; poc->xscom_ops =3D &pnv_occ_power9_xscom_ops; + assert(!dc->user_creatable); } =20 static const TypeInfo pnv_occ_power9_type_info =3D { @@ -263,10 +274,19 @@ static const TypeInfo pnv_occ_power10_type_info =3D { .class_init =3D pnv_occ_power10_class_init, }; =20 +static bool occ_init_homer_memory(PnvOCC *occ, Error **errp); + static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ =3D PNV_OCC(dev); PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); + PnvHomer *homer =3D occ->homer; + + assert(homer); + + if (!occ_init_homer_memory(occ, errp)) { + return; + } =20 occ->occmisc =3D 0; =20 @@ -282,12 +302,17 @@ static void pnv_occ_realize(DeviceState *dev, Error *= *errp) qdev_init_gpio_out(dev, &occ->psi_irq, 1); } =20 +static Property pnv_occ_properties[] =3D { + DEFINE_PROP_LINK("homer", PnvOCC, homer, TYPE_PNV_HOMER, PnvHomer *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_occ_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D pnv_occ_realize; - dc->desc =3D "PowerNV OCC Controller"; + device_class_set_props(dc, pnv_occ_properties); dc->user_creatable =3D false; } =20 @@ -309,3 +334,409 @@ static void pnv_occ_register_types(void) } =20 type_init(pnv_occ_register_types); + +/* From skiboot/hw/occ.c */ +/* OCC Communication Area for PStates */ + +#define OPAL_DYNAMIC_DATA_OFFSET 0x0B80 +/* relative to HOMER_OPAL_DATA_OFFSET */ + +#define MAX_PSTATES 256 +#define MAX_P8_CORES 12 +#define MAX_P9_CORES 24 +#define MAX_P10_CORES 32 + +#define MAX_OPAL_CMD_DATA_LENGTH 4090 +#define MAX_OCC_RSP_DATA_LENGTH 8698 + +#define P8_PIR_CORE_MASK 0xFFF8 +#define P9_PIR_QUAD_MASK 0xFFF0 +#define P10_PIR_CHIP_MASK 0x0000 +#define FREQ_MAX_IN_DOMAIN 0 +#define FREQ_MOST_RECENTLY_SET 1 + +#define u8 uint8_t +#define s8 int8_t +#define u16 uint16_t +#define s16 int16_t +#define u32 uint32_t +#define s32 int32_t +#define u64 uint64_t +#define s64 int64_t +#define __packed QEMU_PACKED + +/** + * OCC-OPAL Shared Memory Region + * + * Reference document : + * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Inter= faces.pdf + * + * Supported layout versions: + * - 0x01, 0x02 : P8 + * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_psta= te.h + * + * - 0x90 : P9 + * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pst= ate.h + * In 0x90 the data is separated into :- + * -- Static Data (struct occ_pstate_table): Data is written once by OCC + * -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime + * + * struct occ_pstate_table - Pstate table layout + * @valid: Indicates if data is valid + * @version: Layout version [Major/Minor] + * @v2.throttle: Reason for limiting the max pstate + * @v9.occ_role: OCC role (Master/Slave) + * @v#.pstate_min: Minimum pstate ever allowed + * @v#.pstate_nom: Nominal pstate + * @v#.pstate_turbo: Maximum turbo pstate + * @v#.pstate_ultra_turbo: Maximum ultra turbo pstate and the maximum + * pstate ever allowed + * @v#.pstates: Pstate-id and frequency list from Pmax to Pmin + * @v#.pstates.id: Pstate-id + * @v#.pstates.flags: Pstate-flag(reserved) + * @v2.pstates.vdd: Voltage Identifier + * @v2.pstates.vcs: Voltage Identifier + * @v#.pstates.freq_khz: Frequency in KHz + * @v#.core_max[1..N]: Max pstate with N active cores + * @spare/reserved/pad: Unused data + */ +struct occ_pstate_table { + u8 valid; + u8 version; + union __packed { + struct __packed { /* Version 0x01 and 0x02 */ + u8 throttle; + s8 pstate_min; + s8 pstate_nom; + s8 pstate_turbo; + s8 pstate_ultra_turbo; + u8 spare; + u64 reserved; + struct __packed { + s8 id; + u8 flags; + u8 vdd; + u8 vcs; + __be32 freq_khz; + } pstates[MAX_PSTATES]; + s8 core_max[MAX_P8_CORES]; + u8 pad[100]; + } v2; + struct __packed { /* Version 0x90 */ + u8 occ_role; + u8 pstate_min; + u8 pstate_nom; + u8 pstate_turbo; + u8 pstate_ultra_turbo; + u8 spare; + u64 reserved1; + u64 reserved2; + struct __packed { + u8 id; + u8 flags; + u16 reserved; + __be32 freq_khz; + } pstates[MAX_PSTATES]; + u8 core_max[MAX_P9_CORES]; + u8 pad[56]; + } v9; + struct __packed { /* Version 0xA0 */ + u8 occ_role; + u8 pstate_min; + u8 pstate_fixed_freq; + u8 pstate_base; + u8 pstate_ultra_turbo; + u8 pstate_fmax; + u8 minor; + u8 pstate_bottom_throttle; + u8 spare; + u8 spare1; + u32 reserved_32; + u64 reserved_64; + struct __packed { + u8 id; + u8 valid; + u16 reserved; + __be32 freq_khz; + } pstates[MAX_PSTATES]; + u8 core_max[MAX_P10_CORES]; + u8 pad[48]; + } v10; + }; +} __packed; + +/** + * OPAL-OCC Command Response Interface + * + * OPAL-OCC Command Buffer + * + * --------------------------------------------------------------------- + * | OPAL | Cmd | OPAL | | Cmd Data | Cmd Data | OPAL | + * | Cmd | Request | OCC | Reserved | Length | Length | Cmd | + * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | + * --------------------------------------------------------------------- + * | =E2=80=A6.OPAL Command Data up to max of Cmd Data Length 4090 bytes = | + * | | + * --------------------------------------------------------------------- + * + * OPAL Command Flag + * + * ----------------------------------------------------------------- + * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | + * | (msb) | | | | | | | (lsb) | + * ----------------------------------------------------------------- + * |Cmd | | | | | | | | + * |Ready | | | | | | | | + * ----------------------------------------------------------------- + * + * struct opal_command_buffer - Defines the layout of OPAL command buffer + * @flag: Provides general status of the command + * @request_id: Token to identify request + * @cmd: Command sent + * @data_size: Command data length + * @data: Command specific data + * @spare: Unused byte + */ +struct opal_command_buffer { + u8 flag; + u8 request_id; + u8 cmd; + u8 spare; + __be16 data_size; + u8 data[MAX_OPAL_CMD_DATA_LENGTH]; +} __packed; + +/** + * OPAL-OCC Response Buffer + * + * --------------------------------------------------------------------- + * | OCC | Cmd | OPAL | Response | Rsp Data | Rsp Data | OPAL | + * | Rsp | Request | OCC | Status | Length | Length | Rsp | + * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | + * --------------------------------------------------------------------- + * | =E2=80=A6.OPAL Response Data up to max of Rsp Data Length 8698 bytes= | + * | | + * --------------------------------------------------------------------- + * + * OCC Response Flag + * + * ----------------------------------------------------------------- + * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | + * | (msb) | | | | | | | (lsb) | + * ----------------------------------------------------------------- + * | | | | | | |OCC in | Rsp | + * | | | | | | |progress|Ready | + * ----------------------------------------------------------------- + * + * struct occ_response_buffer - Defines the layout of OCC response buffer + * @flag: Provides general status of the response + * @request_id: Token to identify request + * @cmd: Command requested + * @status: Indicates success/failure status of + * the command + * @data_size: Response data length + * @data: Response specific data + */ +struct occ_response_buffer { + u8 flag; + u8 request_id; + u8 cmd; + u8 status; + __be16 data_size; + u8 data[MAX_OCC_RSP_DATA_LENGTH]; +} __packed; + +/** + * OCC-OPAL Shared Memory Interface Dynamic Data Vx90 + * + * struct occ_dynamic_data - Contains runtime attributes + * @occ_state: Current state of OCC + * @major_version: Major version number + * @minor_version: Minor version number (backwards compatible) + * Version 1 indicates GPU presence populated + * @gpus_present: Bitmask of GPUs present (on systems where GPU + * presence is detected through APSS) + * @cpu_throttle: Reason for limiting the max pstate + * @mem_throttle: Reason for throttling memory + * @quick_pwr_drop: Indicates if QPD is asserted + * @pwr_shifting_ratio: Indicates the current percentage of power to + * take away from the CPU vs GPU when shifting + * power to maintain a power cap. Value of 100 + * means take all power from CPU. + * @pwr_cap_type: Indicates type of power cap in effect + * @hard_min_pwr_cap: Hard minimum system power cap in Watts. + * Guaranteed unless hardware failure + * @max_pwr_cap: Maximum allowed system power cap in Watts + * @cur_pwr_cap: Current system power cap + * @soft_min_pwr_cap: Soft powercap minimum. OCC may or may not be + * able to maintain this + * @spare/reserved: Unused data + * @cmd: Opal Command Buffer + * @rsp: OCC Response Buffer + */ +struct occ_dynamic_data { + u8 occ_state; + u8 major_version; + u8 minor_version; + u8 gpus_present; + union __packed { + struct __packed { /* Version 0x90 */ + u8 spare1; + } v9; + struct __packed { /* Version 0xA0 */ + u8 wof_enabled; + } v10; + }; + u8 cpu_throttle; + u8 mem_throttle; + u8 quick_pwr_drop; + u8 pwr_shifting_ratio; + u8 pwr_cap_type; + __be16 hard_min_pwr_cap; + __be16 max_pwr_cap; + __be16 cur_pwr_cap; + __be16 soft_min_pwr_cap; + u8 pad[110]; + struct opal_command_buffer cmd; + struct occ_response_buffer rsp; +} __packed; + +enum occ_response_status { + OCC_RSP_SUCCESS =3D 0x00, + OCC_RSP_INVALID_COMMAND =3D 0x11, + OCC_RSP_INVALID_CMD_DATA_LENGTH =3D 0x12, + OCC_RSP_INVALID_DATA =3D 0x13, + OCC_RSP_INTERNAL_ERROR =3D 0x15, +}; + +#define OCC_ROLE_SLAVE 0x00 +#define OCC_ROLE_MASTER 0x01 + +#define OCC_FLAG_RSP_READY 0x01 +#define OCC_FLAG_CMD_IN_PROGRESS 0x02 +#define OPAL_FLAG_CMD_READY 0x80 + +#define PCAP_MAX_POWER_W 100 +#define PCAP_SOFT_MIN_POWER_W 20 +#define PCAP_HARD_MIN_POWER_W 10 + +static bool occ_write_static_data(PnvOCC *occ, + struct occ_pstate_table *static_data, + Error **errp) +{ + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); + PnvHomer *homer =3D occ->homer; + hwaddr static_addr =3D homer->base + poc->opal_shared_memory_offset; + MemTxResult ret; + + ret =3D address_space_write(&address_space_memory, static_addr, + MEMTXATTRS_UNSPECIFIED, static_data, + sizeof(*static_data)); + if (ret !=3D MEMTX_OK) { + error_setg(errp, "OCC: cannot write OCC-OPAL static data"); + return false; + } + + return true; +} + +static bool occ_write_dynamic_data(PnvOCC *occ, + struct occ_dynamic_data *dynamic_data, + Error **errp) +{ + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); + PnvHomer *homer =3D occ->homer; + hwaddr static_addr =3D homer->base + poc->opal_shared_memory_offset; + hwaddr dynamic_addr =3D static_addr + OPAL_DYNAMIC_DATA_OFFSET; + MemTxResult ret; + + ret =3D address_space_write(&address_space_memory, dynamic_addr, + MEMTXATTRS_UNSPECIFIED, dynamic_data, + sizeof(*dynamic_data)); + if (ret !=3D MEMTX_OK) { + error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data"); + return false; + } + + return true; +} + +static bool occ_init_homer_memory(PnvOCC *occ, Error **errp) +{ + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); + PnvHomer *homer =3D occ->homer; + PnvChip *chip =3D homer->chip; + struct occ_pstate_table static_data; + struct occ_dynamic_data dynamic_data; + int i; + + memset(&static_data, 0, sizeof(static_data)); + static_data.valid =3D 1; + static_data.version =3D poc->opal_shared_memory_version; + switch (poc->opal_shared_memory_version) { + case 0x02: + static_data.v2.throttle =3D 0; + static_data.v2.pstate_min =3D -2; + static_data.v2.pstate_nom =3D -1; + static_data.v2.pstate_turbo =3D -1; + static_data.v2.pstate_ultra_turbo =3D 0; + static_data.v2.pstates[0].id =3D 0; + static_data.v2.pstates[1].freq_khz =3D cpu_to_be32(3000); + static_data.v2.pstates[1].id =3D -1; + static_data.v2.pstates[1].freq_khz =3D cpu_to_be32(3000); + static_data.v2.pstates[2].id =3D -2; + static_data.v2.pstates[2].freq_khz =3D cpu_to_be32(3000); + for (i =3D 0; i < chip->nr_cores; i++) { + static_data.v2.core_max[i] =3D 1; + } + break; + case 0x90: + if (chip->chip_id =3D=3D 0) { + static_data.v9.occ_role =3D OCC_ROLE_MASTER; + } else { + static_data.v9.occ_role =3D OCC_ROLE_SLAVE; + } + static_data.v9.pstate_min =3D 2; + static_data.v9.pstate_nom =3D 1; + static_data.v9.pstate_turbo =3D 1; + static_data.v9.pstate_ultra_turbo =3D 0; + static_data.v9.pstates[0].id =3D 0; + static_data.v9.pstates[0].freq_khz =3D cpu_to_be32(3000); + static_data.v9.pstates[1].id =3D 1; + static_data.v9.pstates[1].freq_khz =3D cpu_to_be32(3000); + static_data.v9.pstates[2].id =3D 2; + static_data.v9.pstates[2].freq_khz =3D cpu_to_be32(3000); + for (i =3D 0; i < chip->nr_cores; i++) { + static_data.v9.core_max[i] =3D 1; + } + break; + default: + g_assert_not_reached(); + } + if (!occ_write_static_data(occ, &static_data, errp)) { + return false; + } + + memset(&dynamic_data, 0, sizeof(dynamic_data)); + dynamic_data.occ_state =3D 0x3; /* active */ + dynamic_data.major_version =3D 0x0; + dynamic_data.hard_min_pwr_cap =3D cpu_to_be16(PCAP_HARD_MIN_POWER_W); + dynamic_data.max_pwr_cap =3D cpu_to_be16(PCAP_MAX_POWER_W); + dynamic_data.cur_pwr_cap =3D cpu_to_be16(PCAP_MAX_POWER_W); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=npiggin@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733800056748116600 Content-Type: text/plain; charset="utf-8" Make each pstate have a different frequency, because that's easier to observe and test. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 918b08ba2ff..5567fbf008e 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -681,11 +681,11 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error = **errp) static_data.v2.pstate_turbo =3D -1; static_data.v2.pstate_ultra_turbo =3D 0; static_data.v2.pstates[0].id =3D 0; - static_data.v2.pstates[1].freq_khz =3D cpu_to_be32(3000); + static_data.v2.pstates[1].freq_khz =3D cpu_to_be32(4000); static_data.v2.pstates[1].id =3D -1; static_data.v2.pstates[1].freq_khz =3D cpu_to_be32(3000); static_data.v2.pstates[2].id =3D -2; - static_data.v2.pstates[2].freq_khz =3D cpu_to_be32(3000); + static_data.v2.pstates[2].freq_khz =3D cpu_to_be32(2000); for (i =3D 0; i < chip->nr_cores; i++) { static_data.v2.core_max[i] =3D 1; } @@ -701,11 +701,11 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error = **errp) static_data.v9.pstate_turbo =3D 1; static_data.v9.pstate_ultra_turbo =3D 0; static_data.v9.pstates[0].id =3D 0; - static_data.v9.pstates[0].freq_khz =3D cpu_to_be32(3000); + static_data.v9.pstates[0].freq_khz =3D cpu_to_be32(4000); static_data.v9.pstates[1].id =3D 1; static_data.v9.pstates[1].freq_khz =3D cpu_to_be32(3000); static_data.v9.pstates[2].id =3D 2; - static_data.v9.pstates[2].freq_khz =3D cpu_to_be32(3000); + static_data.v9.pstates[2].freq_khz =3D cpu_to_be32(2000); for (i =3D 0; i < chip->nr_cores; i++) { static_data.v9.core_max[i] =3D 1; } --=20 2.45.2 From nobody Tue Apr 15 22:27:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1733799968; cv=none; d=zohomail.com; s=zohoarc; b=D9iBug8VDkuew0l41E9C0bFyVsGtyMXlMV8SWgS1z+pcSbHHlq0rRufAxe5R/ofcr+h+xu3Q38f7Kb40lKmya8DJq1zMKjQflW0VJFOm81X5kABVeA/obysvigIPrj6ffBCkkA4IOr9XKetx5cAVp9zyIqVS1c/9bZjNt8dXzkk= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733799969945116600 Content-Type: text/plain; charset="utf-8" Add POWER10 OCC-OPAL data format. POWER10 changes major version and adds a few fields. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 5567fbf008e..aa46e118e93 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -263,14 +263,20 @@ static const TypeInfo pnv_occ_power9_type_info =3D { =20 static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) { + PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->desc =3D "PowerNV OCC Controller (POWER10)"; + poc->opal_shared_memory_offset =3D P9_HOMER_OPAL_DATA_OFFSET; + poc->opal_shared_memory_version =3D 0xA0; + poc->xscom_size =3D PNV9_XSCOM_OCC_SIZE; + poc->xscom_ops =3D &pnv_occ_power9_xscom_ops; + assert(!dc->user_creatable); } =20 static const TypeInfo pnv_occ_power10_type_info =3D { .name =3D TYPE_PNV10_OCC, - .parent =3D TYPE_PNV9_OCC, + .parent =3D TYPE_PNV_OCC, .class_init =3D pnv_occ_power10_class_init, }; =20 @@ -710,6 +716,37 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error *= *errp) static_data.v9.core_max[i] =3D 1; } break; + case 0xA0: + if (chip->chip_id =3D=3D 0) { + static_data.v10.occ_role =3D OCC_ROLE_MASTER; + } else { + static_data.v10.occ_role =3D OCC_ROLE_SLAVE; + } + static_data.v10.pstate_min =3D 4; + static_data.v10.pstate_fixed_freq =3D 3; + static_data.v10.pstate_base =3D 2; + static_data.v10.pstate_ultra_turbo =3D 1; + static_data.v10.pstate_fmax =3D 0; + static_data.v10.minor =3D 0x01; + static_data.v10.pstates[0].valid =3D 1; + static_data.v10.pstates[0].id =3D 0; + static_data.v10.pstates[0].freq_khz =3D cpu_to_be32(4200); + static_data.v10.pstates[1].valid =3D 1; + static_data.v10.pstates[1].id =3D 1; + static_data.v10.pstates[1].freq_khz =3D cpu_to_be32(4000); + static_data.v10.pstates[2].valid =3D 1; + static_data.v10.pstates[2].id =3D 2; + static_data.v10.pstates[2].freq_khz =3D cpu_to_be32(3800); + static_data.v10.pstates[3].valid =3D 1; + static_data.v10.pstates[3].id =3D 3; + static_data.v10.pstates[3].freq_khz =3D cpu_to_be32(3000); + static_data.v10.pstates[4].valid =3D 1; + static_data.v10.pstates[4].id =3D 4; + static_data.v10.pstates[4].freq_khz =3D cpu_to_be32(2000); + for (i =3D 0; i < chip->nr_cores; i++) { + static_data.v10.core_max[i] =3D 1; + } + break; default: g_assert_not_reached(); } @@ -725,6 +762,10 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error *= *errp) dynamic_data.cur_pwr_cap =3D cpu_to_be16(PCAP_MAX_POWER_W); dynamic_data.soft_min_pwr_cap =3D cpu_to_be16(PCAP_SOFT_MIN_POWER_W); switch (poc->opal_shared_memory_version) { + case 0xA0: + dynamic_data.minor_version =3D 0x1; + dynamic_data.v10.wof_enabled =3D 0x1; + break; case 0x90: dynamic_data.minor_version =3D 0x1; break; --=20 2.45.2 From nobody Tue Apr 15 22:27:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733800013639116600 Content-Type: text/plain; charset="utf-8" The OCC is an On Chip Controller that handles various thermal and power management. It is a PPC405 microcontroller that runs its own firmware which is out of scope of the powernv machine model. Some dynamic behaviour and interfaces that are important for host CPU testing can be implemented with a much simpler state machine. This change adds a 100ms timer that ticks through a simple state machine that looks for "OCC command requests" coming from host firmware, and responds to them. For now the powercap command is implemented because that is used by OPAL and exported to Linux and is easy to test. $ F=3D/sys/firmware/opal/powercap/system-powercap/powercap-current $ cat $F 100 $ echo 50 | sudo tee $F 50 $ cat $F 50 Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_occ.h | 3 + hw/ppc/pnv_occ.c | 145 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+) diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index f9948609808..3ec42de0ff1 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -41,6 +41,9 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OC= C) struct PnvOCC { DeviceState xd; =20 + /* OCC dynamic model is driven by this timer. */ + QEMUTimer state_machine_timer; + /* OCC Misc interrupt */ uint64_t occmisc; =20 diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index aa46e118e93..11081ecc4b7 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -35,6 +35,7 @@ #define OCB_OCI_OCCMISC_AND 0x4021 #define OCB_OCI_OCCMISC_OR 0x4022 #define OCCMISC_PSI_IRQ PPC_BIT(0) +#define OCCMISC_IRQ_SHMEM PPC_BIT(3) =20 /* OCC sensors */ #define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 @@ -67,6 +68,11 @@ static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); } =20 +static void pnv_occ_raise_msg_irq(PnvOCC *occ) +{ + pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHM= EM); +} + static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, unsigned size) { @@ -281,6 +287,20 @@ static const TypeInfo pnv_occ_power10_type_info =3D { }; =20 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp); +static bool occ_model_tick(PnvOCC *occ); + +/* Relatively arbitrary */ +#define OCC_POLL_MS 100 + +static void occ_state_machine_timer(void *opaque) +{ + PnvOCC *occ =3D opaque; + uint64_t next =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + OCC_POLL_MS; + + if (occ_model_tick(occ)) { + timer_mod(&occ->state_machine_timer, next); + } +} =20 static void pnv_occ_realize(DeviceState *dev, Error **errp) { @@ -306,6 +326,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **= errp) PNV_OCC_SENSOR_DATA_BLOCK_SIZE); =20 qdev_init_gpio_out(dev, &occ->psi_irq, 1); + + timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL, + occ_state_machine_timer, occ); + timer_mod(&occ->state_machine_timer, OCC_POLL_MS); } =20 static Property pnv_occ_properties[] =3D { @@ -646,6 +670,27 @@ static bool occ_write_static_data(PnvOCC *occ, return true; } =20 +static bool occ_read_dynamic_data(PnvOCC *occ, + struct occ_dynamic_data *dynamic_data, + Error **errp) +{ + PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); + PnvHomer *homer =3D occ->homer; + hwaddr static_addr =3D homer->base + poc->opal_shared_memory_offset; + hwaddr dynamic_addr =3D static_addr + OPAL_DYNAMIC_DATA_OFFSET; + MemTxResult ret; + + ret =3D address_space_read(&address_space_memory, dynamic_addr, + MEMTXATTRS_UNSPECIFIED, dynamic_data, + sizeof(*dynamic_data)); + if (ret !=3D MEMTX_OK) { + error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data"); + return false; + } + + return true; +} + static bool occ_write_dynamic_data(PnvOCC *occ, struct occ_dynamic_data *dynamic_data, Error **errp) @@ -667,6 +712,106 @@ static bool occ_write_dynamic_data(PnvOCC *occ, return true; } =20 +static bool occ_opal_send_response(PnvOCC *occ, + struct occ_dynamic_data *dynamic_data, + enum occ_response_status status, + uint8_t *data, uint16_t datalen) +{ + struct opal_command_buffer *cmd =3D &dynamic_data->cmd; + struct occ_response_buffer *rsp =3D &dynamic_data->rsp; + + rsp->request_id =3D cmd->request_id; + rsp->cmd =3D cmd->cmd; + rsp->status =3D status; + rsp->data_size =3D cpu_to_be16(datalen); + if (datalen) { + memcpy(rsp->data, data, datalen); + } + if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { + return false; + } + /* Would be a memory barrier here */ + rsp->flag =3D OCC_FLAG_RSP_READY; + cmd->flag =3D 0; + if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { + return false; + } + + pnv_occ_raise_msg_irq(occ); + + return true; +} + +/* Returns error status */ +static bool occ_opal_process_command(PnvOCC *occ, + struct occ_dynamic_data *dynamic_data) +{ + struct opal_command_buffer *cmd =3D &dynamic_data->cmd; + struct occ_response_buffer *rsp =3D &dynamic_data->rsp; + + if (rsp->flag =3D=3D 0) { + /* Spend one "tick" in the in-progress state */ + rsp->flag =3D OCC_FLAG_CMD_IN_PROGRESS; + return occ_write_dynamic_data(occ, dynamic_data, NULL); + } else if (rsp->flag !=3D OCC_FLAG_CMD_IN_PROGRESS) { + return occ_opal_send_response(occ, dynamic_data, + OCC_RSP_INTERNAL_ERROR, + NULL, 0); + } + + switch (cmd->cmd) { + case 0xD1: /* SET_POWER_CAP */ + uint16_t data; + if (be16_to_cpu(cmd->data_size) !=3D 2) { + return occ_opal_send_response(occ, dynamic_data, + OCC_RSP_INVALID_CMD_DATA_LENGTH, + (uint8_t *)&dynamic_data->cur_pw= r_cap, + 2); + } + data =3D be16_to_cpu(*(uint16_t *)cmd->data); + if (data =3D=3D 0) { /* clear power cap */ + dynamic_data->pwr_cap_type =3D 0x00; /* none */ + data =3D PCAP_MAX_POWER_W; + } else { + dynamic_data->pwr_cap_type =3D 0x02; /* user set in-band */ + if (data < PCAP_HARD_MIN_POWER_W) { + data =3D PCAP_HARD_MIN_POWER_W; + } else if (data > PCAP_MAX_POWER_W) { + data =3D PCAP_MAX_POWER_W; + } + } + dynamic_data->cur_pwr_cap =3D cpu_to_be16(data); + return occ_opal_send_response(occ, dynamic_data, + OCC_RSP_SUCCESS, + (uint8_t *)&dynamic_data->cur_pwr_ca= p, 2); + + default: + return occ_opal_send_response(occ, dynamic_data, + OCC_RSP_INVALID_COMMAND, + NULL, 0); + } + g_assert_not_reached(); +} + +static bool occ_model_tick(PnvOCC *occ) +{ + struct occ_dynamic_data dynamic_data; + + if (!occ_read_dynamic_data(occ, &dynamic_data, NULL)) { + /* Can't move OCC state field to safe because we can't map it! */ + qemu_log("OCC: failed to read HOMER data, shutting down OCC\n"); + return false; + } + if (dynamic_data.cmd.flag =3D=3D OPAL_FLAG_CMD_READY) { + if (!occ_opal_process_command(occ, &dynamic_data)) { + qemu_log("OCC: failed to write HOMER data, shutting down OCC\n= "); + return false; + } + } + + return true; +} + static bool occ_init_homer_memory(PnvOCC *occ, Error **errp) { PnvOCCClass *poc =3D PNV_OCC_GET_CLASS(occ); --=20 2.45.2