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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 01/14] ppc/xive2: Update NVP save/restore for group
attributes
Date: Mon, 9 Dec 2024 18:05:04 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
If the 'H' attribute is set on the NVP structure, the hardware
automatically saves and restores some attributes from the TIMA in the
NVP structure.
The group-specific attributes LSMFB, LGS and T have an extra flag to
individually control what is saved/restored.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive2_regs.h | 10 +++++++---
hw/intc/xive2.c | 23 ++++++++++++++++++-----
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 1d00c8df64..e88d6eab1e 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -1,10 +1,9 @@
/*
* QEMU PowerPC XIVE2 internal structure definitions (POWER10)
*
- * Copyright (c) 2019-2022, IBM Corporation.
+ * Copyright (c) 2019-2024, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#ifndef PPC_XIVE2_REGS_H
@@ -152,6 +151,9 @@ typedef struct Xive2Nvp {
uint32_t w0;
#define NVP2_W0_VALID PPC_BIT32(0)
#define NVP2_W0_HW PPC_BIT32(7)
+#define NVP2_W0_L PPC_BIT32(8)
+#define NVP2_W0_G PPC_BIT32(9)
+#define NVP2_W0_T PPC_BIT32(10)
#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
#define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
uint32_t w1;
@@ -163,6 +165,8 @@ typedef struct Xive2Nvp {
#define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
#define NVP2_W2_IPB PPC_BITMASK32(8, 15)
#define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
+#define NVP2_W2_T PPC_BIT32(27)
+#define NVP2_W2_LGS PPC_BITMASK32(28, 31)
uint32_t w3;
uint32_t w4;
#define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index d1df35e9b3..24e504fce1 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -1,10 +1,9 @@
/*
* QEMU PowerPC XIVE2 interrupt controller model (POWER10)
*
- * Copyright (c) 2019-2022, IBM Corporation..
+ * Copyright (c) 2019-2024, IBM Corporation..
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#include "qemu/osdep.h"
@@ -313,7 +312,19 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, Xiv=
eTCTX *tctx,
=20
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
nvp.w2 =3D xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
- nvp.w2 =3D xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
+ if (nvp.w0 & NVP2_W0_L) {
+ /*
+ * Typically not used. If LSMFB is restored with 0, it will
+ * force a backlog rescan
+ */
+ nvp.w2 =3D xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
+ }
+ if (nvp.w0 & NVP2_W0_G) {
+ nvp.w2 =3D xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]);
+ }
+ if (nvp.w0 & NVP2_W0_T) {
+ nvp.w2 =3D xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]);
+ }
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
=20
nvp.w1 =3D xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
@@ -527,7 +538,9 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *x=
rtr, XiveTCTX *tctx,
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
=20
tctx->regs[TM_QW1_OS + TM_CPPR] =3D cppr;
- /* we don't model LSMFB */
+ tctx->regs[TM_QW1_OS + TM_LSMFB] =3D xive_get_field32(NVP2_W2_LSMFB, n=
vp->w2);
+ tctx->regs[TM_QW1_OS + TM_LGS] =3D xive_get_field32(NVP2_W2_LGS, nvp->=
w2);
+ tctx->regs[TM_QW1_OS + TM_T] =3D xive_get_field32(NVP2_W2_T, nvp->w2);
=20
nvp->w1 =3D xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
nvp->w1 =3D xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 02/14] ppc/xive2: Add grouping level to notification
Date: Mon, 9 Dec 2024 18:05:05 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
The NSR has a (so far unused) grouping level field. When a interrupt
is presented, that field tells the hypervisor or OS if the interrupt
is for an individual VP or for a VP-group/crowd. This patch reworks
the presentation API to allow to set/unset the level when
raising/accepting an interrupt.
It also renames xive_tctx_ipb_update() to xive_tctx_pipr_update() as
the IPB is only used for VP-specific target, whereas the PIPR always
needs to be updated.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive.h | 19 +++++++-
include/hw/ppc/xive_regs.h | 20 +++++++--
hw/intc/xive.c | 90 +++++++++++++++++++++++---------------
hw/intc/xive2.c | 18 ++++----
hw/intc/trace-events | 2 +-
5 files changed, 100 insertions(+), 49 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ebee982528..971da029eb 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -510,6 +510,21 @@ static inline uint8_t xive_priority_to_ipb(uint8_t pri=
ority)
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
=20
+static inline uint8_t xive_priority_to_pipr(uint8_t priority)
+{
+ return priority > XIVE_PRIORITY_MAX ? 0xFF : priority;
+}
+
+/*
+ * Convert an Interrupt Pending Buffer (IPB) register to a Pending
+ * Interrupt Priority Register (PIPR), which contains the priority of
+ * the most favored pending notification.
+ */
+static inline uint8_t xive_ipb_to_pipr(uint8_t ibp)
+{
+ return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
+}
+
/*
* XIVE Thread Interrupt Management Aera (TIMA)
*
@@ -532,8 +547,10 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString =
*buf);
Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
-void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
+void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
+ uint8_t group_level);
void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
+void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level);
=20
/*
* KVM XIVE device helpers
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 326327fc79..b455728c9c 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -146,7 +146,14 @@
#define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line=
*/
/* XXX more... */
=20
-/* NSR fields for the various QW ack types */
+/*
+ * NSR fields for the various QW ack types
+ *
+ * P10 has an extra bit in QW3 for the group level instead of the
+ * reserved 'i' bit. Since it is not used and we don't support group
+ * interrupts on P9, we use the P10 definition for the group level so
+ * that we can have common macros for the NSR
+ */
#define TM_QW0_NSR_EB PPC_BIT8(0)
#define TM_QW1_NSR_EO PPC_BIT8(0)
#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1)
@@ -154,8 +161,15 @@
#define TM_QW3_NSR_HE_POOL 1
#define TM_QW3_NSR_HE_PHYS 2
#define TM_QW3_NSR_HE_LSI 3
-#define TM_QW3_NSR_I PPC_BIT8(2)
-#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7)
+#define TM_NSR_GRP_LVL PPC_BITMASK8(2, 7)
+/*
+ * On P10, the format of the 6-bit group level is: 2 bits for the
+ * crowd size and 4 bits for the group size. Since group/crowd size is
+ * always a power of 2, we encode the log. For example, group_level=3D4
+ * means crowd size =3D 0 and group size =3D 16 (2^4)
+ * Same encoding is used in the NVP and NVGC structures for
+ * PGoFirst and PGoNext fields
+ */
=20
/*
* EAS (Event Assignment Structure)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 245e4d181a..6e73f7b063 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -27,16 +27,6 @@
* XIVE Thread Interrupt Management context
*/
=20
-/*
- * Convert an Interrupt Pending Buffer (IPB) register to a Pending
- * Interrupt Priority Register (PIPR), which contains the priority of
- * the most favored pending notification.
- */
-static uint8_t ipb_to_pipr(uint8_t ibp)
-{
- return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
-}
-
static uint8_t exception_mask(uint8_t ring)
{
switch (ring) {
@@ -87,10 +77,17 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_=
t ring)
=20
regs[TM_CPPR] =3D cppr;
=20
- /* Reset the pending buffer bit */
- alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr);
+ /*
+ * If the interrupt was for a specific VP, reset the pending
+ * buffer bit, otherwise clear the logical server indicator
+ */
+ if (regs[TM_NSR] & TM_NSR_GRP_LVL) {
+ regs[TM_NSR] &=3D ~TM_NSR_GRP_LVL;
+ } else {
+ alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr);
+ }
=20
- /* Drop Exception bit */
+ /* Drop the exception bit */
regs[TM_NSR] &=3D ~mask;
=20
trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring,
@@ -101,7 +98,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t=
ring)
return ((uint64_t)nsr << 8) | regs[TM_CPPR];
}
=20
-static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
+void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
{
/* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
@@ -111,13 +108,13 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t =
ring)
if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) {
switch (ring) {
case TM_QW1_OS:
- regs[TM_NSR] |=3D TM_QW1_NSR_EO;
+ regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F);
break;
case TM_QW2_HV_POOL:
- alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6);
+ alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6) | (group_level =
& 0x3F);
break;
case TM_QW3_HV_PHYS:
- regs[TM_NSR] |=3D (TM_QW3_NSR_HE_PHYS << 6);
+ regs[TM_NSR] =3D (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x=
3F);
break;
default:
g_assert_not_reached();
@@ -159,7 +156,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t =
ring, uint8_t cppr)
* Recompute the PIPR based on local pending interrupts. The PHYS
* ring must take the minimum of both the PHYS and POOL PIPR values.
*/
- pipr_min =3D ipb_to_pipr(regs[TM_IPB]);
+ pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]);
ring_min =3D ring;
=20
/* PHYS updates also depend on POOL values */
@@ -169,7 +166,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t =
ring, uint8_t cppr)
/* POOL values only matter if POOL ctx is valid */
if (pool_regs[TM_WORD2] & 0x80) {
=20
- uint8_t pool_pipr =3D ipb_to_pipr(pool_regs[TM_IPB]);
+ uint8_t pool_pipr =3D xive_ipb_to_pipr(pool_regs[TM_IPB]);
=20
/*
* Determine highest priority interrupt and
@@ -185,17 +182,27 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_=
t ring, uint8_t cppr)
regs[TM_PIPR] =3D pipr_min;
=20
/* CPPR has changed, check if we need to raise a pending exception */
- xive_tctx_notify(tctx, ring_min);
+ xive_tctx_notify(tctx, ring_min, 0);
}
=20
-void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
-{
+void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
+ uint8_t group_level)
+ {
+ /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
+ uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
+ uint8_t *alt_regs =3D &tctx->regs[alt_ring];
uint8_t *regs =3D &tctx->regs[ring];
=20
- regs[TM_IPB] |=3D ipb;
- regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]);
- xive_tctx_notify(tctx, ring);
-}
+ if (group_level =3D=3D 0) {
+ /* VP-specific */
+ regs[TM_IPB] |=3D xive_priority_to_ipb(priority);
+ alt_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]);
+ } else {
+ /* VP-group */
+ alt_regs[TM_PIPR] =3D xive_priority_to_pipr(priority);
+ }
+ xive_tctx_notify(tctx, ring, group_level);
+ }
=20
/*
* XIVE Thread Interrupt Management Area (TIMA)
@@ -411,13 +418,13 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, X=
iveTCTX *tctx,
}
=20
/*
- * Adjust the IPB to allow a CPU to process event queues of other
+ * Adjust the PIPR to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned=
size)
{
- xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xf=
f));
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0);
}
=20
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@@ -495,16 +502,20 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X=
iveTCTX *tctx,
/* Reset the NVT value */
nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
- }
+
+ uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
+ regs[TM_IPB] |=3D ipb;
+}
+
/*
- * Always call xive_tctx_ipb_update(). Even if there were no
+ * Always call xive_tctx_pipr_update(). Even if there were no
* escalation triggered, there could be a pending interrupt which
* was saved when the context was pulled and that we need to take
* into account by recalculating the PIPR (which is not
* saved/restored).
* It will also raise the External interrupt signal if needed.
*/
- xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */
}
=20
/*
@@ -841,9 +852,9 @@ void xive_tctx_reset(XiveTCTX *tctx)
* CPPR is first set.
*/
tctx->regs[TM_QW1_OS + TM_PIPR] =3D
- ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
+ xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =3D
- ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
+ xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
}
=20
static void xive_tctx_realize(DeviceState *dev, Error **errp)
@@ -1660,6 +1671,12 @@ static uint32_t xive_tctx_hw_cam_line(XivePresenter =
*xptr, XiveTCTX *tctx)
return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
=20
+static uint8_t xive_get_group_level(uint32_t nvp_index)
+{
+ /* FIXME add crowd encoding */
+ return ctz32(~nvp_index) + 1;
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -1745,6 +1762,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 };
+ uint8_t group_level;
int count;
=20
/*
@@ -1758,9 +1776,9 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
=20
/* handle CPU exception delivery */
if (count) {
- trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring);
- xive_tctx_ipb_update(match.tctx, match.ring,
- xive_priority_to_ipb(priority));
+ group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
+ trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
+ xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
}
=20
return !!count;
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 4adc3b6950..db372f4b30 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -564,8 +564,10 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, =
XiveTCTX *tctx,
uint8_t nvp_blk, uint32_t nvp_idx,
bool do_restore)
{
+ uint8_t ipb, backlog_level;
+ uint8_t backlog_prio;
+ uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
Xive2Nvp nvp;
- uint8_t ipb;
=20
/*
* Grab the associated thread interrupt context registers in the
@@ -594,15 +596,15 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,=
XiveTCTX *tctx,
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
}
+ regs[TM_IPB] =3D ipb;
+ backlog_prio =3D xive_ipb_to_pipr(ipb);
+ backlog_level =3D 0;
+
/*
- * Always call xive_tctx_ipb_update(). Even if there were no
- * escalation triggered, there could be a pending interrupt which
- * was saved when the context was pulled and that we need to take
- * into account by recalculating the PIPR (which is not
- * saved/restored).
- * It will also raise the External interrupt signal if needed.
+ * Compute the PIPR based on the restored state.
+ * It will raise the External interrupt signal if needed.
*/
- xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level);
}
=20
/*
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 3dcf147198..7435728c51 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -282,7 +282,7 @@ xive_router_end_notify(uint8_t end_blk, uint32_t end_id=
x, uint32_t end_data) "EN
xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_bl=
k, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END =
0x%02x/0x%04x data 0x%08x"
xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uin=
t64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64
xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint=
64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64
-xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "fo=
und NVT 0x%x/0x%x ring=3D0x%x"
+xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uin=
t8_t group_level) "found NVT 0x%x/0x%x ring=3D0x%x group_level=3D%d"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "EN=
D 0x%x/0x%x @0x%"PRIx64
=20
# pnv_xive.c
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 02/14] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr()
Date: Mon, 9 Dec 2024 18:05:06 -0600
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Content-Type: text/plain; charset="utf-8"
Renamed function to follow the convention of the other function names.
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive.h | 16 ++++++++++++----
hw/intc/xive.c | 22 ++++++----------------
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ebee982528..41a4263a9d 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -130,11 +130,9 @@
* TCTX Thread interrupt Context
*
*
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * Copyright (c) 2017-2024, IBM Corporation.
*
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#ifndef PPC_XIVE_H
@@ -510,6 +508,16 @@ static inline uint8_t xive_priority_to_ipb(uint8_t pri=
ority)
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
=20
+/*
+ * Convert an Interrupt Pending Buffer (IPB) register to a Pending
+ * Interrupt Priority Register (PIPR), which contains the priority of
+ * the most favored pending notification.
+ */
+static inline uint8_t xive_ipb_to_pipr(uint8_t ibp)
+{
+ return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
+}
+
/*
* XIVE Thread Interrupt Management Aera (TIMA)
*
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 245e4d181a..7b06a48139 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -3,8 +3,7 @@
*
* Copyright (c) 2017-2018, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#include "qemu/osdep.h"
@@ -27,15 +26,6 @@
* XIVE Thread Interrupt Management context
*/
=20
-/*
- * Convert an Interrupt Pending Buffer (IPB) register to a Pending
- * Interrupt Priority Register (PIPR), which contains the priority of
- * the most favored pending notification.
- */
-static uint8_t ipb_to_pipr(uint8_t ibp)
-{
- return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
-}
=20
static uint8_t exception_mask(uint8_t ring)
{
@@ -159,7 +149,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t =
ring, uint8_t cppr)
* Recompute the PIPR based on local pending interrupts. The PHYS
* ring must take the minimum of both the PHYS and POOL PIPR values.
*/
- pipr_min =3D ipb_to_pipr(regs[TM_IPB]);
+ pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]);
ring_min =3D ring;
=20
/* PHYS updates also depend on POOL values */
@@ -169,7 +159,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t =
ring, uint8_t cppr)
/* POOL values only matter if POOL ctx is valid */
if (pool_regs[TM_WORD2] & 0x80) {
=20
- uint8_t pool_pipr =3D ipb_to_pipr(pool_regs[TM_IPB]);
+ uint8_t pool_pipr =3D xive_ipb_to_pipr(pool_regs[TM_IPB]);
=20
/*
* Determine highest priority interrupt and
@@ -193,7 +183,7 @@ void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring,=
uint8_t ipb)
uint8_t *regs =3D &tctx->regs[ring];
=20
regs[TM_IPB] |=3D ipb;
- regs[TM_PIPR] =3D ipb_to_pipr(regs[TM_IPB]);
+ regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]);
xive_tctx_notify(tctx, ring);
}
=20
@@ -841,9 +831,9 @@ void xive_tctx_reset(XiveTCTX *tctx)
* CPPR is first set.
*/
tctx->regs[TM_QW1_OS + TM_PIPR] =3D
- ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
+ xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =3D
- ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
+ xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
}
=20
static void xive_tctx_realize(DeviceState *dev, Error **errp)
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 03/14] ppc/xive2: Support group-matching when looking for
target
Date: Mon, 9 Dec 2024 18:05:08 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
If an END has the 'i' bit set (ignore), then it targets a group of
VPs. The size of the group depends on the VP index of the target
(first 0 found when looking at the least significant bits of the
index) so a mask is applied on the VP index of a running thread to
know if we have a match.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive.h | 5 +++-
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c | 33 ++++++++++++++-------
hw/intc/xive.c | 56 +++++++++++++++++++++++++-----------
hw/intc/xive2.c | 65 ++++++++++++++++++++++++++++++------------
5 files changed, 114 insertions(+), 46 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 971da029eb..21ce5a9df3 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -424,6 +424,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *=
eas);
typedef struct XiveTCTXMatch {
XiveTCTX *tctx;
uint8_t ring;
+ bool precluded;
} XiveTCTXMatch;
=20
#define TYPE_XIVE_PRESENTER "xive-presenter"
@@ -452,7 +453,9 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
- uint32_t logic_serv);
+ uint32_t logic_serv, bool *precluded);
+
+uint32_t xive_get_vpgroup_size(uint32_t nvp_index);
=20
/*
* XIVE Fabric (Interface between Interrupt Controller and Machine)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 5bccf41159..17c31fcb4b 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -121,6 +121,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xive=
TCTX *tctx,
hwaddr offset, unsigned size);
void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
+bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority);
void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 834d32287b..3fb466bb2c 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -660,21 +660,34 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, u=
int8_t format,
logic_serv);
}
=20
- /*
- * Save the context and follow on to catch duplicates,
- * that we don't support yet.
- */
if (ring !=3D -1) {
- if (match->tctx) {
+ /*
+ * For VP-specific match, finding more than one is a
+ * problem. For group notification, it's possible.
+ */
+ if (!cam_ignore && match->tctx) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
"thread context NVT %x/%x\n",
nvt_blk, nvt_idx);
- return false;
+ /* Should set a FIR if we ever model it */
+ return -1;
+ }
+ /*
+ * For a group notification, we need to know if the
+ * match is precluded first by checking the current
+ * thread priority. If the interrupt can be delivered,
+ * we always notify the first match (for now).
+ */
+ if (cam_ignore &&
+ xive2_tm_irq_precluded(tctx, ring, priority)) {
+ match->precluded =3D true;
+ } else {
+ if (!match->tctx) {
+ match->ring =3D ring;
+ match->tctx =3D tctx;
+ }
+ count++;
}
-
- match->ring =3D ring;
- match->tctx =3D tctx;
- count++;
}
}
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 6e73f7b063..9345cddead 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1671,6 +1671,16 @@ static uint32_t xive_tctx_hw_cam_line(XivePresenter =
*xptr, XiveTCTX *tctx)
return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
=20
+uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
+{
+ /*
+ * Group size is a power of 2. The position of the first 0
+ * (starting with the least significant bits) in the NVP index
+ * gives the size of the group.
+ */
+ return 1 << (ctz32(~nvp_index) + 1);
+}
+
static uint8_t xive_get_group_level(uint32_t nvp_index)
{
/* FIXME add crowd encoding */
@@ -1743,30 +1753,39 @@ int xive_presenter_tctx_match(XivePresenter *xptr, =
XiveTCTX *tctx,
/*
* This is our simple Xive Presenter Engine model. It is merged in the
* Router as it does not require an extra object.
- *
- * It receives notification requests sent by the IVRE to find one
- * matching NVT (or more) dispatched on the processor threads. In case
- * of a single NVT notification, the process is abbreviated and the
- * thread is signaled if a match is found. In case of a logical server
- * notification (bits ignored at the end of the NVT identifier), the
- * IVPE and IVRE select a winning thread using different filters. This
- * involves 2 or 3 exchanges on the PowerBus that the model does not
- * support.
- *
- * The parameters represent what is sent on the PowerBus
*/
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
- uint32_t logic_serv)
+ uint32_t logic_serv, bool *precluded)
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
- XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 };
+ XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0, .precluded =3D =
false };
uint8_t group_level;
int count;
=20
/*
- * Ask the machine to scan the interrupt controllers for a match
+ * Ask the machine to scan the interrupt controllers for a match.
+ *
+ * For VP-specific notification, we expect at most one match and
+ * one call to the presenters is all we need (abbreviated notify
+ * sequence documented by the architecture).
+ *
+ * For VP-group notification, match_nvt() is the equivalent of the
+ * "histogram" and "poll" commands sent to the power bus to the
+ * presenters. 'count' could be more than one, but we always
+ * select the first match for now. 'precluded' tells if (at least)
+ * one thread matches but can't take the interrupt now because
+ * it's running at a more favored priority. We return the
+ * information to the router so that it can take appropriate
+ * actions (backlog, escalation, broadcast, etc...)
+ *
+ * If we were to implement a better way of dispatching the
+ * interrupt in case of multiple matches (instead of the first
+ * match), we would need a heuristic to elect a thread (for
+ * example, the hardware keeps track of an 'age' in the TIMA) and
+ * a new command to the presenters (the equivalent of the "assign"
+ * power bus command in the documented full notify sequence.
*/
count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
priority, logic_serv, &match);
@@ -1779,6 +1798,8 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
+ } else {
+ *precluded =3D match.precluded;
}
=20
return !!count;
@@ -1818,7 +1839,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
uint8_t nvt_blk;
uint32_t nvt_idx;
XiveNVT nvt;
- bool found;
+ bool found, precluded;
=20
uint8_t end_blk =3D xive_get_field64(EAS_END_BLOCK, eas->w);
uint32_t end_idx =3D xive_get_field64(EAS_END_INDEX, eas->w);
@@ -1901,8 +1922,9 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
found =3D xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
- xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
));
-
+ xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
),
+ &precluded);
+ /* we don't support VP-group notification on P9, so precluded is not u=
sed */
/* TODO: Auto EOI. */
=20
if (found) {
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index db372f4b30..2cb03c758e 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -739,6 +739,12 @@ int xive2_router_write_nvgc(Xive2Router *xrtr, bool cr=
owd,
return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
}
=20
+static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2,
+ uint32_t vp_mask)
+{
+ return (cam1 & vp_mask) =3D=3D (cam2 & vp_mask);
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -753,44 +759,50 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw0w2 =3D xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
=20
- /*
- * TODO (PowerNV): ignore mode. The low order bits of the NVT
- * identifier are ignored in the "CAM" match.
- */
+ uint32_t vp_mask =3D 0xFFFFFFFF;
=20
if (format =3D=3D 0) {
- if (cam_ignore =3D=3D true) {
- /*
- * F=3D0 & i=3D1: Logical server notification (bits ignored at
- * the end of the NVT identifier)
- */
- qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
- nvt_blk, nvt_idx);
- return -1;
+ /*
+ * i=3D0: Specific NVT notification
+ * i=3D1: VP-group notification (bits ignored at the end of the
+ * NVT identifier)
+ */
+ if (cam_ignore) {
+ vp_mask =3D ~(xive_get_vpgroup_size(nvt_idx) - 1);
}
=20
- /* F=3D0 & i=3D0: Specific NVT notification */
+ /* For VP-group notifications, threads with LGS=3D0 are excluded */
=20
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
- cam =3D=3D xive2_tctx_hw_cam_line(xptr, tctx)) {
+ !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] =3D=3D 0) =
&&
+ xive2_vp_match_mask(cam,
+ xive2_tctx_hw_cam_line(xptr, tctx),
+ vp_mask)) {
return TM_QW3_HV_PHYS;
}
=20
/* HV POOL ring */
if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
- cam =3D=3D xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
+ !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] =3D=3D 0) =
&&
+ xive2_vp_match_mask(cam,
+ xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2=
),
+ vp_mask)) {
return TM_QW2_HV_POOL;
}
=20
/* OS ring */
if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
- cam =3D=3D xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
+ !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] =3D=3D 0) &&
+ xive2_vp_match_mask(cam,
+ xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2),
+ vp_mask)) {
return TM_QW1_OS;
}
} else {
/* F=3D1 : User level Event-Based Branch (EBB) notification */
=20
+ /* FIXME: what if cam_ignore and LGS =3D 0 ? */
/* USER ring */
if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
(cam =3D=3D xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
@@ -802,6 +814,22 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
return -1;
}
=20
+bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+
+ /*
+ * The xive2_presenter_tctx_match() above tells if there's a match
+ * but for VP-group notification, we still need to look at the
+ * priority to know if the thread can take the interrupt now or if
+ * it is precluded.
+ */
+ if (priority < regs[TM_CPPR]) {
+ return false;
+ }
+ return true;
+}
+
static void xive2_router_realize(DeviceState *dev, Error **errp)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(dev);
@@ -841,7 +869,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr, =
uint8_t end_blk,
Xive2End end;
uint8_t priority;
uint8_t format;
- bool found;
+ bool found, precluded;
Xive2Nvp nvp;
uint8_t nvp_blk;
uint32_t nvp_idx;
@@ -922,7 +950,8 @@ static void xive2_router_end_notify(Xive2Router *xrtr, =
uint8_t end_blk,
found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
xive2_end_is_ignore(&end),
priority,
- xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7));
+ xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7),
+ &precluded);
=20
/* TODO: Auto EOI. */
=20
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 03/14] ppc/xive2: Add grouping level to notification
Date: Mon, 9 Dec 2024 18:05:07 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
The NSR has a (so far unused) grouping level field. When a interrupt
is presented, that field tells the hypervisor or OS if the interrupt
is for an individual VP or for a VP-group/crowd. This patch reworks
the presentation API to allow to set/unset the level when
raising/accepting an interrupt.
It also renames xive_tctx_ipb_update() to xive_tctx_pipr_update() as
the IPB is only used for VP-specific target, whereas the PIPR always
needs to be updated.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive.h | 9 +++-
include/hw/ppc/xive_regs.h | 25 ++++++++---
hw/intc/xive.c | 88 ++++++++++++++++++++++----------------
hw/intc/xive2.c | 19 ++++----
hw/intc/trace-events | 2 +-
5 files changed, 90 insertions(+), 53 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 41a4263a9d..4d1ce376f1 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -508,6 +508,11 @@ static inline uint8_t xive_priority_to_ipb(uint8_t pri=
ority)
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
=20
+static inline uint8_t xive_priority_to_pipr(uint8_t priority)
+{
+ return priority > XIVE_PRIORITY_MAX ? 0xFF : priority;
+}
+
/*
* Convert an Interrupt Pending Buffer (IPB) register to a Pending
* Interrupt Priority Register (PIPR), which contains the priority of
@@ -540,8 +545,10 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString =
*buf);
Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
-void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
+void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
+ uint8_t group_level);
void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring);
+void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level);
=20
/*
* KVM XIVE device helpers
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 326327fc79..54bc6c53b4 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -7,10 +7,9 @@
* access to the different fields.
*
*
- * Copyright (c) 2016-2018, IBM Corporation.
+ * Copyright (c) 2016-2024, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#ifndef PPC_XIVE_REGS_H
@@ -146,7 +145,14 @@
#define TM_SPC_PULL_PHYS_CTX_OL 0xc38 /* Pull phys ctx to odd cache line=
*/
/* XXX more... */
=20
-/* NSR fields for the various QW ack types */
+/*
+ * NSR fields for the various QW ack types
+ *
+ * P10 has an extra bit in QW3 for the group level instead of the
+ * reserved 'i' bit. Since it is not used and we don't support group
+ * interrupts on P9, we use the P10 definition for the group level so
+ * that we can have common macros for the NSR
+ */
#define TM_QW0_NSR_EB PPC_BIT8(0)
#define TM_QW1_NSR_EO PPC_BIT8(0)
#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1)
@@ -154,8 +160,15 @@
#define TM_QW3_NSR_HE_POOL 1
#define TM_QW3_NSR_HE_PHYS 2
#define TM_QW3_NSR_HE_LSI 3
-#define TM_QW3_NSR_I PPC_BIT8(2)
-#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7)
+#define TM_NSR_GRP_LVL PPC_BITMASK8(2, 7)
+/*
+ * On P10, the format of the 6-bit group level is: 2 bits for the
+ * crowd size and 4 bits for the group size. Since group/crowd size is
+ * always a power of 2, we encode the log. For example, group_level=3D4
+ * means crowd size =3D 0 and group size =3D 16 (2^4)
+ * Same encoding is used in the NVP and NVGC structures for
+ * PGoFirst and PGoNext fields
+ */
=20
/*
* EAS (Event Assignment Structure)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7b06a48139..d2690a7d10 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -26,19 +26,6 @@
* XIVE Thread Interrupt Management context
*/
=20
-
-static uint8_t exception_mask(uint8_t ring)
-{
- switch (ring) {
- case TM_QW1_OS:
- return TM_QW1_NSR_EO;
- case TM_QW3_HV_PHYS:
- return TM_QW3_NSR_HE;
- default:
- g_assert_not_reached();
- }
-}
-
static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring)
{
switch (ring) {
@@ -58,11 +45,10 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_=
t ring)
{
uint8_t *regs =3D &tctx->regs[ring];
uint8_t nsr =3D regs[TM_NSR];
- uint8_t mask =3D exception_mask(ring);
=20
qemu_irq_lower(xive_tctx_output(tctx, ring));
=20
- if (regs[TM_NSR] & mask) {
+ if (regs[TM_NSR] !=3D 0) {
uint8_t cppr =3D regs[TM_PIPR];
uint8_t alt_ring;
uint8_t *alt_regs;
@@ -77,11 +63,18 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_=
t ring)
=20
regs[TM_CPPR] =3D cppr;
=20
- /* Reset the pending buffer bit */
- alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr);
+ /*
+ * If the interrupt was for a specific VP, reset the pending
+ * buffer bit, otherwise clear the logical server indicator
+ */
+ if (regs[TM_NSR] & TM_NSR_GRP_LVL) {
+ regs[TM_NSR] &=3D ~TM_NSR_GRP_LVL;
+ } else {
+ alt_regs[TM_IPB] &=3D ~xive_priority_to_ipb(cppr);
+ }
=20
- /* Drop Exception bit */
- regs[TM_NSR] &=3D ~mask;
+ /* Drop the exception bit and any group/crowd */
+ regs[TM_NSR] =3D 0;
=20
trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring,
alt_regs[TM_IPB], regs[TM_PIPR],
@@ -91,7 +84,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t =
ring)
return ((uint64_t)nsr << 8) | regs[TM_CPPR];
}
=20
-static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
+void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring, uint8_t group_level)
{
/* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
@@ -101,13 +94,13 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t r=
ing)
if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) {
switch (ring) {
case TM_QW1_OS:
- regs[TM_NSR] |=3D TM_QW1_NSR_EO;
+ regs[TM_NSR] =3D TM_QW1_NSR_EO | (group_level & 0x3F);
break;
case TM_QW2_HV_POOL:
- alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6);
+ alt_regs[TM_NSR] =3D (TM_QW3_NSR_HE_POOL << 6) | (group_level =
& 0x3F);
break;
case TM_QW3_HV_PHYS:
- regs[TM_NSR] |=3D (TM_QW3_NSR_HE_PHYS << 6);
+ regs[TM_NSR] =3D (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x=
3F);
break;
default:
g_assert_not_reached();
@@ -175,17 +168,27 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_=
t ring, uint8_t cppr)
regs[TM_PIPR] =3D pipr_min;
=20
/* CPPR has changed, check if we need to raise a pending exception */
- xive_tctx_notify(tctx, ring_min);
+ xive_tctx_notify(tctx, ring_min, 0);
}
=20
-void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
-{
+void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t ring, uint8_t priority,
+ uint8_t group_level)
+ {
+ /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
+ uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
+ uint8_t *alt_regs =3D &tctx->regs[alt_ring];
uint8_t *regs =3D &tctx->regs[ring];
=20
- regs[TM_IPB] |=3D ipb;
- regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]);
- xive_tctx_notify(tctx, ring);
-}
+ if (group_level =3D=3D 0) {
+ /* VP-specific */
+ regs[TM_IPB] |=3D xive_priority_to_ipb(priority);
+ alt_regs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]);
+ } else {
+ /* VP-group */
+ alt_regs[TM_PIPR] =3D xive_priority_to_pipr(priority);
+ }
+ xive_tctx_notify(tctx, ring, group_level);
+ }
=20
/*
* XIVE Thread Interrupt Management Area (TIMA)
@@ -401,13 +404,13 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, X=
iveTCTX *tctx,
}
=20
/*
- * Adjust the IPB to allow a CPU to process event queues of other
+ * Adjust the PIPR to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned=
size)
{
- xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xf=
f));
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0);
}
=20
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@@ -485,16 +488,20 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, X=
iveTCTX *tctx,
/* Reset the NVT value */
nvt.w4 =3D xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
+ regs[TM_IPB] |=3D ipb;
}
+
/*
- * Always call xive_tctx_ipb_update(). Even if there were no
+ * Always call xive_tctx_pipr_update(). Even if there were no
* escalation triggered, there could be a pending interrupt which
* was saved when the context was pulled and that we need to take
* into account by recalculating the PIPR (which is not
* saved/restored).
* It will also raise the External interrupt signal if needed.
*/
- xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */
}
=20
/*
@@ -1650,6 +1657,12 @@ static uint32_t xive_tctx_hw_cam_line(XivePresenter =
*xptr, XiveTCTX *tctx)
return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
=20
+static uint8_t xive_get_group_level(uint32_t nvp_index)
+{
+ /* FIXME add crowd encoding */
+ return ctz32(~nvp_index) + 1;
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -1735,6 +1748,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 };
+ uint8_t group_level;
int count;
=20
/*
@@ -1748,9 +1762,9 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
=20
/* handle CPU exception delivery */
if (count) {
- trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring);
- xive_tctx_ipb_update(match.tctx, match.ring,
- xive_priority_to_ipb(priority));
+ group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
+ trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
+ xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
}
=20
return !!count;
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 24e504fce1..54e4f784fc 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -563,8 +563,11 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, =
XiveTCTX *tctx,
uint8_t nvp_blk, uint32_t nvp_idx,
bool do_restore)
{
- Xive2Nvp nvp;
uint8_t ipb;
+ uint8_t backlog_level;
+ uint8_t backlog_prio;
+ uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
+ Xive2Nvp nvp;
=20
/*
* Grab the associated thread interrupt context registers in the
@@ -593,15 +596,15 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,=
XiveTCTX *tctx,
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
}
+ regs[TM_IPB] =3D ipb;
+ backlog_prio =3D xive_ipb_to_pipr(ipb);
+ backlog_level =3D 0;
+
/*
- * Always call xive_tctx_ipb_update(). Even if there were no
- * escalation triggered, there could be a pending interrupt which
- * was saved when the context was pulled and that we need to take
- * into account by recalculating the PIPR (which is not
- * saved/restored).
- * It will also raise the External interrupt signal if needed.
+ * Compute the PIPR based on the restored state.
+ * It will raise the External interrupt signal if needed.
*/
- xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level);
}
=20
/*
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 3dcf147198..7435728c51 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -282,7 +282,7 @@ xive_router_end_notify(uint8_t end_blk, uint32_t end_id=
x, uint32_t end_data) "EN
xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_bl=
k, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END =
0x%02x/0x%04x data 0x%08x"
xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uin=
t64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64
xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint=
64_t value) "target=3D%d @0x%"PRIx64" sz=3D%d val=3D0x%" PRIx64
-xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "fo=
und NVT 0x%x/0x%x ring=3D0x%x"
+xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uin=
t8_t group_level) "found NVT 0x%x/0x%x ring=3D0x%x group_level=3D%d"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "EN=
D 0x%x/0x%x @0x%"PRIx64
=20
# pnv_xive.c
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 04/14] ppc/xive2: Support group-matching when looking for
target
Date: Mon, 9 Dec 2024 18:05:10 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
If an END has the 'i' bit set (ignore), then it targets a group of
VPs. The size of the group depends on the VP index of the target
(first 0 found when looking at the least significant bits of the
index) so a mask is applied on the VP index of a running thread to
know if we have a match.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive.h | 5 +++-
include/hw/ppc/xive2.h | 7 ++---
hw/intc/pnv_xive2.c | 38 +++++++++++++++---------
hw/intc/xive.c | 56 +++++++++++++++++++++++++-----------
hw/intc/xive2.c | 65 ++++++++++++++++++++++++++++++------------
5 files changed, 118 insertions(+), 53 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 4d1ce376f1..ce4eb9726b 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -422,6 +422,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *=
eas);
typedef struct XiveTCTXMatch {
XiveTCTX *tctx;
uint8_t ring;
+ bool precluded;
} XiveTCTXMatch;
=20
#define TYPE_XIVE_PRESENTER "xive-presenter"
@@ -450,7 +451,9 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
- uint32_t logic_serv);
+ uint32_t logic_serv, bool *precluded);
+
+uint32_t xive_get_vpgroup_size(uint32_t nvp_index);
=20
/*
* XIVE Fabric (Interface between Interrupt Controller and Machine)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 5bccf41159..65154f78d8 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -1,11 +1,9 @@
/*
* QEMU PowerPC XIVE2 interrupt controller model (POWER10)
*
- * Copyright (c) 2019-2022, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * Copyright (c) 2019-2024, IBM Corporation.
*
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#ifndef PPC_XIVE2_H
@@ -121,6 +119,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xive=
TCTX *tctx,
hwaddr offset, unsigned size);
void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
+bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority);
void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 834d32287b..5cdd4fdcc9 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1,10 +1,9 @@
/*
* QEMU PowerPC XIVE2 interrupt controller model (POWER10)
*
- * Copyright (c) 2019-2022, IBM Corporation.
+ * Copyright (c) 2019-2024, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#include "qemu/osdep.h"
@@ -660,21 +659,34 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, u=
int8_t format,
logic_serv);
}
=20
- /*
- * Save the context and follow on to catch duplicates,
- * that we don't support yet.
- */
if (ring !=3D -1) {
- if (match->tctx) {
+ /*
+ * For VP-specific match, finding more than one is a
+ * problem. For group notification, it's possible.
+ */
+ if (!cam_ignore && match->tctx) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
"thread context NVT %x/%x\n",
nvt_blk, nvt_idx);
- return false;
+ /* Should set a FIR if we ever model it */
+ return -1;
+ }
+ /*
+ * For a group notification, we need to know if the
+ * match is precluded first by checking the current
+ * thread priority. If the interrupt can be delivered,
+ * we always notify the first match (for now).
+ */
+ if (cam_ignore &&
+ xive2_tm_irq_precluded(tctx, ring, priority)) {
+ match->precluded =3D true;
+ } else {
+ if (!match->tctx) {
+ match->ring =3D ring;
+ match->tctx =3D tctx;
+ }
+ count++;
}
-
- match->ring =3D ring;
- match->tctx =3D tctx;
- count++;
}
}
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index d2690a7d10..412bb94b91 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1657,6 +1657,16 @@ static uint32_t xive_tctx_hw_cam_line(XivePresenter =
*xptr, XiveTCTX *tctx)
return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
=20
+uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
+{
+ /*
+ * Group size is a power of 2. The position of the first 0
+ * (starting with the least significant bits) in the NVP index
+ * gives the size of the group.
+ */
+ return 1 << (ctz32(~nvp_index) + 1);
+}
+
static uint8_t xive_get_group_level(uint32_t nvp_index)
{
/* FIXME add crowd encoding */
@@ -1729,30 +1739,39 @@ int xive_presenter_tctx_match(XivePresenter *xptr, =
XiveTCTX *tctx,
/*
* This is our simple Xive Presenter Engine model. It is merged in the
* Router as it does not require an extra object.
- *
- * It receives notification requests sent by the IVRE to find one
- * matching NVT (or more) dispatched on the processor threads. In case
- * of a single NVT notification, the process is abbreviated and the
- * thread is signaled if a match is found. In case of a logical server
- * notification (bits ignored at the end of the NVT identifier), the
- * IVPE and IVRE select a winning thread using different filters. This
- * involves 2 or 3 exchanges on the PowerBus that the model does not
- * support.
- *
- * The parameters represent what is sent on the PowerBus
*/
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
- uint32_t logic_serv)
+ uint32_t logic_serv, bool *precluded)
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
- XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0 };
+ XiveTCTXMatch match =3D { .tctx =3D NULL, .ring =3D 0, .precluded =3D =
false };
uint8_t group_level;
int count;
=20
/*
- * Ask the machine to scan the interrupt controllers for a match
+ * Ask the machine to scan the interrupt controllers for a match.
+ *
+ * For VP-specific notification, we expect at most one match and
+ * one call to the presenters is all we need (abbreviated notify
+ * sequence documented by the architecture).
+ *
+ * For VP-group notification, match_nvt() is the equivalent of the
+ * "histogram" and "poll" commands sent to the power bus to the
+ * presenters. 'count' could be more than one, but we always
+ * select the first match for now. 'precluded' tells if (at least)
+ * one thread matches but can't take the interrupt now because
+ * it's running at a more favored priority. We return the
+ * information to the router so that it can take appropriate
+ * actions (backlog, escalation, broadcast, etc...)
+ *
+ * If we were to implement a better way of dispatching the
+ * interrupt in case of multiple matches (instead of the first
+ * match), we would need a heuristic to elect a thread (for
+ * example, the hardware keeps track of an 'age' in the TIMA) and
+ * a new command to the presenters (the equivalent of the "assign"
+ * power bus command in the documented full notify sequence.
*/
count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
priority, logic_serv, &match);
@@ -1765,6 +1784,8 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
+ } else {
+ *precluded =3D match.precluded;
}
=20
return !!count;
@@ -1804,7 +1825,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
uint8_t nvt_blk;
uint32_t nvt_idx;
XiveNVT nvt;
- bool found;
+ bool found, precluded;
=20
uint8_t end_blk =3D xive_get_field64(EAS_END_BLOCK, eas->w);
uint32_t end_idx =3D xive_get_field64(EAS_END_INDEX, eas->w);
@@ -1887,8 +1908,9 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
found =3D xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
- xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
));
-
+ xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
),
+ &precluded);
+ /* we don't support VP-group notification on P9, so precluded is not u=
sed */
/* TODO: Auto EOI. */
=20
if (found) {
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 54e4f784fc..cffcf3ff05 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -739,6 +739,12 @@ int xive2_router_write_nvgc(Xive2Router *xrtr, bool cr=
owd,
return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
}
=20
+static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2,
+ uint32_t vp_mask)
+{
+ return (cam1 & vp_mask) =3D=3D (cam2 & vp_mask);
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -753,44 +759,50 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw0w2 =3D xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
=20
- /*
- * TODO (PowerNV): ignore mode. The low order bits of the NVT
- * identifier are ignored in the "CAM" match.
- */
+ uint32_t vp_mask =3D 0xFFFFFFFF;
=20
if (format =3D=3D 0) {
- if (cam_ignore =3D=3D true) {
- /*
- * F=3D0 & i=3D1: Logical server notification (bits ignored at
- * the end of the NVT identifier)
- */
- qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
- nvt_blk, nvt_idx);
- return -1;
+ /*
+ * i=3D0: Specific NVT notification
+ * i=3D1: VP-group notification (bits ignored at the end of the
+ * NVT identifier)
+ */
+ if (cam_ignore) {
+ vp_mask =3D ~(xive_get_vpgroup_size(nvt_idx) - 1);
}
=20
- /* F=3D0 & i=3D0: Specific NVT notification */
+ /* For VP-group notifications, threads with LGS=3D0 are excluded */
=20
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
- cam =3D=3D xive2_tctx_hw_cam_line(xptr, tctx)) {
+ !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] =3D=3D 0) =
&&
+ xive2_vp_match_mask(cam,
+ xive2_tctx_hw_cam_line(xptr, tctx),
+ vp_mask)) {
return TM_QW3_HV_PHYS;
}
=20
/* HV POOL ring */
if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
- cam =3D=3D xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
+ !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] =3D=3D 0) =
&&
+ xive2_vp_match_mask(cam,
+ xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2=
),
+ vp_mask)) {
return TM_QW2_HV_POOL;
}
=20
/* OS ring */
if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
- cam =3D=3D xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
+ !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] =3D=3D 0) &&
+ xive2_vp_match_mask(cam,
+ xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2),
+ vp_mask)) {
return TM_QW1_OS;
}
} else {
/* F=3D1 : User level Event-Based Branch (EBB) notification */
=20
+ /* FIXME: what if cam_ignore and LGS =3D 0 ? */
/* USER ring */
if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
(cam =3D=3D xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
@@ -802,6 +814,22 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
return -1;
}
=20
+bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+
+ /*
+ * The xive2_presenter_tctx_match() above tells if there's a match
+ * but for VP-group notification, we still need to look at the
+ * priority to know if the thread can take the interrupt now or if
+ * it is precluded.
+ */
+ if (priority < regs[TM_CPPR]) {
+ return false;
+ }
+ return true;
+}
+
static void xive2_router_realize(DeviceState *dev, Error **errp)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(dev);
@@ -841,7 +869,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr, =
uint8_t end_blk,
Xive2End end;
uint8_t priority;
uint8_t format;
- bool found;
+ bool found, precluded;
Xive2Nvp nvp;
uint8_t nvp_blk;
uint32_t nvp_idx;
@@ -922,7 +950,8 @@ static void xive2_router_end_notify(Xive2Router *xrtr, =
uint8_t end_blk,
found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
xive2_end_is_ignore(&end),
priority,
- xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7));
+ xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7),
+ &precluded);
=20
/* TODO: Auto EOI. */
=20
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 04/14] ppc/xive2: Add undelivered group interrupt to
backlog
Date: Mon, 9 Dec 2024 18:05:09 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When a group interrupt cannot be delivered, we need to:
- increment the backlog counter for the group in the NVG table
(if the END is configured to keep a backlog).
- start a broadcast operation to set the LSMFB field on matching CPUs
which can't take the interrupt now because they're running at too
high a priority.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive.h | 5 ++
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c | 42 +++++++++++++++++
hw/intc/xive2.c | 105 +++++++++++++++++++++++++++++++++++------
hw/ppc/pnv.c | 18 +++++++
5 files changed, 156 insertions(+), 15 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 21ce5a9df3..c15cd4358d 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -444,6 +444,9 @@ struct XivePresenterClass {
uint32_t logic_serv, XiveTCTXMatch *match);
bool (*in_kernel)(const XivePresenter *xptr);
uint32_t (*get_config)(XivePresenter *xptr);
+ int (*broadcast)(XivePresenter *xptr,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority);
};
=20
int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
@@ -474,6 +477,8 @@ struct XiveFabricClass {
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
+ int (*broadcast)(XiveFabric *xfb, uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority);
};
=20
/*
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 17c31fcb4b..d88db05687 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -122,6 +122,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xive=
TCTX *tctx,
void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority);
+void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority);
void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 3fb466bb2c..0482193fd7 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -706,6 +706,47 @@ static uint32_t pnv_xive2_presenter_get_config(XivePre=
senter *xptr)
return cfg;
}
=20
+static int pnv_xive2_broadcast(XivePresenter *xptr,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority)
+{
+ PnvXive2 *xive =3D PNV_XIVE2(xptr);
+ PnvChip *chip =3D xive->chip;
+ int i, j;
+ bool gen1_tima_os =3D
+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
+
+ for (i =3D 0; i < chip->nr_cores; i++) {
+ PnvCore *pc =3D chip->cores[i];
+ CPUCore *cc =3D CPU_CORE(pc);
+
+ for (j =3D 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu =3D pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
+
+ tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ if (gen1_tima_os) {
+ ring =3D xive_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
+ nvt_idx, true, 0);
+ } else {
+ ring =3D xive2_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
+ nvt_idx, true, 0);
+ }
+
+ if (ring !=3D -1) {
+ xive2_tm_set_lsmfb(tctx, ring, priority);
+ }
+ }
+ }
+ return 0;
+}
+
static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr)
{
return pnv_xive2_block_id(PNV_XIVE2(xrtr));
@@ -2446,6 +2487,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, =
void *data)
=20
xpc->match_nvt =3D pnv_xive2_match_nvt;
xpc->get_config =3D pnv_xive2_presenter_get_config;
+ xpc->broadcast =3D pnv_xive2_broadcast;
};
=20
static const TypeInfo pnv_xive2_info =3D {
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 2cb03c758e..a6dc6d553f 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -63,6 +63,30 @@ static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, =
uint8_t priority)
return val;
}
=20
+static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
+ uint32_t val)
+{
+ uint8_t *ptr, i;
+ uint32_t shift;
+
+ if (priority > 7) {
+ return;
+ }
+
+ if (val > 0xFFFFFF) {
+ val =3D 0xFFFFFF;
+ }
+ /*
+ * The per-priority backlog counters are 24-bit and the structure
+ * is stored in big endian
+ */
+ ptr =3D (uint8_t *)&nvgc->w2 + priority * 3;
+ for (i =3D 0; i < 3; i++, ptr++) {
+ shift =3D 8 * (2 - i);
+ *ptr =3D (val >> shift) & 0xFF;
+ }
+}
+
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
{
if (!xive2_eas_is_valid(eas)) {
@@ -830,6 +854,19 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, =
uint8_t priority)
return true;
}
=20
+void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+
+ /*
+ * Called by the router during a VP-group notification when the
+ * thread matches but can't take the interrupt because it's
+ * already running at a more favored priority. It then stores the
+ * new interrupt priority in the LSMFB field.
+ */
+ regs[TM_LSMFB] =3D priority;
+}
+
static void xive2_router_realize(DeviceState *dev, Error **errp)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(dev);
@@ -962,10 +999,9 @@ static void xive2_router_end_notify(Xive2Router *xrtr,=
uint8_t end_blk,
/*
* If no matching NVP is dispatched on a HW thread :
* - specific VP: update the NVP structure if backlog is activated
- * - logical server : forward request to IVPE (not supported)
+ * - VP-group: update the backlog counter for that priority in the NVG
*/
if (xive2_end_is_backlog(&end)) {
- uint8_t ipb;
=20
if (format =3D=3D 1) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -974,19 +1010,58 @@ static void xive2_router_end_notify(Xive2Router *xrt=
r, uint8_t end_blk,
return;
}
=20
- /*
- * Record the IPB in the associated NVP structure for later
- * use. The presenter will resend the interrupt when the vCPU
- * is dispatched again on a HW thread.
- */
- ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) |
- xive_priority_to_ipb(priority);
- nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
- xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
-
- /*
- * On HW, follows a "Broadcast Backlog" to IVPEs
- */
+ if (!xive2_end_is_ignore(&end)) {
+ uint8_t ipb;
+ /*
+ * Record the IPB in the associated NVP structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) |
+ xive_priority_to_ipb(priority);
+ nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+ } else {
+ Xive2Nvgc nvg;
+ uint32_t backlog;
+
+ /* For groups, the per-priority backlog counters are in the NV=
G */
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg)=
) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVG %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvgc_is_valid(&nvg)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid=
\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ /*
+ * Increment the backlog counter for that priority.
+ * For the precluded case, we only call broadcast the
+ * first time the counter is incremented. broadcast will
+ * set the LSMFB field of the TIMA of relevant threads so
+ * that they know an interrupt is pending.
+ */
+ backlog =3D xive2_nvgc_get_backlog(&nvg, priority) + 1;
+ xive2_nvgc_set_backlog(&nvg, priority, backlog);
+ xive2_router_write_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg);
+
+ if (precluded && backlog =3D=3D 1) {
+ XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb);
+ xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx, priority);
+
+ if (!xive2_end_is_precluded_escalation(&end)) {
+ /*
+ * The interrupt will be picked up when the
+ * matching thread lowers its priority level
+ */
+ return;
+ }
+ }
+ }
}
=20
do_escalation:
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0f0d7567d..6c76f65936 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2639,6 +2639,23 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uin=
t8_t format,
return total_count;
}
=20
+static int pnv10_xive_broadcast(XiveFabric *xfb,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority)
+{
+ PnvMachineState *pnv =3D PNV_MACHINE(xfb);
+ int i;
+
+ for (i =3D 0; i < pnv->num_chips; i++) {
+ Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]);
+ XivePresenter *xptr =3D XIVE_PRESENTER(&chip10->xive);
+ XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
+
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, priority);
+ }
+ return 0;
+}
+
static bool pnv_machine_get_big_core(Object *obj, Error **errp)
{
PnvMachineState *pnv =3D PNV_MACHINE(obj);
@@ -2772,6 +2789,7 @@ static void pnv_machine_p10_common_class_init(ObjectC=
lass *oc, void *data)
pmc->dt_power_mgt =3D pnv_dt_power_mgt;
=20
xfc->match_nvt =3D pnv10_xive_match_nvt;
+ xfc->broadcast =3D pnv10_xive_broadcast;
=20
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 05/14] ppc/xive2: Process group backlog when pushing an OS
context
Date: Mon, 9 Dec 2024 18:05:12 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When pushing an OS context, we were already checking if there was a
pending interrupt in the IPB and sending a notification if needed. We
also need to check if there is a pending group interrupt stored in the
NVG table. To avoid useless backlog scans, we only scan if the NVP
belongs to a group.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
hw/intc/xive2.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 97 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index a6dc6d553f..7130892482 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -279,6 +279,85 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t =
data)
end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
}
+/*
+ * Scan the group chain and return the highest priority and group
+ * level of pending group interrupts.
+ */
+static uint8_t xive2_presenter_backlog_check(XivePresenter *xptr,
+ uint8_t nvp_blk, uint32_t nvp=
_idx,
+ uint8_t first_group,
+ uint8_t *out_level)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint32_t nvgc_idx, mask;
+ uint32_t current_level, count;
+ uint8_t prio;
+ Xive2Nvgc nvgc;
+
+ for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) {
+ current_level =3D first_group & 0xF;
+
+ while (current_level) {
+ mask =3D (1 << current_level) - 1;
+ nvgc_idx =3D nvp_idx & ~mask;
+ nvgc_idx |=3D mask >> 1;
+ qemu_log("fxb %s checking backlog for prio %d group idx %x\n",
+ __func__, prio, nvgc_idx);
+
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvg=
c)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return 0xFF;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return 0xFF;
+ }
+
+ count =3D xive2_nvgc_get_backlog(&nvgc, prio);
+ if (count) {
+ *out_level =3D current_level;
+ return prio;
+ }
+ current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0xF;
+ }
+ }
+ return 0xFF;
+}
+
+static void xive2_presenter_backlog_decr(XivePresenter *xptr,
+ uint8_t nvp_blk, uint32_t nvp_idx,
+ uint8_t group_prio,
+ uint8_t group_level)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint32_t nvgc_idx, mask, count;
+ Xive2Nvgc nvgc;
+
+ group_level &=3D 0xF;
+ mask =3D (1 << group_level) - 1;
+ nvgc_idx =3D nvp_idx & ~mask;
+ nvgc_idx |=3D mask >> 1;
+
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return;
+ }
+ count =3D xive2_nvgc_get_backlog(&nvgc, group_prio);
+ if (!count) {
+ return;
+ }
+ xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1);
+ xive2_router_write_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc);
+}
+
/*
* XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
*
@@ -588,8 +667,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, X=
iveTCTX *tctx,
uint8_t nvp_blk, uint32_t nvp_idx,
bool do_restore)
{
- uint8_t ipb, backlog_level;
- uint8_t backlog_prio;
+ XivePresenter *xptr =3D XIVE_PRESENTER(xrtr);
+ uint8_t ipb, backlog_level, group_level, first_group;
+ uint8_t backlog_prio, group_prio;
uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
Xive2Nvp nvp;
@@ -624,8 +704,22 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, =
XiveTCTX *tctx,
backlog_prio =3D xive_ipb_to_pipr(ipb);
backlog_level =3D 0;
+ first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);
+ if (first_group && regs[TM_LSMFB] < backlog_prio) {
+ group_prio =3D xive2_presenter_backlog_check(xptr, nvp_blk, nvp_id=
x,
+ first_group, &group_lev=
el);
+ regs[TM_LSMFB] =3D group_prio;
+ if (regs[TM_LGS] && group_prio < backlog_prio) {
+ /* VP can take a group interrupt */
+ xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx,
+ group_prio, group_level);
+ backlog_prio =3D group_prio;
+ backlog_level =3D group_level;
+ }
+ }
+
/*
- * Compute the PIPR based on the restored state.
+ * Compute the PIPR based on the restored state.
* It will raise the External interrupt signal if needed.
*/
xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level);
--
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 05/14] ppc/xive2: Add undelivered group interrupt to
backlog
Date: Mon, 9 Dec 2024 18:05:11 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When a group interrupt cannot be delivered, we need to:
- increment the backlog counter for the group in the NVG table
(if the END is configured to keep a backlog).
- start a broadcast operation to set the LSMFB field on matching CPUs
which can't take the interrupt now because they're running at too
high a priority.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive.h | 5 ++
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c | 42 +++++++++++++++++
hw/intc/xive2.c | 105 +++++++++++++++++++++++++++++++++++------
hw/ppc/pnv.c | 22 ++++++++-
5 files changed, 159 insertions(+), 16 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ce4eb9726b..f443a39cf1 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -442,6 +442,9 @@ struct XivePresenterClass {
uint32_t logic_serv, XiveTCTXMatch *match);
bool (*in_kernel)(const XivePresenter *xptr);
uint32_t (*get_config)(XivePresenter *xptr);
+ int (*broadcast)(XivePresenter *xptr,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority);
};
=20
int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
@@ -472,6 +475,8 @@ struct XiveFabricClass {
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
+ int (*broadcast)(XiveFabric *xfb, uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority);
};
=20
/*
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 65154f78d8..ebf301bb5b 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -120,6 +120,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, Xive=
TCTX *tctx,
void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority);
+void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority);
void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 5cdd4fdcc9..41b727d1fb 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -705,6 +705,47 @@ static uint32_t pnv_xive2_presenter_get_config(XivePre=
senter *xptr)
return cfg;
}
=20
+static int pnv_xive2_broadcast(XivePresenter *xptr,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority)
+{
+ PnvXive2 *xive =3D PNV_XIVE2(xptr);
+ PnvChip *chip =3D xive->chip;
+ int i, j;
+ bool gen1_tima_os =3D
+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
+
+ for (i =3D 0; i < chip->nr_cores; i++) {
+ PnvCore *pc =3D chip->cores[i];
+ CPUCore *cc =3D CPU_CORE(pc);
+
+ for (j =3D 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu =3D pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
+
+ tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ if (gen1_tima_os) {
+ ring =3D xive_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
+ nvt_idx, true, 0);
+ } else {
+ ring =3D xive2_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
+ nvt_idx, true, 0);
+ }
+
+ if (ring !=3D -1) {
+ xive2_tm_set_lsmfb(tctx, ring, priority);
+ }
+ }
+ }
+ return 0;
+}
+
static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr)
{
return pnv_xive2_block_id(PNV_XIVE2(xrtr));
@@ -2445,6 +2486,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, =
void *data)
=20
xpc->match_nvt =3D pnv_xive2_match_nvt;
xpc->get_config =3D pnv_xive2_presenter_get_config;
+ xpc->broadcast =3D pnv_xive2_broadcast;
};
=20
static const TypeInfo pnv_xive2_info =3D {
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index cffcf3ff05..05cb17518d 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -62,6 +62,30 @@ static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, =
uint8_t priority)
return val;
}
=20
+static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
+ uint32_t val)
+{
+ uint8_t *ptr, i;
+ uint32_t shift;
+
+ if (priority > 7) {
+ return;
+ }
+
+ if (val > 0xFFFFFF) {
+ val =3D 0xFFFFFF;
+ }
+ /*
+ * The per-priority backlog counters are 24-bit and the structure
+ * is stored in big endian
+ */
+ ptr =3D (uint8_t *)&nvgc->w2 + priority * 3;
+ for (i =3D 0; i < 3; i++, ptr++) {
+ shift =3D 8 * (2 - i);
+ *ptr =3D (val >> shift) & 0xFF;
+ }
+}
+
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
{
if (!xive2_eas_is_valid(eas)) {
@@ -830,6 +854,19 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, =
uint8_t priority)
return true;
}
=20
+void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+
+ /*
+ * Called by the router during a VP-group notification when the
+ * thread matches but can't take the interrupt because it's
+ * already running at a more favored priority. It then stores the
+ * new interrupt priority in the LSMFB field.
+ */
+ regs[TM_LSMFB] =3D priority;
+}
+
static void xive2_router_realize(DeviceState *dev, Error **errp)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(dev);
@@ -962,10 +999,9 @@ static void xive2_router_end_notify(Xive2Router *xrtr,=
uint8_t end_blk,
/*
* If no matching NVP is dispatched on a HW thread :
* - specific VP: update the NVP structure if backlog is activated
- * - logical server : forward request to IVPE (not supported)
+ * - VP-group: update the backlog counter for that priority in the NVG
*/
if (xive2_end_is_backlog(&end)) {
- uint8_t ipb;
=20
if (format =3D=3D 1) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -974,19 +1010,58 @@ static void xive2_router_end_notify(Xive2Router *xrt=
r, uint8_t end_blk,
return;
}
=20
- /*
- * Record the IPB in the associated NVP structure for later
- * use. The presenter will resend the interrupt when the vCPU
- * is dispatched again on a HW thread.
- */
- ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) |
- xive_priority_to_ipb(priority);
- nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
- xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
-
- /*
- * On HW, follows a "Broadcast Backlog" to IVPEs
- */
+ if (!xive2_end_is_ignore(&end)) {
+ uint8_t ipb;
+ /*
+ * Record the IPB in the associated NVP structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) |
+ xive_priority_to_ipb(priority);
+ nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+ } else {
+ Xive2Nvgc nvg;
+ uint32_t backlog;
+
+ /* For groups, the per-priority backlog counters are in the NV=
G */
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg)=
) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVG %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvgc_is_valid(&nvg)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid=
\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ /*
+ * Increment the backlog counter for that priority.
+ * For the precluded case, we only call broadcast the
+ * first time the counter is incremented. broadcast will
+ * set the LSMFB field of the TIMA of relevant threads so
+ * that they know an interrupt is pending.
+ */
+ backlog =3D xive2_nvgc_get_backlog(&nvg, priority) + 1;
+ xive2_nvgc_set_backlog(&nvg, priority, backlog);
+ xive2_router_write_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg);
+
+ if (precluded && backlog =3D=3D 1) {
+ XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb);
+ xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx, priority);
+
+ if (!xive2_end_is_precluded_escalation(&end)) {
+ /*
+ * The interrupt will be picked up when the
+ * matching thread lowers its priority level
+ */
+ return;
+ }
+ }
+ }
}
=20
do_escalation:
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0f0d7567d..7c11143749 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1,7 +1,9 @@
/*
* QEMU PowerPC PowerNV machine model
*
- * Copyright (c) 2016, IBM Corporation.
+ * Copyright (c) 2016-2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -2639,6 +2641,23 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uin=
t8_t format,
return total_count;
}
=20
+static int pnv10_xive_broadcast(XiveFabric *xfb,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ uint8_t priority)
+{
+ PnvMachineState *pnv =3D PNV_MACHINE(xfb);
+ int i;
+
+ for (i =3D 0; i < pnv->num_chips; i++) {
+ Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]);
+ XivePresenter *xptr =3D XIVE_PRESENTER(&chip10->xive);
+ XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
+
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, priority);
+ }
+ return 0;
+}
+
static bool pnv_machine_get_big_core(Object *obj, Error **errp)
{
PnvMachineState *pnv =3D PNV_MACHINE(obj);
@@ -2772,6 +2791,7 @@ static void pnv_machine_p10_common_class_init(ObjectC=
lass *oc, void *data)
pmc->dt_power_mgt =3D pnv_dt_power_mgt;
=20
xfc->match_nvt =3D pnv10_xive_match_nvt;
+ xfc->broadcast =3D pnv10_xive_broadcast;
=20
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
}
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 06/14] ppc/xive2: Process group backlog when updating the
CPPR
Date: Mon, 9 Dec 2024 18:05:14 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB
value is lower than the new CPPR value, there could be a pending group
interrupt in the backlog, so it needs to be scanned.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive2.h | 4 +
hw/intc/xive.c | 4 +-
hw/intc/xive2.c | 173 ++++++++++++++++++++++++++++++++++++++++-
3 files changed, 177 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index d88db05687..e61b978f37 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -115,6 +115,10 @@ typedef struct Xive2EndSource {
* XIVE2 Thread Interrupt Management Area (POWER10)
*/
=20
+void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size);
+void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offs=
et,
uint64_t value, unsigned size);
uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9345cddead..74a78da88b 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -603,7 +603,7 @@ static const XiveTmOp xive2_tm_operations[] =3D {
* MMIOs below 2K : raw values and special operations without side
* effects
*/
- { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr,
+ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive2_tm_set_os_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
NULL },
@@ -611,7 +611,7 @@ static const XiveTmOp xive2_tm_operations[] =3D {
NULL },
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
NULL },
- { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive2_tm_set_hv_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
NULL },
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 7130892482..0c53f71879 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -18,6 +18,7 @@
#include "hw/ppc/xive.h"
#include "hw/ppc/xive2.h"
#include "hw/ppc/xive2_regs.h"
+#include "trace.h"
=20
uint32_t xive2_router_get_config(Xive2Router *xrtr)
{
@@ -764,6 +765,172 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTC=
TX *tctx,
}
}
=20
+static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring,
+ uint32_t *nvp_blk, uint32_t *nvp_idx)
+{
+ uint32_t w2, cam;
+
+ w2 =3D xive_tctx_word2(&tctx->regs[ring]);
+ switch (ring) {
+ case TM_QW1_OS:
+ if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) {
+ return -1;
+ }
+ cam =3D xive_get_field32(TM2_QW1W2_OS_CAM, w2);
+ break;
+ case TM_QW2_HV_POOL:
+ if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) {
+ return -1;
+ }
+ cam =3D xive_get_field32(TM2_QW2W2_POOL_CAM, w2);
+ break;
+ case TM_QW3_HV_PHYS:
+ if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) {
+ return -1;
+ }
+ cam =3D xive2_tctx_hw_cam_line(tctx->xptr, tctx);
+ break;
+ default:
+ return -1;
+ }
+ *nvp_blk =3D xive2_nvp_blk(cam);
+ *nvp_idx =3D xive2_nvp_idx(cam);
+ return 0;
+}
+
+static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+ Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr);
+ uint8_t old_cppr, backlog_prio, first_group, group_level =3D 0;
+ uint8_t pipr_min, lsmfb_min, ring_min;
+ bool group_enabled;
+ uint32_t nvp_blk, nvp_idx;
+ Xive2Nvp nvp;
+ int rc;
+
+ trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring,
+ regs[TM_IPB], regs[TM_PIPR],
+ cppr, regs[TM_NSR]);
+
+ if (cppr > XIVE_PRIORITY_MAX) {
+ cppr =3D 0xff;
+ }
+
+ old_cppr =3D regs[TM_CPPR];
+ regs[TM_CPPR] =3D cppr;
+
+ /*
+ * Recompute the PIPR based on local pending interrupts. It will
+ * be adjusted below if needed in case of pending group interrupts.
+ */
+ pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]);
+ group_enabled =3D !!regs[TM_LGS];
+ lsmfb_min =3D (group_enabled) ? regs[TM_LSMFB] : 0xff;
+ ring_min =3D ring;
+
+ /* PHYS updates also depend on POOL values */
+ if (ring =3D=3D TM_QW3_HV_PHYS) {
+ uint8_t *pregs =3D &tctx->regs[TM_QW2_HV_POOL];
+
+ /* POOL values only matter if POOL ctx is valid */
+ if (pregs[TM_WORD2] & 0x80) {
+
+ uint8_t pool_pipr =3D xive_ipb_to_pipr(pregs[TM_IPB]);
+ uint8_t pool_lsmfb =3D pregs[TM_LSMFB];
+
+ /*
+ * Determine highest priority interrupt and
+ * remember which ring has it.
+ */
+ if (pool_pipr < pipr_min) {
+ pipr_min =3D pool_pipr;
+ if (pool_pipr < lsmfb_min) {
+ ring_min =3D TM_QW2_HV_POOL;
+ }
+ }
+
+ /* Values needed for group priority calculation */
+ if (pregs[TM_LGS] && (pool_lsmfb < lsmfb_min)) {
+ group_enabled =3D true;
+ lsmfb_min =3D pool_lsmfb;
+ if (lsmfb_min < pipr_min) {
+ ring_min =3D TM_QW2_HV_POOL;
+ }
+ }
+ }
+ }
+ regs[TM_PIPR] =3D pipr_min;
+
+ rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx);
+ if (rc) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\=
n");
+ return;
+ }
+
+ if (cppr < old_cppr) {
+ /*
+ * FIXME: check if there's a group interrupt being presented
+ * and if the new cppr prevents it. If so, then the group
+ * interrupt needs to be re-added to the backlog and
+ * re-triggered (see re-trigger END info in the NVGC
+ * structure)
+ */
+ }
+
+ if (group_enabled &&
+ lsmfb_min < cppr &&
+ lsmfb_min < regs[TM_PIPR]) {
+ /*
+ * Thread has seen a group interrupt with a higher priority
+ * than the new cppr or pending local interrupt. Check the
+ * backlog
+ */
+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);
+ if (!first_group) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ backlog_prio =3D xive2_presenter_backlog_check(tctx->xptr,
+ nvp_blk, nvp_idx,
+ first_group, &group_l=
evel);
+ tctx->regs[ring_min + TM_LSMFB] =3D backlog_prio;
+ if (backlog_prio !=3D 0xFF) {
+ xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx,
+ backlog_prio, group_level);
+ regs[TM_PIPR] =3D backlog_prio;
+ }
+ }
+ /* CPPR has changed, check if we need to raise a pending exception */
+ xive_tctx_notify(tctx, ring_min, group_level);
+}
+
+void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
+}
+
+void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
+}
+
static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t ta=
rget)
{
uint8_t *regs =3D &tctx->regs[ring];
@@ -934,7 +1101,9 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
=20
bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority)
{
- uint8_t *regs =3D &tctx->regs[ring];
+ /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
+ uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
+ uint8_t *alt_regs =3D &tctx->regs[alt_ring];
=20
/*
* The xive2_presenter_tctx_match() above tells if there's a match
@@ -942,7 +1111,7 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, =
uint8_t priority)
* priority to know if the thread can take the interrupt now or if
* it is precluded.
*/
- if (priority < regs[TM_CPPR]) {
+ if (priority < alt_regs[TM_CPPR]) {
return false;
}
return true;
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 06/14] ppc/xive2: Process group backlog when pushing an OS
context
Date: Mon, 9 Dec 2024 18:05:13 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When pushing an OS context, we were already checking if there was a
pending interrupt in the IPB and sending a notification if needed. We
also need to check if there is a pending group interrupt stored in the
NVG table. To avoid useless backlog scans, we only scan if the NVP
belongs to a group.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
hw/intc/xive2.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 05cb17518d..bb18a56e8f 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -278,6 +278,85 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t =
data)
end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
}
=20
+/*
+ * Scan the group chain and return the highest priority and group
+ * level of pending group interrupts.
+ */
+static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr,
+ uint8_t nvp_blk, uint32_t nvp_=
idx,
+ uint8_t first_group,
+ uint8_t *out_level)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint32_t nvgc_idx, mask;
+ uint32_t current_level, count;
+ uint8_t prio;
+ Xive2Nvgc nvgc;
+
+ for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) {
+ current_level =3D first_group & 0xF;
+
+ while (current_level) {
+ mask =3D (1 << current_level) - 1;
+ nvgc_idx =3D nvp_idx & ~mask;
+ nvgc_idx |=3D mask >> 1;
+ qemu_log("fxb %s checking backlog for prio %d group idx %x\n",
+ __func__, prio, nvgc_idx);
+
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvg=
c)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return 0xFF;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return 0xFF;
+ }
+
+ count =3D xive2_nvgc_get_backlog(&nvgc, prio);
+ if (count) {
+ *out_level =3D current_level;
+ return prio;
+ }
+ current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0xF;
+ }
+ }
+ return 0xFF;
+}
+
+static void xive2_presenter_backlog_decr(XivePresenter *xptr,
+ uint8_t nvp_blk, uint32_t nvp_idx,
+ uint8_t group_prio,
+ uint8_t group_level)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint32_t nvgc_idx, mask, count;
+ Xive2Nvgc nvgc;
+
+ group_level &=3D 0xF;
+ mask =3D (1 << group_level) - 1;
+ nvgc_idx =3D nvp_idx & ~mask;
+ nvgc_idx |=3D mask >> 1;
+
+ if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
+ nvp_blk, nvgc_idx);
+ return;
+ }
+ count =3D xive2_nvgc_get_backlog(&nvgc, group_prio);
+ if (!count) {
+ return;
+ }
+ xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1);
+ xive2_router_write_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc);
+}
+
/*
* XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
*
@@ -587,9 +666,13 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, =
XiveTCTX *tctx,
uint8_t nvp_blk, uint32_t nvp_idx,
bool do_restore)
{
+ XivePresenter *xptr =3D XIVE_PRESENTER(xrtr);
uint8_t ipb;
uint8_t backlog_level;
+ uint8_t group_level;
+ uint8_t first_group;
uint8_t backlog_prio;
+ uint8_t group_prio;
uint8_t *regs =3D &tctx->regs[TM_QW1_OS];
Xive2Nvp nvp;
=20
@@ -624,6 +707,20 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, =
XiveTCTX *tctx,
backlog_prio =3D xive_ipb_to_pipr(ipb);
backlog_level =3D 0;
=20
+ first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);
+ if (first_group && regs[TM_LSMFB] < backlog_prio) {
+ group_prio =3D xive2_presenter_backlog_scan(xptr, nvp_blk, nvp_idx,
+ first_group, &group_leve=
l);
+ regs[TM_LSMFB] =3D group_prio;
+ if (regs[TM_LGS] && group_prio < backlog_prio) {
+ /* VP can take a group interrupt */
+ xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx,
+ group_prio, group_level);
+ backlog_prio =3D group_prio;
+ backlog_level =3D group_level;
+ }
+ }
+
/*
* Compute the PIPR based on the restored state.
* It will raise the External interrupt signal if needed.
--=20
2.43.0
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Subject: [PATCH v2 07/14] ppc/xive2: Process group backlog when updating the
CPPR
Date: Mon, 9 Dec 2024 18:05:15 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB
value is lower than the new CPPR value, there could be a pending group
interrupt in the backlog, so it needs to be scanned.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive2.h | 4 +
hw/intc/xive.c | 4 +-
hw/intc/xive2.c | 173 ++++++++++++++++++++++++++++++++++++++++-
3 files changed, 177 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index ebf301bb5b..fc7422fea7 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -113,6 +113,10 @@ typedef struct Xive2EndSource {
* XIVE2 Thread Interrupt Management Area (POWER10)
*/
=20
+void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size);
+void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size);
void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offs=
et,
uint64_t value, unsigned size);
uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 412bb94b91..308de5aefc 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -589,7 +589,7 @@ static const XiveTmOp xive2_tm_operations[] =3D {
* MMIOs below 2K : raw values and special operations without side
* effects
*/
- { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr,
+ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive2_tm_set_os_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
NULL },
@@ -597,7 +597,7 @@ static const XiveTmOp xive2_tm_operations[] =3D {
NULL },
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
NULL },
- { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive2_tm_set_hv_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
NULL },
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index bb18a56e8f..47f7a099de 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -17,6 +17,7 @@
#include "hw/ppc/xive.h"
#include "hw/ppc/xive2.h"
#include "hw/ppc/xive2_regs.h"
+#include "trace.h"
=20
uint32_t xive2_router_get_config(Xive2Router *xrtr)
{
@@ -767,6 +768,172 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTC=
TX *tctx,
}
}
=20
+static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring,
+ uint32_t *nvp_blk, uint32_t *nvp_idx)
+{
+ uint32_t w2, cam;
+
+ w2 =3D xive_tctx_word2(&tctx->regs[ring]);
+ switch (ring) {
+ case TM_QW1_OS:
+ if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) {
+ return -1;
+ }
+ cam =3D xive_get_field32(TM2_QW1W2_OS_CAM, w2);
+ break;
+ case TM_QW2_HV_POOL:
+ if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) {
+ return -1;
+ }
+ cam =3D xive_get_field32(TM2_QW2W2_POOL_CAM, w2);
+ break;
+ case TM_QW3_HV_PHYS:
+ if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) {
+ return -1;
+ }
+ cam =3D xive2_tctx_hw_cam_line(tctx->xptr, tctx);
+ break;
+ default:
+ return -1;
+ }
+ *nvp_blk =3D xive2_nvp_blk(cam);
+ *nvp_idx =3D xive2_nvp_idx(cam);
+ return 0;
+}
+
+static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
+{
+ uint8_t *regs =3D &tctx->regs[ring];
+ Xive2Router *xrtr =3D XIVE2_ROUTER(tctx->xptr);
+ uint8_t old_cppr, backlog_prio, first_group, group_level =3D 0;
+ uint8_t pipr_min, lsmfb_min, ring_min;
+ bool group_enabled;
+ uint32_t nvp_blk, nvp_idx;
+ Xive2Nvp nvp;
+ int rc;
+
+ trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring,
+ regs[TM_IPB], regs[TM_PIPR],
+ cppr, regs[TM_NSR]);
+
+ if (cppr > XIVE_PRIORITY_MAX) {
+ cppr =3D 0xff;
+ }
+
+ old_cppr =3D regs[TM_CPPR];
+ regs[TM_CPPR] =3D cppr;
+
+ /*
+ * Recompute the PIPR based on local pending interrupts. It will
+ * be adjusted below if needed in case of pending group interrupts.
+ */
+ pipr_min =3D xive_ipb_to_pipr(regs[TM_IPB]);
+ group_enabled =3D !!regs[TM_LGS];
+ lsmfb_min =3D (group_enabled) ? regs[TM_LSMFB] : 0xff;
+ ring_min =3D ring;
+
+ /* PHYS updates also depend on POOL values */
+ if (ring =3D=3D TM_QW3_HV_PHYS) {
+ uint8_t *pregs =3D &tctx->regs[TM_QW2_HV_POOL];
+
+ /* POOL values only matter if POOL ctx is valid */
+ if (pregs[TM_WORD2] & 0x80) {
+
+ uint8_t pool_pipr =3D xive_ipb_to_pipr(pregs[TM_IPB]);
+ uint8_t pool_lsmfb =3D pregs[TM_LSMFB];
+
+ /*
+ * Determine highest priority interrupt and
+ * remember which ring has it.
+ */
+ if (pool_pipr < pipr_min) {
+ pipr_min =3D pool_pipr;
+ if (pool_pipr < lsmfb_min) {
+ ring_min =3D TM_QW2_HV_POOL;
+ }
+ }
+
+ /* Values needed for group priority calculation */
+ if (pregs[TM_LGS] && (pool_lsmfb < lsmfb_min)) {
+ group_enabled =3D true;
+ lsmfb_min =3D pool_lsmfb;
+ if (lsmfb_min < pipr_min) {
+ ring_min =3D TM_QW2_HV_POOL;
+ }
+ }
+ }
+ }
+ regs[TM_PIPR] =3D pipr_min;
+
+ rc =3D xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx);
+ if (rc) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\=
n");
+ return;
+ }
+
+ if (cppr < old_cppr) {
+ /*
+ * FIXME: check if there's a group interrupt being presented
+ * and if the new cppr prevents it. If so, then the group
+ * interrupt needs to be re-added to the backlog and
+ * re-triggered (see re-trigger END info in the NVGC
+ * structure)
+ */
+ }
+
+ if (group_enabled &&
+ lsmfb_min < cppr &&
+ lsmfb_min < regs[TM_PIPR]) {
+ /*
+ * Thread has seen a group interrupt with a higher priority
+ * than the new cppr or pending local interrupt. Check the
+ * backlog
+ */
+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ first_group =3D xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);
+ if (!first_group) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ backlog_prio =3D xive2_presenter_backlog_scan(tctx->xptr,
+ nvp_blk, nvp_idx,
+ first_group, &group_le=
vel);
+ tctx->regs[ring_min + TM_LSMFB] =3D backlog_prio;
+ if (backlog_prio !=3D 0xFF) {
+ xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx,
+ backlog_prio, group_level);
+ regs[TM_PIPR] =3D backlog_prio;
+ }
+ }
+ /* CPPR has changed, check if we need to raise a pending exception */
+ xive_tctx_notify(tctx, ring_min, group_level);
+}
+
+void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
+}
+
+void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
+}
+
static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t ta=
rget)
{
uint8_t *regs =3D &tctx->regs[ring];
@@ -937,7 +1104,9 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
=20
bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority)
{
- uint8_t *regs =3D &tctx->regs[ring];
+ /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */
+ uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : r=
ing;
+ uint8_t *alt_regs =3D &tctx->regs[alt_ring];
=20
/*
* The xive2_presenter_tctx_match() above tells if there's a match
@@ -945,7 +1114,7 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, =
uint8_t priority)
* priority to know if the thread can take the interrupt now or if
* it is precluded.
*/
- if (priority < regs[TM_CPPR]) {
+ if (priority < alt_regs[TM_CPPR]) {
return false;
}
return true;
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 07/14] qtest/xive: Add group-interrupt test
Date: Mon, 9 Dec 2024 18:05:16 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
Add XIVE2 tests for group interrupts and group interrupts that have
been backlogged.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
tests/qtest/pnv-xive2-test.c | 160 +++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index dd19e88861..a4d06550ee 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -2,6 +2,8 @@
* QTest testcase for PowerNV 10 interrupt controller (xive2)
* - Test irq to hardware thread
* - Test 'Pull Thread Context to Odd Thread Reporting Line'
+ * - Test irq to hardware group
+ * - Test irq to hardware group going through backlog
*
* Copyright (c) 2024, IBM Corporation.
*
@@ -315,6 +317,158 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTe=
stState *qts)
word2 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2);
g_assert_cmphex(xive_get_field32(TM_QW3W2_VT, word2), =3D=3D, 0);
}
+
+static void test_hw_group_irq(QTestState *qts)
+{
+ uint32_t irq =3D 100;
+ uint32_t irq_data =3D 0xdeadbeef;
+ uint32_t end_index =3D 23;
+ uint32_t chosen_one;
+ uint32_t target_nvp =3D 0x81; /* group size =3D 4 */
+ uint8_t priority =3D 6;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing irq %d to hardware group of size 4\n", irq);
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, true /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING);
+
+ /* find the targeted vCPU */
+ for (chosen_one =3D 0; chosen_one < SMT; chosen_one++) {
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ if (nsr =3D=3D 0x82) {
+ break;
+ }
+ }
+ g_assert_cmphex(chosen_one, <, SMT);
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+
+ /* ack the irq */
+ reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
+ nsr =3D reg16 >> 8;
+ cppr =3D reg16 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority);
+
+ /* check irq data is what was configured */
+ reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff));
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x00);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+}
+
+static void test_hw_group_irq_backlog(QTestState *qts)
+{
+ uint32_t irq =3D 31;
+ uint32_t irq_data =3D 0x01234567;
+ uint32_t end_index =3D 129;
+ uint32_t target_nvp =3D 0x81; /* group size =3D 4 */
+ uint32_t chosen_one =3D 3;
+ uint8_t blocking_priority, priority =3D 3;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr, lsmfb, i;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing irq %d to hardware group of size 4 going through " \
+ "backlog\n",
+ irq);
+
+ /*
+ * set current priority of all threads in the group to something
+ * higher than what we're about to trigger
+ */
+ blocking_priority =3D priority - 1;
+ for (i =3D 0; i < SMT; i++) {
+ set_tima8(qts, i, TM_QW3_HV_PHYS + TM_CPPR, blocking_priority);
+ }
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, true /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING);
+
+ /* check no interrupt is pending on the 2 possible targets */
+ for (i =3D 0; i < SMT; i++) {
+ reg32 =3D get_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ lsmfb =3D reg32 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x0);
+ g_assert_cmphex(cppr, =3D=3D, blocking_priority);
+ g_assert_cmphex(lsmfb, =3D=3D, priority);
+ }
+
+ /* lower priority of one thread */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, priority + 1);
+
+ /* check backlogged interrupt is presented */
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority + 1);
+
+ /* ack the irq */
+ reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
+ nsr =3D reg16 >> 8;
+ cppr =3D reg16 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority);
+
+ /* check irq data is what was configured */
+ reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff));
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ lsmfb =3D reg32 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x00);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+ g_assert_cmphex(lsmfb, =3D=3D, 0xFF);
+}
+
static void test_xive(void)
{
QTestState *qts;
@@ -330,6 +484,12 @@ static void test_xive(void)
/* omit reset_state here and use settings from test_hw_irq */
test_pull_thread_ctx_to_odd_thread_cl(qts);
=20
+ reset_state(qts);
+ test_hw_group_irq(qts);
+
+ reset_state(qts);
+ test_hw_group_irq_backlog(qts);
+
reset_state(qts);
test_flush_sync_inject(qts);
=20
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 08/14] qtest/xive: Add group-interrupt test
Date: Mon, 9 Dec 2024 18:05:18 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
Add XIVE2 tests for group interrupts and group interrupts that have
been backlogged.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/pnv-xive2-test.c | 160 +++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index dd19e88861..a4d06550ee 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -2,6 +2,8 @@
* QTest testcase for PowerNV 10 interrupt controller (xive2)
* - Test irq to hardware thread
* - Test 'Pull Thread Context to Odd Thread Reporting Line'
+ * - Test irq to hardware group
+ * - Test irq to hardware group going through backlog
*
* Copyright (c) 2024, IBM Corporation.
*
@@ -315,6 +317,158 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTe=
stState *qts)
word2 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2);
g_assert_cmphex(xive_get_field32(TM_QW3W2_VT, word2), =3D=3D, 0);
}
+
+static void test_hw_group_irq(QTestState *qts)
+{
+ uint32_t irq =3D 100;
+ uint32_t irq_data =3D 0xdeadbeef;
+ uint32_t end_index =3D 23;
+ uint32_t chosen_one;
+ uint32_t target_nvp =3D 0x81; /* group size =3D 4 */
+ uint8_t priority =3D 6;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing irq %d to hardware group of size 4\n", irq);
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, true /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING);
+
+ /* find the targeted vCPU */
+ for (chosen_one =3D 0; chosen_one < SMT; chosen_one++) {
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ if (nsr =3D=3D 0x82) {
+ break;
+ }
+ }
+ g_assert_cmphex(chosen_one, <, SMT);
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+
+ /* ack the irq */
+ reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
+ nsr =3D reg16 >> 8;
+ cppr =3D reg16 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority);
+
+ /* check irq data is what was configured */
+ reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff));
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x00);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+}
+
+static void test_hw_group_irq_backlog(QTestState *qts)
+{
+ uint32_t irq =3D 31;
+ uint32_t irq_data =3D 0x01234567;
+ uint32_t end_index =3D 129;
+ uint32_t target_nvp =3D 0x81; /* group size =3D 4 */
+ uint32_t chosen_one =3D 3;
+ uint8_t blocking_priority, priority =3D 3;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr, lsmfb, i;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing irq %d to hardware group of size 4 going through " \
+ "backlog\n",
+ irq);
+
+ /*
+ * set current priority of all threads in the group to something
+ * higher than what we're about to trigger
+ */
+ blocking_priority =3D priority - 1;
+ for (i =3D 0; i < SMT; i++) {
+ set_tima8(qts, i, TM_QW3_HV_PHYS + TM_CPPR, blocking_priority);
+ }
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, true /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING);
+
+ /* check no interrupt is pending on the 2 possible targets */
+ for (i =3D 0; i < SMT; i++) {
+ reg32 =3D get_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ lsmfb =3D reg32 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x0);
+ g_assert_cmphex(cppr, =3D=3D, blocking_priority);
+ g_assert_cmphex(lsmfb, =3D=3D, priority);
+ }
+
+ /* lower priority of one thread */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, priority + 1);
+
+ /* check backlogged interrupt is presented */
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority + 1);
+
+ /* ack the irq */
+ reg16 =3D get_tima16(qts, chosen_one, TM_SPC_ACK_HV_REG);
+ nsr =3D reg16 >> 8;
+ cppr =3D reg16 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x82);
+ g_assert_cmphex(cppr, =3D=3D, priority);
+
+ /* check irq data is what was configured */
+ reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff));
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, chosen_one, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 =3D get_tima32(qts, chosen_one, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ lsmfb =3D reg32 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x00);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+ g_assert_cmphex(lsmfb, =3D=3D, 0xFF);
+}
+
static void test_xive(void)
{
QTestState *qts;
@@ -330,6 +484,12 @@ static void test_xive(void)
/* omit reset_state here and use settings from test_hw_irq */
test_pull_thread_ctx_to_odd_thread_cl(qts);
=20
+ reset_state(qts);
+ test_hw_group_irq(qts);
+
+ reset_state(qts);
+ test_hw_group_irq_backlog(qts);
+
reset_state(qts);
test_flush_sync_inject(qts);
=20
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
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lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 08/14] Add support for MMIO operations on the NVPG/NVC BAR
Date: Mon, 9 Dec 2024 18:05:17 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
Add support for the NVPG and NVC BARs. Access to the BAR pages will
cause backlog counter operations to either increment or decriment
the counter.
Also added qtests for the same.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive2.h | 9 ++
include/hw/ppc/xive2_regs.h | 3 +
tests/qtest/pnv-xive2-common.h | 1 +
hw/intc/pnv_xive2.c | 80 +++++++++++++---
hw/intc/xive2.c | 87 +++++++++++++++++
tests/qtest/pnv-xive2-nvpg_bar.c | 154 +++++++++++++++++++++++++++++++
tests/qtest/pnv-xive2-test.c | 3 +
hw/intc/trace-events | 4 +
tests/qtest/meson.build | 3 +-
9 files changed, 329 insertions(+), 15 deletions(-)
create mode 100644 tests/qtest/pnv-xive2-nvpg_bar.c
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index e61b978f37..049028d2c2 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -92,6 +92,15 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint32_t logic_serv);
=20
+uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset);
+
+uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
+ bool crowd,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset, uint16_t val);
+
/*
* XIVE2 END ESBs (POWER10)
*/
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 30868e8e09..66a419441c 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -234,4 +234,7 @@ typedef struct Xive2Nvgc {
void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx,
GString *buf);
=20
+#define NVx_BACKLOG_OP PPC_BITMASK(52, 53)
+#define NVx_BACKLOG_PRIO PPC_BITMASK(57, 59)
+
#endif /* PPC_XIVE2_REGS_H */
diff --git a/tests/qtest/pnv-xive2-common.h b/tests/qtest/pnv-xive2-common.h
index 9ae34771aa..2077c05ebc 100644
--- a/tests/qtest/pnv-xive2-common.h
+++ b/tests/qtest/pnv-xive2-common.h
@@ -107,5 +107,6 @@ extern void set_end(QTestState *qts, uint32_t index, ui=
nt32_t nvp_index,
=20
=20
void test_flush_sync_inject(QTestState *qts);
+void test_nvpg_bar(QTestState *qts);
=20
#endif /* TEST_PNV_XIVE2_COMMON_H */
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 0482193fd7..9736b623ba 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -2203,21 +2203,40 @@ static const MemoryRegionOps pnv_xive2_tm_ops =3D {
},
};
=20
-static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset,
+static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset);
- return -1;
+ if (size !=3D 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc load size %d\n",
+ size);
+ return -1;
+ }
+
+ return xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, 1);
}
=20
-static void pnv_xive2_nvc_write(void *opaque, hwaddr offset,
+static void pnv_xive2_nvc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvc_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset);
+ if (size !=3D 1) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc write size %d\n",
+ size);
+ return;
+ }
+
+ (void)xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, val);
}
=20
static const MemoryRegionOps pnv_xive2_nvc_ops =3D {
@@ -2225,30 +2244,63 @@ static const MemoryRegionOps pnv_xive2_nvc_ops =3D {
.write =3D pnv_xive2_nvc_write,
.endianness =3D DEVICE_BIG_ENDIAN,
.valid =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
.impl =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
};
=20
-static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset,
+static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint32_t index =3D page >> 1;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset);
- return -1;
+ if (size !=3D 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg load size %d\n",
+ size);
+ return -1;
+ }
+
+ if (page % 2) {
+ /* odd page - NVG */
+ return xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op=
, 1);
+ } else {
+ /* even page - NVP */
+ return xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
+ }
}
=20
-static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset,
+static void pnv_xive2_nvpg_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint32_t index =3D page >> 1;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset);
+ if (size !=3D 1) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg write size %d\n=
",
+ size);
+ return;
+ }
+
+ if (page % 2) {
+ /* odd page - NVG */
+ (void)xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op,=
val);
+ } else {
+ /* even page - NVP */
+ (void)xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
+ }
}
=20
static const MemoryRegionOps pnv_xive2_nvpg_ops =3D {
@@ -2256,11 +2308,11 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops =3D=
{
.write =3D pnv_xive2_nvpg_write,
.endianness =3D DEVICE_BIG_ENDIAN,
.valid =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
.impl =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
};
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 0c53f71879..b6f279e6a3 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -88,6 +88,93 @@ static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint=
8_t priority,
}
}
=20
+uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
+ bool crowd,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset, uint16_t val)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint8_t priority =3D GETFIELD(NVx_BACKLOG_PRIO, offset);
+ uint8_t op =3D GETFIELD(NVx_BACKLOG_OP, offset);
+ Xive2Nvgc nvgc;
+ uint32_t count, old_count;
+
+ if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n",
+ crowd ? "NVC" : "NVG", blk, idx);
+ return -1;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, i=
dx);
+ return -1;
+ }
+
+ old_count =3D xive2_nvgc_get_backlog(&nvgc, priority);
+ count =3D old_count;
+ /*
+ * op:
+ * 0b00 =3D> increment
+ * 0b01 =3D> decrement
+ * 0b1- =3D> read
+ */
+ if (op =3D=3D 0b00 || op =3D=3D 0b01) {
+ if (op =3D=3D 0b00) {
+ count +=3D val;
+ } else {
+ if (count > val) {
+ count -=3D val;
+ } else {
+ count =3D 0;
+ }
+ }
+ xive2_nvgc_set_backlog(&nvgc, priority, count);
+ xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc);
+ }
+ trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count);
+ return old_count;
+}
+
+uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint8_t priority =3D GETFIELD(NVx_BACKLOG_PRIO, offset);
+ uint8_t op =3D GETFIELD(NVx_BACKLOG_OP, offset);
+ Xive2Nvp nvp;
+ uint8_t ipb, old_ipb, rc;
+
+ if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx);
+ return -1;
+ }
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, i=
dx);
+ return -1;
+ }
+
+ old_ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2);
+ ipb =3D old_ipb;
+ /*
+ * op:
+ * 0b00 =3D> set priority bit
+ * 0b01 =3D> reset priority bit
+ * 0b1- =3D> read
+ */
+ if (op =3D=3D 0b00 || op =3D=3D 0b01) {
+ if (op =3D=3D 0b00) {
+ ipb |=3D xive_priority_to_ipb(priority);
+ } else {
+ ipb &=3D ~xive_priority_to_ipb(priority);
+ }
+ nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
+ xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2);
+ }
+ rc =3D !!(old_ipb & xive_priority_to_ipb(priority));
+ trace_xive_nvp_backlog_op(blk, idx, op, priority, rc);
+ return rc;
+}
+
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
{
if (!xive2_eas_is_valid(eas)) {
diff --git a/tests/qtest/pnv-xive2-nvpg_bar.c b/tests/qtest/pnv-xive2-nvpg_=
bar.c
new file mode 100644
index 0000000000..10d4962d1e
--- /dev/null
+++ b/tests/qtest/pnv-xive2-nvpg_bar.c
@@ -0,0 +1,154 @@
+/*
+ * QTest testcase for PowerNV 10 interrupt controller (xive2)
+ * - Test NVPG BAR MMIO operations
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+#include "pnv-xive2-common.h"
+
+#define NVPG_BACKLOG_OP_SHIFT 10
+#define NVPG_BACKLOG_PRIO_SHIFT 4
+
+#define XIVE_PRIORITY_MAX 7
+
+enum NVx {
+ NVP,
+ NVG,
+ NVC
+};
+
+typedef enum {
+ INCR_STORE =3D 0b100,
+ INCR_LOAD =3D 0b000,
+ DECR_STORE =3D 0b101,
+ DECR_LOAD =3D 0b001,
+ READ_x =3D 0b010,
+ READ_y =3D 0b011,
+} backlog_op;
+
+static uint32_t nvpg_backlog_op(QTestState *qts, backlog_op op,
+ enum NVx type, uint64_t index,
+ uint8_t priority, uint8_t delta)
+{
+ uint64_t addr, offset;
+ uint32_t count =3D 0;
+
+ switch (type) {
+ case NVP:
+ addr =3D XIVE_NVPG_ADDR + (index << (XIVE_PAGE_SHIFT + 1));
+ break;
+ case NVG:
+ addr =3D XIVE_NVPG_ADDR + (index << (XIVE_PAGE_SHIFT + 1)) +
+ (1 << XIVE_PAGE_SHIFT);
+ break;
+ case NVC:
+ addr =3D XIVE_NVC_ADDR + (index << XIVE_PAGE_SHIFT);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ offset =3D (op & 0b11) << NVPG_BACKLOG_OP_SHIFT;
+ offset |=3D priority << NVPG_BACKLOG_PRIO_SHIFT;
+ if (op >> 2) {
+ qtest_writeb(qts, addr + offset, delta);
+ } else {
+ count =3D qtest_readw(qts, addr + offset);
+ }
+ return count;
+}
+
+void test_nvpg_bar(QTestState *qts)
+{
+ uint32_t nvp_target =3D 0x11;
+ uint32_t group_target =3D 0x17; /* size 16 */
+ uint32_t vp_irq =3D 33, group_irq =3D 47;
+ uint32_t vp_end =3D 3, group_end =3D 97;
+ uint32_t vp_irq_data =3D 0x33333333;
+ uint32_t group_irq_data =3D 0x66666666;
+ uint8_t vp_priority =3D 0, group_priority =3D 5;
+ uint32_t vp_count[XIVE_PRIORITY_MAX + 1] =3D { 0 };
+ uint32_t group_count[XIVE_PRIORITY_MAX + 1] =3D { 0 };
+ uint32_t count, delta;
+ uint8_t i;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing NVPG BAR operations\n");
+
+ set_nvg(qts, group_target, 0);
+ set_nvp(qts, nvp_target, 0x04);
+ set_nvp(qts, group_target, 0x04);
+
+ /*
+ * Setup: trigger a VP-specific interrupt and a group interrupt
+ * so that the backlog counters are initialized to something else
+ * than 0 for at least one priority level
+ */
+ set_eas(qts, vp_irq, vp_end, vp_irq_data);
+ set_end(qts, vp_end, nvp_target, vp_priority, false /* group */);
+
+ set_eas(qts, group_irq, group_end, group_irq_data);
+ set_end(qts, group_end, group_target, group_priority, true /* group */=
);
+
+ get_esb(qts, vp_irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, vp_irq, XIVE_TRIGGER_PAGE, 0, 0);
+ vp_count[vp_priority]++;
+
+ get_esb(qts, group_irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, group_irq, XIVE_TRIGGER_PAGE, 0, 0);
+ group_count[group_priority]++;
+
+ /* check the initial counters */
+ for (i =3D 0; i <=3D XIVE_PRIORITY_MAX; i++) {
+ count =3D nvpg_backlog_op(qts, READ_x, NVP, nvp_target, i, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[i]);
+
+ count =3D nvpg_backlog_op(qts, READ_y, NVG, group_target, i, 0);
+ g_assert_cmpuint(count, =3D=3D, group_count[i]);
+ }
+
+ /* do a few ops on the VP. Counter can only be 0 and 1 */
+ vp_priority =3D 2;
+ delta =3D 7;
+ nvpg_backlog_op(qts, INCR_STORE, NVP, nvp_target, vp_priority, delta);
+ vp_count[vp_priority] =3D 1;
+ count =3D nvpg_backlog_op(qts, INCR_LOAD, NVP, nvp_target, vp_priority=
, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+ count =3D nvpg_backlog_op(qts, READ_y, NVP, nvp_target, vp_priority, 0=
);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+
+ count =3D nvpg_backlog_op(qts, DECR_LOAD, NVP, nvp_target, vp_priority=
, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+ vp_count[vp_priority] =3D 0;
+ nvpg_backlog_op(qts, DECR_STORE, NVP, nvp_target, vp_priority, delta);
+ count =3D nvpg_backlog_op(qts, READ_x, NVP, nvp_target, vp_priority, 0=
);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+
+ /* do a few ops on the group */
+ group_priority =3D 2;
+ delta =3D 9;
+ /* can't go negative */
+ nvpg_backlog_op(qts, DECR_STORE, NVG, group_target, group_priority, de=
lta);
+ count =3D nvpg_backlog_op(qts, READ_y, NVG, group_target, group_priori=
ty, 0);
+ g_assert_cmpuint(count, =3D=3D, 0);
+ nvpg_backlog_op(qts, INCR_STORE, NVG, group_target, group_priority, de=
lta);
+ group_count[group_priority] +=3D delta;
+ count =3D nvpg_backlog_op(qts, INCR_LOAD, NVG, group_target,
+ group_priority, delta);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+ group_count[group_priority]++;
+
+ count =3D nvpg_backlog_op(qts, DECR_LOAD, NVG, group_target,
+ group_priority, delta);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+ group_count[group_priority]--;
+ count =3D nvpg_backlog_op(qts, READ_x, NVG, group_target, group_priori=
ty, 0);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+}
+
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index a4d06550ee..a0e9f19313 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -493,6 +493,9 @@ static void test_xive(void)
reset_state(qts);
test_flush_sync_inject(qts);
=20
+ reset_state(qts);
+ test_nvpg_bar(qts);
+
qtest_quit(qts);
}
=20
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 7435728c51..7f362c38b0 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -285,6 +285,10 @@ xive_tctx_tm_read(uint32_t index, uint64_t offset, uns=
igned int size, uint64_t v
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uin=
t8_t group_level) "found NVT 0x%x/0x%x ring=3D0x%x group_level=3D%d"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "EN=
D 0x%x/0x%x @0x%"PRIx64
=20
+# xive2.c
+xive_nvp_backlog_op(uint8_t blk, uint32_t idx, uint8_t op, uint8_t priorit=
y, uint8_t rc) "NVP 0x%x/0x%x operation=3D%d priority=3D%d rc=3D%d"
+xive_nvgc_backlog_op(bool c, uint8_t blk, uint32_t idx, uint8_t op, uint8_=
t priority, uint32_t rc) "NVGC crowd=3D%d 0x%x/0x%x operation=3D%d priority=
=3D%d rc=3D%d"
+
# pnv_xive.c
pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=3D0x=
%"PRIx64
=20
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 0dbdb59a55..352760545e 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -346,7 +346,8 @@ qtests =3D {
'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'],
'migration-test': migration_files,
'pxe-test': files('boot-sector.c'),
- 'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c'),
+ 'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c',
+ 'pnv-xive2-nvpg_bar.c'),
'qos-test': [chardev, io, qos_test_ss.apply({}).sources()],
'tpm-crb-swtpm-test': [io, tpmemu_files],
'tpm-crb-test': [io, tpmemu_files],
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 09/14] ppc/xive2: Support crowd-matching when looking for
target
Date: Mon, 9 Dec 2024 18:05:20 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
If an END is defined with the 'crowd' bit set, then a target can be
running on different blocks. It means that some bits from the block
VP are masked when looking for a match. It is similar to groups, but
on the block instead of the VP index.
Most of the changes are due to passing the extra argument 'crowd' all
the way to the function checking for matches.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive.h | 10 +++---
include/hw/ppc/xive2.h | 3 +-
hw/intc/pnv_xive.c | 5 +--
hw/intc/pnv_xive2.c | 12 +++----
hw/intc/spapr_xive.c | 3 +-
hw/intc/xive.c | 21 ++++++++----
hw/intc/xive2.c | 78 +++++++++++++++++++++++++++++++++---------
hw/ppc/pnv.c | 15 ++++----
hw/ppc/spapr.c | 4 +--
9 files changed, 105 insertions(+), 46 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index c15cd4358d..187a03d55c 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -440,13 +440,13 @@ struct XivePresenterClass {
InterfaceClass parent;
int (*match_nvt)(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
bool (*in_kernel)(const XivePresenter *xptr);
uint32_t (*get_config)(XivePresenter *xptr);
int (*broadcast)(XivePresenter *xptr,
uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority);
+ bool crowd, bool cam_ignore, uint8_t priority);
};
=20
int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
@@ -455,7 +455,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
bool cam_ignore, uint32_t logic_serv);
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, bool *precluded);
=20
uint32_t xive_get_vpgroup_size(uint32_t nvp_index);
@@ -475,10 +475,10 @@ struct XiveFabricClass {
InterfaceClass parent;
int (*match_nvt)(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
int (*broadcast)(XiveFabric *xfb, uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority);
+ bool crowd, bool cam_ignore, uint8_t priority);
};
=20
/*
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 049028d2c2..37aca4d26a 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -90,7 +90,8 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t lisn,=
bool pq_checked);
int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv);
+ bool crowd, bool cam_ignore,
+ uint32_t logic_serv);
=20
uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
uint8_t blk, uint32_t idx,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 5bacbce6a4..346549f32e 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -473,7 +473,7 @@ static bool pnv_xive_is_cpu_enabled(PnvXive *xive, Powe=
rPCCPU *cpu)
=20
static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priorit=
y,
uint32_t logic_serv, XiveTCTXMatch *match)
{
PnvXive *xive =3D PNV_XIVE(xptr);
@@ -500,7 +500,8 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint=
8_t format,
* Check the thread context CAM lines and record matches.
*/
ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
- nvt_idx, cam_ignore, logic_se=
rv);
+ nvt_idx, cam_ignore,
+ logic_serv);
/*
* Save the context and follow on to catch duplicates, that we
* don't support yet.
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 9736b623ba..236f9d7eb7 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -625,7 +625,7 @@ static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, Po=
werPCCPU *cpu)
=20
static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priori=
ty,
uint32_t logic_serv, XiveTCTXMatch *match)
{
PnvXive2 *xive =3D PNV_XIVE2(xptr);
@@ -656,8 +656,8 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uin=
t8_t format,
logic_serv);
} else {
ring =3D xive2_presenter_tctx_match(xptr, tctx, format, nv=
t_blk,
- nvt_idx, cam_ignore,
- logic_serv);
+ nvt_idx, crowd, cam_igno=
re,
+ logic_serv);
}
=20
if (ring !=3D -1) {
@@ -708,7 +708,7 @@ static uint32_t pnv_xive2_presenter_get_config(XivePres=
enter *xptr)
=20
static int pnv_xive2_broadcast(XivePresenter *xptr,
uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority)
+ bool crowd, bool ignore, uint8_t priority)
{
PnvXive2 *xive =3D PNV_XIVE2(xptr);
PnvChip *chip =3D xive->chip;
@@ -733,10 +733,10 @@ static int pnv_xive2_broadcast(XivePresenter *xptr,
=20
if (gen1_tima_os) {
ring =3D xive_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
- nvt_idx, true, 0);
+ nvt_idx, ignore, 0);
} else {
ring =3D xive2_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
- nvt_idx, true, 0);
+ nvt_idx, crowd, ignore, =
0);
}
=20
if (ring !=3D -1) {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 283a6b8fd2..41cfcab3b9 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -431,7 +431,8 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8=
_t nvt_blk,
=20
static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore,
+ uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
CPUState *cs;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 74a78da88b..2a7ce72606 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1681,10 +1681,18 @@ uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
return 1 << (ctz32(~nvp_index) + 1);
}
=20
-static uint8_t xive_get_group_level(uint32_t nvp_index)
+static uint8_t xive_get_group_level(bool crowd, bool ignore,
+ uint32_t nvp_blk, uint32_t nvp_index)
{
- /* FIXME add crowd encoding */
- return ctz32(~nvp_index) + 1;
+ uint8_t level =3D 0;
+
+ if (crowd) {
+ level =3D ((ctz32(~nvp_blk) + 1) & 0b11) << 4;
+ }
+ if (ignore) {
+ level |=3D (ctz32(~nvp_index) + 1) & 0b1111;
+ }
+ return level;
}
=20
/*
@@ -1756,7 +1764,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
*/
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, bool *precluded)
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
@@ -1787,7 +1795,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
* a new command to the presenters (the equivalent of the "assign"
* power bus command in the documented full notify sequence.
*/
- count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
+ count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ign=
ore,
priority, logic_serv, &match);
if (count < 0) {
return false;
@@ -1795,7 +1803,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
=20
/* handle CPU exception delivery */
if (count) {
- group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
+ group_level =3D xive_get_group_level(crowd, cam_ignore, nvt_blk, n=
vt_idx);
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
} else {
@@ -1920,6 +1928,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
}
=20
found =3D xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,
+ false /* crowd */,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
),
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index b6f279e6a3..1f2837104c 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -1117,13 +1117,42 @@ static bool xive2_vp_match_mask(uint32_t cam1, uint=
32_t cam2,
return (cam1 & vp_mask) =3D=3D (cam2 & vp_mask);
}
=20
+static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd)
+{
+ uint8_t size, block_mask =3D 0b1111;
+
+ /* 3 supported crowd sizes: 2, 4, 16 */
+ if (crowd) {
+ size =3D xive_get_vpgroup_size(nvt_blk);
+ if (size =3D=3D 8) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of 8n=
");
+ return block_mask;
+ }
+ block_mask =3D ~(size - 1);
+ block_mask &=3D 0b1111;
+ }
+ return block_mask;
+}
+
+static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignor=
e)
+{
+ uint32_t index_mask =3D 0xFFFFFF; /* 24 bits */
+
+ if (cam_ignore) {
+ index_mask =3D ~(xive_get_vpgroup_size(nvt_index) - 1);
+ index_mask &=3D 0xFFFFFF;
+ }
+ return index_mask;
+}
+
/*
* The thread context register words are in big-endian format.
*/
int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv)
+ bool crowd, bool cam_ignore,
+ uint32_t logic_serv)
{
uint32_t cam =3D xive2_nvp_cam_line(nvt_blk, nvt_idx);
uint32_t qw3w2 =3D xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1131,7 +1160,8 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw0w2 =3D xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
=20
- uint32_t vp_mask =3D 0xFFFFFFFF;
+ uint32_t index_mask, vp_mask;
+ uint8_t block_mask;
=20
if (format =3D=3D 0) {
/*
@@ -1139,9 +1169,9 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
* i=3D1: VP-group notification (bits ignored at the end of the
* NVT identifier)
*/
- if (cam_ignore) {
- vp_mask =3D ~(xive_get_vpgroup_size(nvt_idx) - 1);
- }
+ block_mask =3D xive2_get_vp_block_mask(nvt_blk, crowd);
+ index_mask =3D xive2_get_vp_index_mask(nvt_idx, cam_ignore);
+ vp_mask =3D xive2_nvp_cam_line(block_mask, index_mask);
=20
/* For VP-group notifications, threads with LGS=3D0 are excluded */
=20
@@ -1274,6 +1304,12 @@ static void xive2_router_end_notify(Xive2Router *xrt=
r, uint8_t end_blk,
return;
}
=20
+ if (xive2_end_is_crowd(&end) & !xive2_end_is_ignore(&end)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: invalid END, 'crowd' bit requires 'ignore' bi=
t\n");
+ return;
+ }
+
if (xive2_end_is_enqueue(&end)) {
xive2_end_enqueue(&end, end_data);
/* Enqueuing event data modifies the EQ toggle and index */
@@ -1335,7 +1371,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr=
, uint8_t end_blk,
}
=20
found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
- xive2_end_is_ignore(&end),
+ xive2_end_is_crowd(&end), xive2_end_is_ignore(&e=
nd),
priority,
xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7),
&precluded);
@@ -1372,17 +1408,24 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
} else {
- Xive2Nvgc nvg;
+ Xive2Nvgc nvgc;
uint32_t backlog;
+ bool crowd;
=20
- /* For groups, the per-priority backlog counters are in the NV=
G */
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg)=
) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVG %x/%x\n",
- nvp_blk, nvp_idx);
+ crowd =3D xive2_end_is_crowd(&end);
+
+ /*
+ * For groups and crowds, the per-priority backlog
+ * counters are stored in the NVG/NVC structures
+ */
+ if (xive2_router_get_nvgc(xrtr, crowd,
+ nvp_blk, nvp_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n",
+ crowd ? "NVC" : "NVG", nvp_blk, nvp_idx);
return;
}
=20
- if (!xive2_nvgc_is_valid(&nvg)) {
+ if (!xive2_nvgc_is_valid(&nvgc)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid=
\n",
nvp_blk, nvp_idx);
return;
@@ -1395,13 +1438,16 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
* set the LSMFB field of the TIMA of relevant threads so
* that they know an interrupt is pending.
*/
- backlog =3D xive2_nvgc_get_backlog(&nvg, priority) + 1;
- xive2_nvgc_set_backlog(&nvg, priority, backlog);
- xive2_router_write_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg);
+ backlog =3D xive2_nvgc_get_backlog(&nvgc, priority) + 1;
+ xive2_nvgc_set_backlog(&nvgc, priority, backlog);
+ xive2_router_write_nvgc(xrtr, crowd, nvp_blk, nvp_idx, &nvgc);
=20
if (precluded && backlog =3D=3D 1) {
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb);
- xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx, priority);
+ xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx,
+ xive2_end_is_crowd(&end),
+ xive2_end_is_ignore(&end),
+ priority);
=20
if (!xive2_end_is_precluded_escalation(&end)) {
/*
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6c76f65936..419f65607a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2583,7 +2583,7 @@ static void pnv_pic_print_info(InterruptStatsProvider=
*obj, GString *buf)
=20
static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv,
XiveTCTXMatch *match)
{
@@ -2597,8 +2597,8 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t for=
mat,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor=
e,
- priority, logic_serv, match);
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
=20
if (count < 0) {
return count;
@@ -2612,7 +2612,7 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t for=
mat,
=20
static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t prior=
ity,
uint32_t logic_serv,
XiveTCTXMatch *match)
{
@@ -2626,8 +2626,8 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint=
8_t format,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor=
e,
- priority, logic_serv, match);
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
=20
if (count < 0) {
return count;
@@ -2641,6 +2641,7 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint=
8_t format,
=20
static int pnv10_xive_broadcast(XiveFabric *xfb,
uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore,
uint8_t priority)
{
PnvMachineState *pnv =3D PNV_MACHINE(xfb);
@@ -2651,7 +2652,7 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
XivePresenter *xptr =3D XIVE_PRESENTER(&chip10->xive);
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
=20
- xpc->broadcast(xptr, nvt_blk, nvt_idx, priority);
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority=
);
}
return 0;
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 5c02037c56..5fdd9ad915 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4437,7 +4437,7 @@ static void spapr_pic_print_info(InterruptStatsProvid=
er *obj, GString *buf)
*/
static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
SpaprMachineState *spapr =3D SPAPR_MACHINE(xfb);
@@ -4445,7 +4445,7 @@ static int spapr_match_nvt(XiveFabric *xfb, uint8_t f=
ormat,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, cam_ig=
nore,
priority, logic_serv, match);
if (count < 0) {
return count;
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 09/14] ppc/xive2: Add support for MMIO operations on the
NVPG/NVC BAR
Date: Mon, 9 Dec 2024 18:05:19 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
Add support for the NVPG and NVC BARs. Access to the BAR pages will
cause backlog counter operations to either increment or decriment
the counter.
Also added qtests for the same.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive2.h | 9 ++
include/hw/ppc/xive2_regs.h | 3 +
tests/qtest/pnv-xive2-common.h | 1 +
hw/intc/pnv_xive2.c | 80 +++++++++++++---
hw/intc/xive2.c | 87 +++++++++++++++++
tests/qtest/pnv-xive2-nvpg_bar.c | 154 +++++++++++++++++++++++++++++++
tests/qtest/pnv-xive2-test.c | 3 +
hw/intc/trace-events | 4 +
tests/qtest/meson.build | 3 +-
9 files changed, 329 insertions(+), 15 deletions(-)
create mode 100644 tests/qtest/pnv-xive2-nvpg_bar.c
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index fc7422fea7..c07e23e1d3 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -90,6 +90,15 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint32_t logic_serv);
=20
+uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset);
+
+uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
+ bool crowd,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset, uint16_t val);
+
/*
* XIVE2 END ESBs (POWER10)
*/
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index e88d6eab1e..9bcf7a8a6f 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -233,4 +233,7 @@ typedef struct Xive2Nvgc {
void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx,
GString *buf);
=20
+#define NVx_BACKLOG_OP PPC_BITMASK(52, 53)
+#define NVx_BACKLOG_PRIO PPC_BITMASK(57, 59)
+
#endif /* PPC_XIVE2_REGS_H */
diff --git a/tests/qtest/pnv-xive2-common.h b/tests/qtest/pnv-xive2-common.h
index 9ae34771aa..2077c05ebc 100644
--- a/tests/qtest/pnv-xive2-common.h
+++ b/tests/qtest/pnv-xive2-common.h
@@ -107,5 +107,6 @@ extern void set_end(QTestState *qts, uint32_t index, ui=
nt32_t nvp_index,
=20
=20
void test_flush_sync_inject(QTestState *qts);
+void test_nvpg_bar(QTestState *qts);
=20
#endif /* TEST_PNV_XIVE2_COMMON_H */
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 41b727d1fb..54abfe3947 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -2202,21 +2202,40 @@ static const MemoryRegionOps pnv_xive2_tm_ops =3D {
},
};
=20
-static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset,
+static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset);
- return -1;
+ if (size !=3D 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc load size %d\n",
+ size);
+ return -1;
+ }
+
+ return xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, 1);
}
=20
-static void pnv_xive2_nvc_write(void *opaque, hwaddr offset,
+static void pnv_xive2_nvc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvc_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset);
+ if (size !=3D 1) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc write size %d\n",
+ size);
+ return;
+ }
+
+ (void)xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, val);
}
=20
static const MemoryRegionOps pnv_xive2_nvc_ops =3D {
@@ -2224,30 +2243,63 @@ static const MemoryRegionOps pnv_xive2_nvc_ops =3D {
.write =3D pnv_xive2_nvc_write,
.endianness =3D DEVICE_BIG_ENDIAN,
.valid =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
.impl =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
};
=20
-static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset,
+static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr addr,
unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint32_t index =3D page >> 1;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset);
- return -1;
+ if (size !=3D 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg load size %d\n",
+ size);
+ return -1;
+ }
+
+ if (page % 2) {
+ /* odd page - NVG */
+ return xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op=
, 1);
+ } else {
+ /* even page - NVP */
+ return xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
+ }
}
=20
-static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset,
+static void pnv_xive2_nvpg_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvXive2 *xive =3D PNV_XIVE2(opaque);
+ XivePresenter *xptr =3D XIVE_PRESENTER(xive);
+ uint32_t page =3D addr >> xive->nvpg_shift;
+ uint16_t op =3D addr & 0xFFF;
+ uint32_t index =3D page >> 1;
+ uint8_t blk =3D pnv_xive2_block_id(xive);
=20
- xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset);
+ if (size !=3D 1) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg write size %d\n=
",
+ size);
+ return;
+ }
+
+ if (page % 2) {
+ /* odd page - NVG */
+ (void)xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op,=
val);
+ } else {
+ /* even page - NVP */
+ (void)xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
+ }
}
=20
static const MemoryRegionOps pnv_xive2_nvpg_ops =3D {
@@ -2255,11 +2307,11 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops =3D=
{
.write =3D pnv_xive2_nvpg_write,
.endianness =3D DEVICE_BIG_ENDIAN,
.valid =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
.impl =3D {
- .min_access_size =3D 8,
+ .min_access_size =3D 1,
.max_access_size =3D 8,
},
};
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 47f7a099de..f4621bdd02 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -87,6 +87,93 @@ static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint=
8_t priority,
}
}
=20
+uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
+ bool crowd,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset, uint16_t val)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint8_t priority =3D GETFIELD(NVx_BACKLOG_PRIO, offset);
+ uint8_t op =3D GETFIELD(NVx_BACKLOG_OP, offset);
+ Xive2Nvgc nvgc;
+ uint32_t count, old_count;
+
+ if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n",
+ crowd ? "NVC" : "NVG", blk, idx);
+ return -1;
+ }
+ if (!xive2_nvgc_is_valid(&nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, i=
dx);
+ return -1;
+ }
+
+ old_count =3D xive2_nvgc_get_backlog(&nvgc, priority);
+ count =3D old_count;
+ /*
+ * op:
+ * 0b00 =3D> increment
+ * 0b01 =3D> decrement
+ * 0b1- =3D> read
+ */
+ if (op =3D=3D 0b00 || op =3D=3D 0b01) {
+ if (op =3D=3D 0b00) {
+ count +=3D val;
+ } else {
+ if (count > val) {
+ count -=3D val;
+ } else {
+ count =3D 0;
+ }
+ }
+ xive2_nvgc_set_backlog(&nvgc, priority, count);
+ xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc);
+ }
+ trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count);
+ return old_count;
+}
+
+uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
+ uint8_t blk, uint32_t idx,
+ uint16_t offset)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
+ uint8_t priority =3D GETFIELD(NVx_BACKLOG_PRIO, offset);
+ uint8_t op =3D GETFIELD(NVx_BACKLOG_OP, offset);
+ Xive2Nvp nvp;
+ uint8_t ipb, old_ipb, rc;
+
+ if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx);
+ return -1;
+ }
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, i=
dx);
+ return -1;
+ }
+
+ old_ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2);
+ ipb =3D old_ipb;
+ /*
+ * op:
+ * 0b00 =3D> set priority bit
+ * 0b01 =3D> reset priority bit
+ * 0b1- =3D> read
+ */
+ if (op =3D=3D 0b00 || op =3D=3D 0b01) {
+ if (op =3D=3D 0b00) {
+ ipb |=3D xive_priority_to_ipb(priority);
+ } else {
+ ipb &=3D ~xive_priority_to_ipb(priority);
+ }
+ nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
+ xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2);
+ }
+ rc =3D !!(old_ipb & xive_priority_to_ipb(priority));
+ trace_xive_nvp_backlog_op(blk, idx, op, priority, rc);
+ return rc;
+}
+
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
{
if (!xive2_eas_is_valid(eas)) {
diff --git a/tests/qtest/pnv-xive2-nvpg_bar.c b/tests/qtest/pnv-xive2-nvpg_=
bar.c
new file mode 100644
index 0000000000..10d4962d1e
--- /dev/null
+++ b/tests/qtest/pnv-xive2-nvpg_bar.c
@@ -0,0 +1,154 @@
+/*
+ * QTest testcase for PowerNV 10 interrupt controller (xive2)
+ * - Test NVPG BAR MMIO operations
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+#include "pnv-xive2-common.h"
+
+#define NVPG_BACKLOG_OP_SHIFT 10
+#define NVPG_BACKLOG_PRIO_SHIFT 4
+
+#define XIVE_PRIORITY_MAX 7
+
+enum NVx {
+ NVP,
+ NVG,
+ NVC
+};
+
+typedef enum {
+ INCR_STORE =3D 0b100,
+ INCR_LOAD =3D 0b000,
+ DECR_STORE =3D 0b101,
+ DECR_LOAD =3D 0b001,
+ READ_x =3D 0b010,
+ READ_y =3D 0b011,
+} backlog_op;
+
+static uint32_t nvpg_backlog_op(QTestState *qts, backlog_op op,
+ enum NVx type, uint64_t index,
+ uint8_t priority, uint8_t delta)
+{
+ uint64_t addr, offset;
+ uint32_t count =3D 0;
+
+ switch (type) {
+ case NVP:
+ addr =3D XIVE_NVPG_ADDR + (index << (XIVE_PAGE_SHIFT + 1));
+ break;
+ case NVG:
+ addr =3D XIVE_NVPG_ADDR + (index << (XIVE_PAGE_SHIFT + 1)) +
+ (1 << XIVE_PAGE_SHIFT);
+ break;
+ case NVC:
+ addr =3D XIVE_NVC_ADDR + (index << XIVE_PAGE_SHIFT);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ offset =3D (op & 0b11) << NVPG_BACKLOG_OP_SHIFT;
+ offset |=3D priority << NVPG_BACKLOG_PRIO_SHIFT;
+ if (op >> 2) {
+ qtest_writeb(qts, addr + offset, delta);
+ } else {
+ count =3D qtest_readw(qts, addr + offset);
+ }
+ return count;
+}
+
+void test_nvpg_bar(QTestState *qts)
+{
+ uint32_t nvp_target =3D 0x11;
+ uint32_t group_target =3D 0x17; /* size 16 */
+ uint32_t vp_irq =3D 33, group_irq =3D 47;
+ uint32_t vp_end =3D 3, group_end =3D 97;
+ uint32_t vp_irq_data =3D 0x33333333;
+ uint32_t group_irq_data =3D 0x66666666;
+ uint8_t vp_priority =3D 0, group_priority =3D 5;
+ uint32_t vp_count[XIVE_PRIORITY_MAX + 1] =3D { 0 };
+ uint32_t group_count[XIVE_PRIORITY_MAX + 1] =3D { 0 };
+ uint32_t count, delta;
+ uint8_t i;
+
+ printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
+ printf("# Testing NVPG BAR operations\n");
+
+ set_nvg(qts, group_target, 0);
+ set_nvp(qts, nvp_target, 0x04);
+ set_nvp(qts, group_target, 0x04);
+
+ /*
+ * Setup: trigger a VP-specific interrupt and a group interrupt
+ * so that the backlog counters are initialized to something else
+ * than 0 for at least one priority level
+ */
+ set_eas(qts, vp_irq, vp_end, vp_irq_data);
+ set_end(qts, vp_end, nvp_target, vp_priority, false /* group */);
+
+ set_eas(qts, group_irq, group_end, group_irq_data);
+ set_end(qts, group_end, group_target, group_priority, true /* group */=
);
+
+ get_esb(qts, vp_irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, vp_irq, XIVE_TRIGGER_PAGE, 0, 0);
+ vp_count[vp_priority]++;
+
+ get_esb(qts, group_irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, group_irq, XIVE_TRIGGER_PAGE, 0, 0);
+ group_count[group_priority]++;
+
+ /* check the initial counters */
+ for (i =3D 0; i <=3D XIVE_PRIORITY_MAX; i++) {
+ count =3D nvpg_backlog_op(qts, READ_x, NVP, nvp_target, i, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[i]);
+
+ count =3D nvpg_backlog_op(qts, READ_y, NVG, group_target, i, 0);
+ g_assert_cmpuint(count, =3D=3D, group_count[i]);
+ }
+
+ /* do a few ops on the VP. Counter can only be 0 and 1 */
+ vp_priority =3D 2;
+ delta =3D 7;
+ nvpg_backlog_op(qts, INCR_STORE, NVP, nvp_target, vp_priority, delta);
+ vp_count[vp_priority] =3D 1;
+ count =3D nvpg_backlog_op(qts, INCR_LOAD, NVP, nvp_target, vp_priority=
, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+ count =3D nvpg_backlog_op(qts, READ_y, NVP, nvp_target, vp_priority, 0=
);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+
+ count =3D nvpg_backlog_op(qts, DECR_LOAD, NVP, nvp_target, vp_priority=
, 0);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+ vp_count[vp_priority] =3D 0;
+ nvpg_backlog_op(qts, DECR_STORE, NVP, nvp_target, vp_priority, delta);
+ count =3D nvpg_backlog_op(qts, READ_x, NVP, nvp_target, vp_priority, 0=
);
+ g_assert_cmpuint(count, =3D=3D, vp_count[vp_priority]);
+
+ /* do a few ops on the group */
+ group_priority =3D 2;
+ delta =3D 9;
+ /* can't go negative */
+ nvpg_backlog_op(qts, DECR_STORE, NVG, group_target, group_priority, de=
lta);
+ count =3D nvpg_backlog_op(qts, READ_y, NVG, group_target, group_priori=
ty, 0);
+ g_assert_cmpuint(count, =3D=3D, 0);
+ nvpg_backlog_op(qts, INCR_STORE, NVG, group_target, group_priority, de=
lta);
+ group_count[group_priority] +=3D delta;
+ count =3D nvpg_backlog_op(qts, INCR_LOAD, NVG, group_target,
+ group_priority, delta);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+ group_count[group_priority]++;
+
+ count =3D nvpg_backlog_op(qts, DECR_LOAD, NVG, group_target,
+ group_priority, delta);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+ group_count[group_priority]--;
+ count =3D nvpg_backlog_op(qts, READ_x, NVG, group_target, group_priori=
ty, 0);
+ g_assert_cmpuint(count, =3D=3D, group_count[group_priority]);
+}
+
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index a4d06550ee..a0e9f19313 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -493,6 +493,9 @@ static void test_xive(void)
reset_state(qts);
test_flush_sync_inject(qts);
=20
+ reset_state(qts);
+ test_nvpg_bar(qts);
+
qtest_quit(qts);
}
=20
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 7435728c51..7f362c38b0 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -285,6 +285,10 @@ xive_tctx_tm_read(uint32_t index, uint64_t offset, uns=
igned int size, uint64_t v
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uin=
t8_t group_level) "found NVT 0x%x/0x%x ring=3D0x%x group_level=3D%d"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "EN=
D 0x%x/0x%x @0x%"PRIx64
=20
+# xive2.c
+xive_nvp_backlog_op(uint8_t blk, uint32_t idx, uint8_t op, uint8_t priorit=
y, uint8_t rc) "NVP 0x%x/0x%x operation=3D%d priority=3D%d rc=3D%d"
+xive_nvgc_backlog_op(bool c, uint8_t blk, uint32_t idx, uint8_t op, uint8_=
t priority, uint32_t rc) "NVGC crowd=3D%d 0x%x/0x%x operation=3D%d priority=
=3D%d rc=3D%d"
+
# pnv_xive.c
pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=3D0x=
%"PRIx64
=20
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index bd41c9da5f..f7da3df24b 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -348,7 +348,8 @@ qtests =3D {
'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'],
'migration-test': migration_files,
'pxe-test': files('boot-sector.c'),
- 'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c'),
+ 'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c',
+ 'pnv-xive2-nvpg_bar.c'),
'qos-test': [chardev, io, qos_test_ss.apply({}).sources()],
'tpm-crb-swtpm-test': [io, tpmemu_files],
'tpm-crb-test': [io, tpmemu_files],
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 10/14] ppc/xive2: Check crowd backlog when scanning group
backlog
Date: Mon, 9 Dec 2024 18:05:21 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When processing a backlog scan for group interrupts, also take
into account crowd interrupts.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive2_regs.h | 4 ++
hw/intc/xive2.c | 82 +++++++++++++++++++++++++------------
2 files changed, 60 insertions(+), 26 deletions(-)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 66a419441c..89236b9aaf 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -237,4 +237,8 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_=
t nvgc_idx,
#define NVx_BACKLOG_OP PPC_BITMASK(52, 53)
#define NVx_BACKLOG_PRIO PPC_BITMASK(57, 59)
=20
+/* split the 6-bit crowd/group level */
+#define NVx_CROWD_LVL(level) ((level >> 4) & 0b11)
+#define NVx_GROUP_LVL(level) (level & 0b1111)
+
#endif /* PPC_XIVE2_REGS_H */
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 1f2837104c..41d689eaab 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -367,6 +367,35 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t =
data)
end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
}
=20
+static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx,
+ uint8_t next_level)
+{
+ uint32_t mask, next_idx;
+ uint8_t next_blk;
+
+ /*
+ * Adjust the block and index of a VP for the next group/crowd
+ * size (PGofFirst/PGofNext field in the NVP and NVGC structures).
+ *
+ * The 6-bit group level is split into a 2-bit crowd and 4-bit
+ * group levels. Encoding is similar. However, we don't support
+ * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd
+ * size of 16.
+ */
+ next_blk =3D NVx_CROWD_LVL(next_level);
+ if (next_blk =3D=3D 3) {
+ next_blk =3D 4;
+ }
+ mask =3D (1 << next_blk) - 1;
+ *nvgc_blk &=3D ~mask;
+ *nvgc_blk |=3D mask >> 1;
+
+ next_idx =3D NVx_GROUP_LVL(next_level);
+ mask =3D (1 << next_idx) - 1;
+ *nvgc_idx &=3D ~mask;
+ *nvgc_idx |=3D mask >> 1;
+}
+
/*
* Scan the group chain and return the highest priority and group
* level of pending group interrupts.
@@ -377,29 +406,28 @@ static uint8_t xive2_presenter_backlog_check(XivePres=
enter *xptr,
uint8_t *out_level)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
- uint32_t nvgc_idx, mask;
+ uint32_t nvgc_idx;
uint32_t current_level, count;
- uint8_t prio;
+ uint8_t nvgc_blk, prio;
Xive2Nvgc nvgc;
=20
for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) {
- current_level =3D first_group & 0xF;
+ current_level =3D first_group & 0x3F;
+ nvgc_blk =3D nvp_blk;
+ nvgc_idx =3D nvp_idx;
=20
while (current_level) {
- mask =3D (1 << current_level) - 1;
- nvgc_idx =3D nvp_idx & ~mask;
- nvgc_idx |=3D mask >> 1;
- qemu_log("fxb %s checking backlog for prio %d group idx %x\n",
- __func__, prio, nvgc_idx);
-
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvg=
c)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level);
+
+ if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level),
+ nvgc_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return 0xFF;
}
if (!xive2_nvgc_is_valid(&nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n=
",
+ nvgc_blk, nvgc_idx);
return 0xFF;
}
=20
@@ -408,7 +436,7 @@ static uint8_t xive2_presenter_backlog_check(XivePresen=
ter *xptr,
*out_level =3D current_level;
return prio;
}
- current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0xF;
+ current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0x3F;
}
}
return 0xFF;
@@ -420,22 +448,23 @@ static void xive2_presenter_backlog_decr(XivePresente=
r *xptr,
uint8_t group_level)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
- uint32_t nvgc_idx, mask, count;
+ uint32_t nvgc_idx, count;
+ uint8_t nvgc_blk;
Xive2Nvgc nvgc;
=20
- group_level &=3D 0xF;
- mask =3D (1 << group_level) - 1;
- nvgc_idx =3D nvp_idx & ~mask;
- nvgc_idx |=3D mask >> 1;
+ nvgc_blk =3D nvp_blk;
+ nvgc_idx =3D nvp_idx;
+ xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level);
=20
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level),
+ nvgc_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return;
}
if (!xive2_nvgc_is_valid(&nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return;
}
count =3D xive2_nvgc_get_backlog(&nvgc, group_prio);
@@ -443,7 +472,8 @@ static void xive2_presenter_backlog_decr(XivePresenter =
*xptr,
return;
}
xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1);
- xive2_router_write_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc);
+ xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level),
+ nvgc_blk, nvgc_idx, &nvgc);
}
=20
/*
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
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david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 10/14] ppc/xive2: Support crowd-matching when looking for
target
Date: Mon, 9 Dec 2024 18:05:22 -0600
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RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,
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From: Frederic Barrat <fbarrat@linux.ibm.com>
XIVE crowd sizes are encoded into a 2-bit field as follows:
0: 0b00
2: 0b01
4: 0b10
16: 0b11
A crowd size of 8 is not supported.
If an END is defined with the 'crowd' bit set, then a target can be
running on different blocks. It means that some bits from the block
VP are masked when looking for a match. It is similar to groups, but
on the block instead of the VP index.
Most of the changes are due to passing the extra argument 'crowd' all
the way to the function checking for matches.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive.h | 10 +++---
include/hw/ppc/xive2.h | 3 +-
hw/intc/pnv_xive.c | 10 +++---
hw/intc/pnv_xive2.c | 12 +++----
hw/intc/spapr_xive.c | 8 ++---
hw/intc/xive.c | 40 ++++++++++++++++++----
hw/intc/xive2.c | 78 +++++++++++++++++++++++++++++++++---------
hw/ppc/pnv.c | 15 ++++----
hw/ppc/spapr.c | 7 ++--
9 files changed, 131 insertions(+), 52 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index f443a39cf1..8317fde0db 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -438,13 +438,13 @@ struct XivePresenterClass {
InterfaceClass parent;
int (*match_nvt)(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
bool (*in_kernel)(const XivePresenter *xptr);
uint32_t (*get_config)(XivePresenter *xptr);
int (*broadcast)(XivePresenter *xptr,
uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority);
+ bool crowd, bool cam_ignore, uint8_t priority);
};
=20
int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
@@ -453,7 +453,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xive=
TCTX *tctx,
bool cam_ignore, uint32_t logic_serv);
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, bool *precluded);
=20
uint32_t xive_get_vpgroup_size(uint32_t nvp_index);
@@ -473,10 +473,10 @@ struct XiveFabricClass {
InterfaceClass parent;
int (*match_nvt)(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match);
int (*broadcast)(XiveFabric *xfb, uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority);
+ bool crowd, bool cam_ignore, uint8_t priority);
};
=20
/*
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index c07e23e1d3..8cdf819174 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -88,7 +88,8 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t lisn,=
bool pq_checked);
int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv);
+ bool crowd, bool cam_ignore,
+ uint32_t logic_serv);
=20
uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
uint8_t blk, uint32_t idx,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 5bacbce6a4..d4796ab5a6 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1,10 +1,9 @@
/*
* QEMU PowerPC XIVE interrupt controller model
*
- * Copyright (c) 2017-2019, IBM Corporation.
+ * Copyright (c) 2017-2024, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#include "qemu/osdep.h"
@@ -473,7 +472,7 @@ static bool pnv_xive_is_cpu_enabled(PnvXive *xive, Powe=
rPCCPU *cpu)
=20
static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priorit=
y,
uint32_t logic_serv, XiveTCTXMatch *match)
{
PnvXive *xive =3D PNV_XIVE(xptr);
@@ -500,7 +499,8 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint=
8_t format,
* Check the thread context CAM lines and record matches.
*/
ring =3D xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
- nvt_idx, cam_ignore, logic_se=
rv);
+ nvt_idx, cam_ignore,
+ logic_serv);
/*
* Save the context and follow on to catch duplicates, that we
* don't support yet.
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 54abfe3947..91f3514f93 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -624,7 +624,7 @@ static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, Po=
werPCCPU *cpu)
=20
static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priori=
ty,
uint32_t logic_serv, XiveTCTXMatch *match)
{
PnvXive2 *xive =3D PNV_XIVE2(xptr);
@@ -655,8 +655,8 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uin=
t8_t format,
logic_serv);
} else {
ring =3D xive2_presenter_tctx_match(xptr, tctx, format, nv=
t_blk,
- nvt_idx, cam_ignore,
- logic_serv);
+ nvt_idx, crowd, cam_igno=
re,
+ logic_serv);
}
=20
if (ring !=3D -1) {
@@ -707,7 +707,7 @@ static uint32_t pnv_xive2_presenter_get_config(XivePres=
enter *xptr)
=20
static int pnv_xive2_broadcast(XivePresenter *xptr,
uint8_t nvt_blk, uint32_t nvt_idx,
- uint8_t priority)
+ bool crowd, bool ignore, uint8_t priority)
{
PnvXive2 *xive =3D PNV_XIVE2(xptr);
PnvChip *chip =3D xive->chip;
@@ -732,10 +732,10 @@ static int pnv_xive2_broadcast(XivePresenter *xptr,
=20
if (gen1_tima_os) {
ring =3D xive_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
- nvt_idx, true, 0);
+ nvt_idx, ignore, 0);
} else {
ring =3D xive2_presenter_tctx_match(xptr, tctx, 0, nvt_blk,
- nvt_idx, true, 0);
+ nvt_idx, crowd, ignore, =
0);
}
=20
if (ring !=3D -1) {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 283a6b8fd2..0477fdd594 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -1,10 +1,9 @@
/*
* QEMU PowerPC sPAPR XIVE interrupt controller model
*
- * Copyright (c) 2017-2018, IBM Corporation.
+ * Copyright (c) 2017-2024, IBM Corporation.
*
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
=20
#include "qemu/osdep.h"
@@ -431,7 +430,8 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8=
_t nvt_blk,
=20
static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore,
+ uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
CPUState *cs;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 308de5aefc..97d1c42bb2 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1667,10 +1667,37 @@ uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
return 1 << (ctz32(~nvp_index) + 1);
}
=20
-static uint8_t xive_get_group_level(uint32_t nvp_index)
+static uint8_t xive_get_group_level(bool crowd, bool ignore,
+ uint32_t nvp_blk, uint32_t nvp_index)
{
- /* FIXME add crowd encoding */
- return ctz32(~nvp_index) + 1;
+ uint8_t level =3D 0;
+
+ if (crowd) {
+ /* crowd level is bit position of first 0 from the right in nvp_bl=
k */
+ level =3D ctz32(~nvp_blk) + 1;
+
+ /*
+ * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not support=
ed.
+ * HW will encode level 4 as the value 3. See xive2_pgofnext().
+ */
+ switch (level) {
+ case 1:
+ case 2:
+ break;
+ case 4:
+ level =3D 3;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Crowd level bits reside in upper 2 bits of the 6 bit group leve=
l */
+ level <<=3D 4;
+ }
+ if (ignore) {
+ level |=3D (ctz32(~nvp_index) + 1) & 0b1111;
+ }
+ return level;
}
=20
/*
@@ -1742,7 +1769,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi=
veTCTX *tctx,
*/
bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, bool *precluded)
{
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xfb);
@@ -1773,7 +1800,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
* a new command to the presenters (the equivalent of the "assign"
* power bus command in the documented full notify sequence.
*/
- count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
+ count =3D xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ign=
ore,
priority, logic_serv, &match);
if (count < 0) {
return false;
@@ -1781,7 +1808,7 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t f=
ormat,
=20
/* handle CPU exception delivery */
if (count) {
- group_level =3D cam_ignore ? xive_get_group_level(nvt_idx) : 0;
+ group_level =3D xive_get_group_level(crowd, cam_ignore, nvt_blk, n=
vt_idx);
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring, group_le=
vel);
xive_tctx_pipr_update(match.tctx, match.ring, priority, group_leve=
l);
} else {
@@ -1906,6 +1933,7 @@ void xive_router_end_notify(XiveRouter *xrtr, XiveEAS=
*eas)
}
=20
found =3D xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,
+ false /* crowd */,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7=
),
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index f4621bdd02..20d63e8f6e 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -1120,13 +1120,42 @@ static bool xive2_vp_match_mask(uint32_t cam1, uint=
32_t cam2,
return (cam1 & vp_mask) =3D=3D (cam2 & vp_mask);
}
=20
+static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd)
+{
+ uint8_t size, block_mask =3D 0b1111;
+
+ /* 3 supported crowd sizes: 2, 4, 16 */
+ if (crowd) {
+ size =3D xive_get_vpgroup_size(nvt_blk);
+ if (size =3D=3D 8) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of 8n=
");
+ return block_mask;
+ }
+ block_mask =3D ~(size - 1);
+ block_mask &=3D 0b1111;
+ }
+ return block_mask;
+}
+
+static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignor=
e)
+{
+ uint32_t index_mask =3D 0xFFFFFF; /* 24 bits */
+
+ if (cam_ignore) {
+ index_mask =3D ~(xive_get_vpgroup_size(nvt_index) - 1);
+ index_mask &=3D 0xFFFFFF;
+ }
+ return index_mask;
+}
+
/*
* The thread context register words are in big-endian format.
*/
int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv)
+ bool crowd, bool cam_ignore,
+ uint32_t logic_serv)
{
uint32_t cam =3D xive2_nvp_cam_line(nvt_blk, nvt_idx);
uint32_t qw3w2 =3D xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1134,7 +1163,8 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
uint32_t qw1w2 =3D xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw0w2 =3D xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
=20
- uint32_t vp_mask =3D 0xFFFFFFFF;
+ uint32_t index_mask, vp_mask;
+ uint8_t block_mask;
=20
if (format =3D=3D 0) {
/*
@@ -1142,9 +1172,9 @@ int xive2_presenter_tctx_match(XivePresenter *xptr, X=
iveTCTX *tctx,
* i=3D1: VP-group notification (bits ignored at the end of the
* NVT identifier)
*/
- if (cam_ignore) {
- vp_mask =3D ~(xive_get_vpgroup_size(nvt_idx) - 1);
- }
+ block_mask =3D xive2_get_vp_block_mask(nvt_blk, crowd);
+ index_mask =3D xive2_get_vp_index_mask(nvt_idx, cam_ignore);
+ vp_mask =3D xive2_nvp_cam_line(block_mask, index_mask);
=20
/* For VP-group notifications, threads with LGS=3D0 are excluded */
=20
@@ -1277,6 +1307,12 @@ static void xive2_router_end_notify(Xive2Router *xrt=
r, uint8_t end_blk,
return;
}
=20
+ if (xive2_end_is_crowd(&end) & !xive2_end_is_ignore(&end)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: invalid END, 'crowd' bit requires 'ignore' bi=
t\n");
+ return;
+ }
+
if (xive2_end_is_enqueue(&end)) {
xive2_end_enqueue(&end, end_data);
/* Enqueuing event data modifies the EQ toggle and index */
@@ -1338,7 +1374,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr=
, uint8_t end_blk,
}
=20
found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
- xive2_end_is_ignore(&end),
+ xive2_end_is_crowd(&end), xive2_end_is_ignore(&e=
nd),
priority,
xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7),
&precluded);
@@ -1375,17 +1411,24 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
} else {
- Xive2Nvgc nvg;
+ Xive2Nvgc nvgc;
uint32_t backlog;
+ bool crowd;
=20
- /* For groups, the per-priority backlog counters are in the NV=
G */
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg)=
) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVG %x/%x\n",
- nvp_blk, nvp_idx);
+ crowd =3D xive2_end_is_crowd(&end);
+
+ /*
+ * For groups and crowds, the per-priority backlog
+ * counters are stored in the NVG/NVC structures
+ */
+ if (xive2_router_get_nvgc(xrtr, crowd,
+ nvp_blk, nvp_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n",
+ crowd ? "NVC" : "NVG", nvp_blk, nvp_idx);
return;
}
=20
- if (!xive2_nvgc_is_valid(&nvg)) {
+ if (!xive2_nvgc_is_valid(&nvgc)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid=
\n",
nvp_blk, nvp_idx);
return;
@@ -1398,13 +1441,16 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
* set the LSMFB field of the TIMA of relevant threads so
* that they know an interrupt is pending.
*/
- backlog =3D xive2_nvgc_get_backlog(&nvg, priority) + 1;
- xive2_nvgc_set_backlog(&nvg, priority, backlog);
- xive2_router_write_nvgc(xrtr, false, nvp_blk, nvp_idx, &nvg);
+ backlog =3D xive2_nvgc_get_backlog(&nvgc, priority) + 1;
+ xive2_nvgc_set_backlog(&nvgc, priority, backlog);
+ xive2_router_write_nvgc(xrtr, crowd, nvp_blk, nvp_idx, &nvgc);
=20
if (precluded && backlog =3D=3D 1) {
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb);
- xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx, priority);
+ xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx,
+ xive2_end_is_crowd(&end),
+ xive2_end_is_ignore(&end),
+ priority);
=20
if (!xive2_end_is_precluded_escalation(&end)) {
/*
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 7c11143749..6681648ed6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2585,7 +2585,7 @@ static void pnv_pic_print_info(InterruptStatsProvider=
*obj, GString *buf)
=20
static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv,
XiveTCTXMatch *match)
{
@@ -2599,8 +2599,8 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t for=
mat,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor=
e,
- priority, logic_serv, match);
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
=20
if (count < 0) {
return count;
@@ -2614,7 +2614,7 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t for=
mat,
=20
static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t prior=
ity,
uint32_t logic_serv,
XiveTCTXMatch *match)
{
@@ -2628,8 +2628,8 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint=
8_t format,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignor=
e,
- priority, logic_serv, match);
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
=20
if (count < 0) {
return count;
@@ -2643,6 +2643,7 @@ static int pnv10_xive_match_nvt(XiveFabric *xfb, uint=
8_t format,
=20
static int pnv10_xive_broadcast(XiveFabric *xfb,
uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore,
uint8_t priority)
{
PnvMachineState *pnv =3D PNV_MACHINE(xfb);
@@ -2653,7 +2654,7 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
XivePresenter *xptr =3D XIVE_PRESENTER(&chip10->xive);
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
=20
- xpc->broadcast(xptr, nvt_blk, nvt_idx, priority);
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority=
);
}
return 0;
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0d4efaa0c0..7a922ef309 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4,6 +4,9 @@
* Copyright (c) 2004-2007 Fabrice Bellard
* Copyright (c) 2007 Jocelyn Mayer
* Copyright (c) 2010 David Gibson, IBM Corporation.
+ * Copyright (c) 2010-2024, IBM Corporation..
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
*
* Permission is hereby granted, free of charge, to any person obtaining a=
copy
* of this software and associated documentation files (the "Software"), t=
o deal
@@ -4437,7 +4440,7 @@ static void spapr_pic_print_info(InterruptStatsProvid=
er *obj, GString *buf)
*/
static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
+ bool crowd, bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
SpaprMachineState *spapr =3D SPAPR_MACHINE(xfb);
@@ -4445,7 +4448,7 @@ static int spapr_match_nvt(XiveFabric *xfb, uint8_t f=
ormat,
XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr);
int count;
=20
- count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ count =3D xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, cam_ig=
nore,
priority, logic_serv, match);
if (count < 0) {
return count;
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 11/14] pnv/xive: Only support crowd size of 0, 2, 4 and 16
Date: Mon, 9 Dec 2024 18:05:23 -0600
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From: Glenn Miles <milesg@linux.vnet.ibm.com>
XIVE crowd sizes are encoded into a 2-bit field as follows:
0: 0b00
2: 0b01
4: 0b10
16: 0b11
A crowd size of 8 is not supported.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
hw/intc/xive.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 2a7ce72606..df77098dd7 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1687,7 +1687,26 @@ static uint8_t xive_get_group_level(bool crowd, bool=
ignore,
uint8_t level =3D 0;
=20
if (crowd) {
- level =3D ((ctz32(~nvp_blk) + 1) & 0b11) << 4;
+ /* crowd level is bit position of first 0 from the right in nvp_bl=
k */
+ level =3D ctz32(~nvp_blk) + 1;
+
+ /*
+ * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not support=
ed.
+ * HW will encode level 4 as the value 3. See xive2_pgofnext().
+ */
+ switch (level) {
+ case 1:
+ case 2:
+ break;
+ case 4:
+ level =3D 3;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Crowd level bits reside in upper 2 bits of the 6 bit group leve=
l */
+ level <<=3D 4;
}
if (ignore) {
level |=3D (ctz32(~nvp_index) + 1) & 0b1111;
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 11/14] ppc/xive2: Check crowd backlog when scanning group
backlog
Date: Mon, 9 Dec 2024 18:05:24 -0600
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From: Frederic Barrat <fbarrat@linux.ibm.com>
When processing a backlog scan for group interrupts, also take
into account crowd interrupts.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
include/hw/ppc/xive2_regs.h | 4 ++
hw/intc/xive2.c | 82 +++++++++++++++++++++++++------------
2 files changed, 60 insertions(+), 26 deletions(-)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 9bcf7a8a6f..b11395c563 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -236,4 +236,8 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_=
t nvgc_idx,
#define NVx_BACKLOG_OP PPC_BITMASK(52, 53)
#define NVx_BACKLOG_PRIO PPC_BITMASK(57, 59)
=20
+/* split the 6-bit crowd/group level */
+#define NVx_CROWD_LVL(level) ((level >> 4) & 0b11)
+#define NVx_GROUP_LVL(level) (level & 0b1111)
+
#endif /* PPC_XIVE2_REGS_H */
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 20d63e8f6e..c29d8e4831 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -366,6 +366,35 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t =
data)
end->w1 =3D xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
}
=20
+static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx,
+ uint8_t next_level)
+{
+ uint32_t mask, next_idx;
+ uint8_t next_blk;
+
+ /*
+ * Adjust the block and index of a VP for the next group/crowd
+ * size (PGofFirst/PGofNext field in the NVP and NVGC structures).
+ *
+ * The 6-bit group level is split into a 2-bit crowd and 4-bit
+ * group levels. Encoding is similar. However, we don't support
+ * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd
+ * size of 16.
+ */
+ next_blk =3D NVx_CROWD_LVL(next_level);
+ if (next_blk =3D=3D 3) {
+ next_blk =3D 4;
+ }
+ mask =3D (1 << next_blk) - 1;
+ *nvgc_blk &=3D ~mask;
+ *nvgc_blk |=3D mask >> 1;
+
+ next_idx =3D NVx_GROUP_LVL(next_level);
+ mask =3D (1 << next_idx) - 1;
+ *nvgc_idx &=3D ~mask;
+ *nvgc_idx |=3D mask >> 1;
+}
+
/*
* Scan the group chain and return the highest priority and group
* level of pending group interrupts.
@@ -376,29 +405,28 @@ static uint8_t xive2_presenter_backlog_scan(XivePrese=
nter *xptr,
uint8_t *out_level)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
- uint32_t nvgc_idx, mask;
+ uint32_t nvgc_idx;
uint32_t current_level, count;
- uint8_t prio;
+ uint8_t nvgc_blk, prio;
Xive2Nvgc nvgc;
=20
for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) {
- current_level =3D first_group & 0xF;
+ current_level =3D first_group & 0x3F;
+ nvgc_blk =3D nvp_blk;
+ nvgc_idx =3D nvp_idx;
=20
while (current_level) {
- mask =3D (1 << current_level) - 1;
- nvgc_idx =3D nvp_idx & ~mask;
- nvgc_idx |=3D mask >> 1;
- qemu_log("fxb %s checking backlog for prio %d group idx %x\n",
- __func__, prio, nvgc_idx);
-
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvg=
c)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level);
+
+ if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level),
+ nvgc_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return 0xFF;
}
if (!xive2_nvgc_is_valid(&nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n=
",
+ nvgc_blk, nvgc_idx);
return 0xFF;
}
=20
@@ -407,7 +435,7 @@ static uint8_t xive2_presenter_backlog_scan(XivePresent=
er *xptr,
*out_level =3D current_level;
return prio;
}
- current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0xF;
+ current_level =3D xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) =
& 0x3F;
}
}
return 0xFF;
@@ -419,22 +447,23 @@ static void xive2_presenter_backlog_decr(XivePresente=
r *xptr,
uint8_t group_level)
{
Xive2Router *xrtr =3D XIVE2_ROUTER(xptr);
- uint32_t nvgc_idx, mask, count;
+ uint32_t nvgc_idx, count;
+ uint8_t nvgc_blk;
Xive2Nvgc nvgc;
=20
- group_level &=3D 0xF;
- mask =3D (1 << group_level) - 1;
- nvgc_idx =3D nvp_idx & ~mask;
- nvgc_idx |=3D mask >> 1;
+ nvgc_blk =3D nvp_blk;
+ nvgc_idx =3D nvp_idx;
+ xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level);
=20
- if (xive2_router_get_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level),
+ nvgc_blk, nvgc_idx, &nvgc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return;
}
if (!xive2_nvgc_is_valid(&nvgc)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n",
- nvp_blk, nvgc_idx);
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n",
+ nvgc_blk, nvgc_idx);
return;
}
count =3D xive2_nvgc_get_backlog(&nvgc, group_prio);
@@ -442,7 +471,8 @@ static void xive2_presenter_backlog_decr(XivePresenter =
*xptr,
return;
}
xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1);
- xive2_router_write_nvgc(xrtr, false, nvp_blk, nvgc_idx, &nvgc);
+ xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level),
+ nvgc_blk, nvgc_idx, &nvgc);
}
=20
/*
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 12/14] pnv/xive: Support ESB Escalation
Date: Mon, 9 Dec 2024 18:05:25 -0600
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From: Glenn Miles <milesg@linux.vnet.ibm.com>
END notification processing has an escalation path. The escalation is
not always an END escalation but can be an ESB escalation.
Also added a check for 'resume' processing which log a message stating it
needs to be implemented. This is not needed at the time but is part of
the END notification processing.
This change was taken from a patch provided by Michael Kowal
Suggested-by: Michael Kowal <kowal@us.ibm.com>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
include/hw/ppc/xive2.h | 1 +
include/hw/ppc/xive2_regs.h | 13 +++++---
hw/intc/xive2.c | 61 +++++++++++++++++++++++++++++--------
3 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 8cdf819174..2436ddb5e5 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -80,6 +80,7 @@ int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
uint32_t xive2_router_get_config(Xive2Router *xrtr);
=20
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
+void xive2_notify(Xive2Router *xrtr, uint32_t lisn, bool pq_checked);
=20
/*
* XIVE2 Presenter (POWER10)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index b11395c563..164d61e605 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -39,15 +39,18 @@
=20
typedef struct Xive2Eas {
uint64_t w;
-#define EAS2_VALID PPC_BIT(0)
-#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ blo=
ck# */
-#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ in=
dex */
-#define EAS2_MASKED PPC_BIT(32) /* Masked */
-#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the E=
Q */
+#define EAS2_VALID PPC_BIT(0)
+#define EAS2_QOS PPC_BIT(1, 2) /* Quality of Service(unimp=
) */
+#define EAS2_RESUME PPC_BIT(3) /* END Resume(unimp) */
+#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
+#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
+#define EAS2_MASKED PPC_BIT(32) /* Masked */
+#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
} Xive2Eas;
=20
#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
+#define xive2_eas_is_resume(eas) (be64_to_cpu((eas)->w) & EAS2_RESUME)
=20
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf);
=20
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index c29d8e4831..44b7743b2b 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -1514,18 +1514,39 @@ do_escalation:
}
}
=20
- /*
- * The END trigger becomes an Escalation trigger
- */
- xive2_router_end_notify(xrtr,
- xive_get_field32(END2_W4_END_BLOCK, end.w4),
- xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
- xive_get_field32(END2_W5_ESC_END_DATA, end.w5)=
);
+ if (xive2_end_is_escalate_end(&end)) {
+ /*
+ * Perform END Adaptive escalation processing
+ * The END trigger becomes an Escalation trigger
+ */
+ xive2_router_end_notify(xrtr,
+ xive_get_field32(END2_W4_END_BLOCK, end=
.w4),
+ xive_get_field32(END2_W4_ESC_END_INDEX, end=
.w4),
+ xive_get_field32(END2_W5_ESC_END_DATA, end=
.w5));
+ } /* end END adaptive escalation */
+
+ else {
+ uint32_t lisn; /* Logical Interrupt Source Number */
+
+ /*
+ * Perform ESB escalation processing
+ * E[N] =3D=3D 1 --> N
+ * Req[Block] <- E[ESB_Block]
+ * Req[Index] <- E[ESB_Index]
+ * Req[Offset] <- 0x000
+ * Execute <ESB Store> Req command
+ */
+ lisn =3D XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4),
+ xive_get_field32(END2_W4_ESC_END_INDEX, end.w4));
+
+ xive2_notify(xrtr, lisn, true /* pq_checked */);
+ }
+
+ return;
}
=20
-void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
+void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked)
{
- Xive2Router *xrtr =3D XIVE2_ROUTER(xn);
uint8_t eas_blk =3D XIVE_EAS_BLOCK(lisn);
uint32_t eas_idx =3D XIVE_EAS_INDEX(lisn);
Xive2Eas eas;
@@ -1568,13 +1589,29 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t=
lisn, bool pq_checked)
return;
}
=20
+ /* TODO: add support for EAS resume if ever needed */
+ if (xive2_eas_is_resume(&eas)) {
+ qemu_log_mask(LOG_UNIMP,
+ "XIVE: EAS resume processing unimplemented - LISN %x=
\n",
+ lisn);
+ return;
+ }
+
/*
* The event trigger becomes an END trigger
*/
xive2_router_end_notify(xrtr,
- xive_get_field64(EAS2_END_BLOCK, eas.w),
- xive_get_field64(EAS2_END_INDEX, eas.w),
- xive_get_field64(EAS2_END_DATA, eas.w));
+ xive_get_field64(EAS2_END_BLOCK, eas.w),
+ xive_get_field64(EAS2_END_INDEX, eas.w),
+ xive_get_field64(EAS2_END_DATA, eas.w));
+}
+
+void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
+{
+ Xive2Router *xrtr =3D XIVE2_ROUTER(xn);
+
+ xive2_notify(xrtr, lisn, pq_checked);
+ return;
}
=20
static Property xive2_router_properties[] =3D {
--=20
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 13/14] pnv/xive: Fix problem with treating NVGC as a NVP
Date: Mon, 9 Dec 2024 18:05:26 -0600
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From: Glenn Miles <milesg@linux.ibm.com>
When booting with PHYP, the blk/index for a NVGC was being
mistakenly treated as the blk/index for a NVP. Renamed
nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent
confusion in the future and now we delay loading the NVP until
the point where we know that the block and index actually point to
a NVP.
Suggested-by: Michael Kowal <kowal@us.ibm.com>
Fixes: ("ppc/xive2: Support crowd-matching when looking for target")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
hw/intc/xive2.c | 78 ++++++++++++++++++++++++-------------------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 44b7743b2b..07f2d20aec 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -225,8 +225,8 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e=
nd_idx, GString *buf)
uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3);
uint32_t qentries =3D 1 << (qsize + 10);
=20
- uint32_t nvp_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6);
- uint32_t nvp_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6);
+ uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6);
+ uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6);
uint8_t priority =3D xive_get_field32(END2_W7_F0_PRIORITY, end->w7);
uint8_t pq;
=20
@@ -255,7 +255,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e=
nd_idx, GString *buf)
xive2_end_is_firmware2(end) ? 'F' : '-',
xive2_end_is_ignore(end) ? 'i' : '-',
xive2_end_is_crowd(end) ? 'c' : '-',
- priority, nvp_blk, nvp_idx);
+ priority, nvx_blk, nvx_idx);
=20
if (qaddr_base) {
g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
@@ -400,7 +400,7 @@ static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t =
*nvgc_idx,
* level of pending group interrupts.
*/
static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr,
- uint8_t nvp_blk, uint32_t nvp_=
idx,
+ uint8_t nvx_blk, uint32_t nvx_=
idx,
uint8_t first_group,
uint8_t *out_level)
{
@@ -412,8 +412,8 @@ static uint8_t xive2_presenter_backlog_scan(XivePresent=
er *xptr,
=20
for (prio =3D 0; prio <=3D XIVE_PRIORITY_MAX; prio++) {
current_level =3D first_group & 0x3F;
- nvgc_blk =3D nvp_blk;
- nvgc_idx =3D nvp_idx;
+ nvgc_blk =3D nvx_blk;
+ nvgc_idx =3D nvx_idx;
=20
while (current_level) {
xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level);
@@ -442,7 +442,7 @@ static uint8_t xive2_presenter_backlog_scan(XivePresent=
er *xptr,
}
=20
static void xive2_presenter_backlog_decr(XivePresenter *xptr,
- uint8_t nvp_blk, uint32_t nvp_idx,
+ uint8_t nvx_blk, uint32_t nvx_idx,
uint8_t group_prio,
uint8_t group_level)
{
@@ -451,8 +451,8 @@ static void xive2_presenter_backlog_decr(XivePresenter =
*xptr,
uint8_t nvgc_blk;
Xive2Nvgc nvgc;
=20
- nvgc_blk =3D nvp_blk;
- nvgc_idx =3D nvp_idx;
+ nvgc_blk =3D nvx_blk;
+ nvgc_idx =3D nvx_idx;
xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level);
=20
if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level),
@@ -1320,9 +1320,8 @@ static void xive2_router_end_notify(Xive2Router *xrtr=
, uint8_t end_blk,
uint8_t priority;
uint8_t format;
bool found, precluded;
- Xive2Nvp nvp;
- uint8_t nvp_blk;
- uint32_t nvp_idx;
+ uint8_t nvx_blk;
+ uint32_t nvx_idx;
=20
/* END cache lookup */
if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) {
@@ -1387,23 +1386,10 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
/*
* Follows IVPE notification
*/
- nvp_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end.w6);
- nvp_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end.w6);
-
- /* NVP cache lookup */
- if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
- nvp_blk, nvp_idx);
- return;
- }
-
- if (!xive2_nvp_is_valid(&nvp)) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n",
- nvp_blk, nvp_idx);
- return;
- }
+ nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end.w6);
+ nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end.w6);
=20
- found =3D xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
+ found =3D xive_presenter_notify(xrtr->xfb, format, nvx_blk, nvx_idx,
xive2_end_is_crowd(&end), xive2_end_is_ignore(&e=
nd),
priority,
xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w=
7),
@@ -1431,6 +1417,21 @@ static void xive2_router_end_notify(Xive2Router *xrt=
r, uint8_t end_blk,
=20
if (!xive2_end_is_ignore(&end)) {
uint8_t ipb;
+ Xive2Nvp nvp;
+
+ /* NVP cache lookup */
+ if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
+ nvx_blk, nvx_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid=
\n",
+ nvx_blk, nvx_idx);
+ return;
+ }
+
/*
* Record the IPB in the associated NVP structure for later
* use. The presenter will resend the interrupt when the vCPU
@@ -1439,7 +1440,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr=
, uint8_t end_blk,
ipb =3D xive_get_field32(NVP2_W2_IPB, nvp.w2) |
xive_priority_to_ipb(priority);
nvp.w2 =3D xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
- xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+ xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2);
} else {
Xive2Nvgc nvgc;
uint32_t backlog;
@@ -1452,32 +1453,31 @@ static void xive2_router_end_notify(Xive2Router *xr=
tr, uint8_t end_blk,
* counters are stored in the NVG/NVC structures
*/
if (xive2_router_get_nvgc(xrtr, crowd,
- nvp_blk, nvp_idx, &nvgc)) {
+ nvx_blk, nvx_idx, &nvgc)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n",
- crowd ? "NVC" : "NVG", nvp_blk, nvp_idx);
+ crowd ? "NVC" : "NVG", nvx_blk, nvx_idx);
return;
}
=20
if (!xive2_nvgc_is_valid(&nvgc)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid=
\n",
- nvp_blk, nvp_idx);
+ nvx_blk, nvx_idx);
return;
}
=20
/*
* Increment the backlog counter for that priority.
- * For the precluded case, we only call broadcast the
- * first time the counter is incremented. broadcast will
- * set the LSMFB field of the TIMA of relevant threads so
- * that they know an interrupt is pending.
+ * We only call broadcast the first time the counter is
+ * incremented. broadcast will set the LSMFB field of the TIMA=
of
+ * relevant threads so that they know an interrupt is pending.
*/
backlog =3D xive2_nvgc_get_backlog(&nvgc, priority) + 1;
xive2_nvgc_set_backlog(&nvgc, priority, backlog);
- xive2_router_write_nvgc(xrtr, crowd, nvp_blk, nvp_idx, &nvgc);
+ xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc);
=20
- if (precluded && backlog =3D=3D 1) {
+ if (backlog =3D=3D 1) {
XiveFabricClass *xfc =3D XIVE_FABRIC_GET_CLASS(xrtr->xfb);
- xfc->broadcast(xrtr->xfb, nvp_blk, nvp_idx,
+ xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx,
xive2_end_is_crowd(&end),
xive2_end_is_ignore(&end),
priority);
--=20
2.43.0
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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
milesg@linux.ibm.com, danielhb413@gmail.com,
david@gibson.dropbear.id.au, harshpb@linux.ibm.com, thuth@redhat.com,
lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH v2 14/14] qtest/xive: Add test of pool interrupts
Date: Mon, 9 Dec 2024 18:05:27 -0600
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From: Glenn Miles <milesg@linux.ibm.com>
Added new test for pool interrupts. Removed all printfs from pnv-xive2-* q=
tests.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/pnv-xive2-flush-sync.c | 6 +-
tests/qtest/pnv-xive2-nvpg_bar.c | 7 +--
tests/qtest/pnv-xive2-test.c | 98 +++++++++++++++++++++++++++---
3 files changed, 94 insertions(+), 17 deletions(-)
diff --git a/tests/qtest/pnv-xive2-flush-sync.c b/tests/qtest/pnv-xive2-flu=
sh-sync.c
index 3b32446adb..142826bad0 100644
--- a/tests/qtest/pnv-xive2-flush-sync.c
+++ b/tests/qtest/pnv-xive2-flush-sync.c
@@ -178,14 +178,14 @@ void test_flush_sync_inject(QTestState *qts)
int test_nr;
uint8_t byte;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Starting cache flush/queue sync injection tests...\n");
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Starting cache flush/queue sync injection tests...");
=20
for (test_nr =3D 0; test_nr < sizeof(xive_inject_tests);
test_nr++) {
int op_type =3D xive_inject_tests[test_nr];
=20
- printf("# Running test %d\n", test_nr);
+ g_test_message("Running test %d", test_nr);
=20
/* start with status byte set to 0 */
clr_sync(qts, src_pir, ic_topo_id, op_type);
diff --git a/tests/qtest/pnv-xive2-nvpg_bar.c b/tests/qtest/pnv-xive2-nvpg_=
bar.c
index 10d4962d1e..8481a70f22 100644
--- a/tests/qtest/pnv-xive2-nvpg_bar.c
+++ b/tests/qtest/pnv-xive2-nvpg_bar.c
@@ -4,8 +4,7 @@
*
* Copyright (c) 2024, IBM Corporation.
*
- * This work is licensed under the terms of the GNU GPL, version 2 or
- * later. See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "libqtest.h"
@@ -78,8 +77,8 @@ void test_nvpg_bar(QTestState *qts)
uint32_t count, delta;
uint8_t i;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Testing NVPG BAR operations\n");
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing NVPG BAR operations");
=20
set_nvg(qts, group_target, 0);
set_nvp(qts, nvp_target, 0x04);
diff --git a/tests/qtest/pnv-xive2-test.c b/tests/qtest/pnv-xive2-test.c
index a0e9f19313..5313d4ef18 100644
--- a/tests/qtest/pnv-xive2-test.c
+++ b/tests/qtest/pnv-xive2-test.c
@@ -4,6 +4,7 @@
* - Test 'Pull Thread Context to Odd Thread Reporting Line'
* - Test irq to hardware group
* - Test irq to hardware group going through backlog
+ * - Test irq to pool thread
*
* Copyright (c) 2024, IBM Corporation.
*
@@ -220,8 +221,8 @@ static void test_hw_irq(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Testing irq %d to hardware thread %d\n", irq, target_pir);
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing irq %d to hardware thread %d", irq, target_pir=
);
=20
/* irq config */
set_eas(qts, irq, end_index, irq_data);
@@ -266,6 +267,79 @@ static void test_hw_irq(QTestState *qts)
g_assert_cmphex(cppr, =3D=3D, 0xFF);
}
=20
+static void test_pool_irq(QTestState *qts)
+{
+ uint32_t irq =3D 2;
+ uint32_t irq_data =3D 0x600d0d06;
+ uint32_t end_index =3D 5;
+ uint32_t target_pir =3D 1;
+ uint32_t target_nvp =3D 0x100 + target_pir;
+ uint8_t priority =3D 5;
+ uint32_t reg32;
+ uint16_t reg16;
+ uint8_t pq, nsr, cppr, ipb;
+
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing irq %d to pool thread %d", irq, target_pir);
+
+ /* irq config */
+ set_eas(qts, irq, end_index, irq_data);
+ set_end(qts, end_index, target_nvp, priority, false /* group */);
+
+ /* enable and trigger irq */
+ get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_SET_PQ_00);
+ set_esb(qts, irq, XIVE_TRIGGER_PAGE, 0, 0);
+
+ /* check irq is raised on cpu */
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_PENDING);
+
+ /* check TIMA values in the PHYS ring (shared by POOL ring) */
+ reg32 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x40);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+
+ /* check TIMA values in the POOL ring */
+ reg32 =3D get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ ipb =3D (reg32 >> 8) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0);
+ g_assert_cmphex(cppr, =3D=3D, 0);
+ g_assert_cmphex(ipb, =3D=3D, 0x80 >> priority);
+
+ /* ack the irq */
+ reg16 =3D get_tima16(qts, target_pir, TM_SPC_ACK_HV_REG);
+ nsr =3D reg16 >> 8;
+ cppr =3D reg16 & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x40);
+ g_assert_cmphex(cppr, =3D=3D, priority);
+
+ /* check irq data is what was configured */
+ reg32 =3D qtest_readl(qts, xive_get_queue_addr(end_index));
+ g_assert_cmphex((reg32 & 0x7fffffff), =3D=3D, (irq_data & 0x7fffffff));
+
+ /* check IPB is cleared in the POOL ring */
+ reg32 =3D get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0);
+ ipb =3D (reg32 >> 8) & 0xFF;
+ g_assert_cmphex(ipb, =3D=3D, 0);
+
+ /* End Of Interrupt */
+ set_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_STORE_EOI, 0);
+ pq =3D get_esb(qts, irq, XIVE_EOI_PAGE, XIVE_ESB_GET);
+ g_assert_cmpuint(pq, =3D=3D, XIVE_ESB_RESET);
+
+ /* reset CPPR */
+ set_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_CPPR, 0xFF);
+ reg32 =3D get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0);
+ nsr =3D reg32 >> 24;
+ cppr =3D (reg32 >> 16) & 0xFF;
+ g_assert_cmphex(nsr, =3D=3D, 0x00);
+ g_assert_cmphex(cppr, =3D=3D, 0xFF);
+}
+
#define XIVE_ODD_CL 0x80
static void test_pull_thread_ctx_to_odd_thread_cl(QTestState *qts)
{
@@ -278,8 +352,9 @@ static void test_pull_thread_ctx_to_odd_thread_cl(QTest=
State *qts)
uint32_t cl_word;
uint32_t word2;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Testing 'Pull Thread Context to Odd Thread Reporting Line'\n=
");
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing 'Pull Thread Context to Odd Thread Reporting "=
\
+ "Line'");
=20
/* clear odd cache line prior to pull operation */
memset(cl_pair, 0, sizeof(cl_pair));
@@ -330,8 +405,8 @@ static void test_hw_group_irq(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Testing irq %d to hardware group of size 4\n", irq);
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing irq %d to hardware group of size 4", irq);
=20
/* irq config */
set_eas(qts, irq, end_index, irq_data);
@@ -395,10 +470,10 @@ static void test_hw_group_irq_backlog(QTestState *qts)
uint16_t reg16;
uint8_t pq, nsr, cppr, lsmfb, i;
=20
- printf("# =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n");
- printf("# Testing irq %d to hardware group of size 4 going through " \
- "backlog\n",
- irq);
+ g_test_message("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D");
+ g_test_message("Testing irq %d to hardware group of size 4 going " \
+ "through backlog",
+ irq);
=20
/*
* set current priority of all threads in the group to something
@@ -484,6 +559,9 @@ static void test_xive(void)
/* omit reset_state here and use settings from test_hw_irq */
test_pull_thread_ctx_to_odd_thread_cl(qts);
=20
+ reset_state(qts);
+ test_pool_irq(qts);
+
reset_state(qts);
test_hw_group_irq(qts);
=20
--=20
2.43.0