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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1733484164; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qmjoLu6lY502Dk2o1GeUKH/NYKFssFYjNhZ6QNGQyQg=; b=dnb8h+l9BklBwpv4hWRRbegO8TTmfOGBCvYqcEeUU70LLfBqosoacLyLxrm1iQ7rivfOGW KNhA7wKrGuSkuM2wdnryKDeJvXLbHj7nAtjc6JzKmQ0RV9awSyidEtgFpH1Yxls0QG/WiW EHiu5BLBHtMjbSc+m7tat15jafJSbI8= X-MC-Unique: pRJRNUj1PWO-fXvFAraEtQ-1 X-Mimecast-MFC-AGG-ID: pRJRNUj1PWO-fXvFAraEtQ From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH RFCv2 02/20] arm/cpu: Add sysreg definitions in cpu-sysregs.h Date: Fri, 6 Dec 2024 12:21:55 +0100 Message-ID: <20241206112213.88394-3-cohuck@redhat.com> In-Reply-To: <20241206112213.88394-1-cohuck@redhat.com> References: <20241206112213.88394-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger This new header contains macros that define aarch64 registers. In a subsequent patch, this will be replaced by a more exhaustive version that will be generated from linux arch/arm64/tools/sysreg file. Those macros are sufficient to migrate the storage of those ID regs from named fields in isar struct to an array cell. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h | 42 +++++++++++++++++++++++++++++++ target/arm/cpu.h | 54 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 target/arm/cpu-sysregs.h diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h new file mode 100644 index 000000000000..f4b63a3af77b --- /dev/null +++ b/target/arm/cpu-sysregs.h @@ -0,0 +1,42 @@ +#ifndef ARM_CPU_SYSREGS_H +#define ARM_CPU_SYSREGS_H + +/* to be generated */ + +#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4= , 0) +#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4= , 1) +#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4= , 5) +#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5= , 0) +#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5= , 1) +#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6= , 0) +#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6= , 1) +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6= , 2) +#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7= , 0) +#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7= , 1) +#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7= , 2) +#define SYS_ID_AA64MMFR3_EL1 sys_reg(3, 0, 0, 7= , 3) + +#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1= , 0) +#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1= , 1) +#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1= , 2) +#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1= , 4) +#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1= , 5) +#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1= , 6) +#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1= , 7) +#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2= , 0) +#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2= , 1) +#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2= , 2) +#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2= , 3) +#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2= , 4) +#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2= , 5) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2= , 6) +#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2= , 7) +#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3= , 0) +#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3= , 1) +#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3= , 2) +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3= , 4) +#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3= , 5) +#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3= , 6) +#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4= , 4) + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e359152a4dbc..9e0403c9810a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -144,6 +144,14 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; =20 +typedef struct ARMSysReg { + int op0; + int op1; + int crn; + int crm; + int op2; +} ARMSysReg; + /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -841,6 +849,51 @@ typedef struct IdRegMap { uint64_t regs[NR_ID_REGS]; } IdRegMap; =20 +#define ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 =3D (op1) & 3; \ + __op1 -=3D (__op1 =3D=3D 3); = \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +static inline uint64_t _get_idreg(const IdRegMap *map, ARMSysReg sr) +{ + int index =3D ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.crm,= sr.op2); + + return map->regs[index]; +} + +static inline void _set_idreg(IdRegMap *map, ARMSysReg sr, uint64_t value) +{ + int index =3D ARM_FEATURE_ID_RANGE_IDX(sr.op0, sr.op1, sr.crn, sr.crm,= sr.op2); + + map->regs[index] =3D value; +} + +/* REG is ID_XXX */ +#define FIELD_DP64_IDREG(MAP, REG, FIELD, VALUE) \ +{ \ +uint64_t regval =3D _get_idreg(MAP, SYS_ ## REG ## _EL1); \ +regval =3D FIELD_DP64(regval, REG, FIELD, VALUE); \ +_set_idreg(MAP, SYS_ ## REG ## _EL1, regval); \ +} + +#define FIELD_EX64_IDREG(MAP, REG, FIELD) \ +FIELD_EX64(_get_idreg(MAP, SYS_ ## REG ## _EL1), REG, FIELD) \ + +#define SET_IDREG(MAP, REG, VALUE) \ +_set_idreg(MAP, SYS_ ## REG ## _EL1, VALUE) + +#define GET_IDREG(MAP, REG) \ +_get_idreg(MAP, SYS_ ## REG ## _EL1) + +static inline ARMSysReg sys_reg(int op0, int op1, int crn, int crm, int op= 2) +{ + ARMSysReg sr =3D {op0, op1, crn, crm, op2}; + + return sr; +} + /** * ARMCPU: * @env: #CPUARMState @@ -1052,6 +1105,7 @@ struct ArchCPU { uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; + IdRegMap idregs; } isar; uint64_t midr; uint32_t revidr; --=20 2.47.0