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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 1/2] target/arm: Use float_status in helper_fcvtx_f64_to_f32
Date: Thu, 5 Dec 2024 21:19:51 -0600
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Pass float_status not env to match other functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
target/arm/tcg/helper-a64.h | 2 +-
target/arm/tcg/helper-a64.c | 3 +--
target/arm/tcg/translate-a64.c | 2 +-
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index 26e327af3a..0c120bf388 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -44,7 +44,7 @@ DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64=
, f64, fpst)
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
-DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
+DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index ff48bac1a8..35dce4bef3 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -384,10 +384,9 @@ float64 HELPER(frecpx_f64)(float64 a, float_status *fp=
st)
}
}
=20
-float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
+float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status *fpst)
{
float32 r;
- float_status *fpst =3D &env->vfp.fp_status;
int old =3D get_float_rounding_mode(fpst);
=20
set_float_rounding_mode(float_round_to_odd, fpst);
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 59df99d502..6286e4fda3 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9102,7 +9102,7 @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
* with von Neumann rounding (round to odd)
*/
TCGv_i32 tmp =3D tcg_temp_new_i32();
- gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env);
+ gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
tcg_gen_extu_i32_i64(d, tmp);
}
=20
--=20
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 2/2] target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
Date: Thu, 5 Dec 2024 21:19:52 -0600
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Pass float_status not env to match other functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate-a64.c | 15 ++++++++++-----
target/arm/tcg/translate-vfp.c | 4 ++--
target/arm/vfp_helper.c | 8 ++++----
4 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index d4c8ff40a1..6abab5da99 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -147,8 +147,8 @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
=20
-DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
-DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
+DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
+DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
=20
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 6286e4fda3..f0d5ce123e 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8502,8 +8502,9 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *=
a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn =3D read_fp_sreg(s, a->rn);
TCGv_i64 tcg_rd =3D tcg_temp_new_i64();
+ TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR);
=20
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
write_fp_dreg(s, a->rd, tcg_rd);
}
return true;
@@ -8528,8 +8529,9 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *=
a)
if (fp_access_check(s)) {
TCGv_i64 tcg_rn =3D read_fp_dreg(s, a->rn);
TCGv_i32 tcg_rd =3D tcg_temp_new_i32();
+ TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR);
=20
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
write_fp_sreg(s, a->rd, tcg_rd);
}
return true;
@@ -9208,7 +9210,9 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
{
TCGv_i32 tmp =3D tcg_temp_new_i32();
- gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
+ TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR);
+
+ gen_helper_vfp_fcvtsd(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp);
}
=20
@@ -9498,11 +9502,13 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_=
e *a)
* The only instruction like this is FCVTL.
*/
int pass;
+ TCGv_ptr fpst;
=20
if (!fp_access_check(s)) {
return true;
}
=20
+ fpst =3D fpstatus_ptr(FPST_FPCR);
if (a->esz =3D=3D MO_64) {
/* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2];
@@ -9512,7 +9518,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e =
*a)
for (pass =3D 0; pass < 2; pass++) {
tcg_res[pass] =3D tcg_temp_new_i64();
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
}
for (pass =3D 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
@@ -9521,7 +9527,6 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e =
*a)
/* 16 -> 32 bit fp conversion */
int srcelt =3D a->q ? 4 : 0;
TCGv_i32 tcg_res[4];
- TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR);
TCGv_i32 ahp =3D get_ahp_flag();
=20
for (pass =3D 0; pass < 4; pass++) {
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index c160a86e70..3cbe9a7418 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s=
p *a)
vm =3D tcg_temp_new_i32();
vd =3D tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, tcg_env);
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg64(vd, a->vd);
return true;
}
@@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d=
p *a)
vd =3D tcg_temp_new_i32();
vm =3D tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg32(vd, a->vd);
return true;
}
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 26a52852fc..40c13f3685 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -400,14 +400,14 @@ FLOAT_CONVS(ui, d, float64, 64, u)
#undef FLOAT_CONVS
=20
/* floating point conversion */
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
+float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
{
- return float32_to_float64(x, &env->vfp.fp_status);
+ return float32_to_float64(x, status);
}
=20
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
+float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
{
- return float64_to_float32(x, &env->vfp.fp_status);
+ return float64_to_float32(x, status);
}
=20
uint32_t HELPER(bfcvt)(float32 x, float_status *status)
--=20
2.43.0