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Tsirkin" , Richard Henderson , Cameron Esfahani , Roman Bolshakov , Marcelo Tosatti , qemu-devel@nongnu.org Subject: [RFC PATCH 1/4] i386/topology: Update the comment of x86_apicid_from_topo_ids() Date: Thu, 5 Dec 2024 09:57:13 -0500 Message-Id: <20241205145716.472456-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205145716.472456-1-xiaoyao.li@intel.com> References: <20241205145716.472456-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.17; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.822, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1733411538860116600 Content-Type: text/plain; charset="utf-8" Update the comment of x86_apicid_from_topo_ids() to match the current implementation, Signed-off-by: Xiaoyao Li Acked-by: Igor Mammedov Reviewed-by: Zhao Liu --- include/hw/i386/topology.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index b2c8bf2de158..21b65219a5ca 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -121,9 +121,10 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInf= o *topo_info) } =20 /* - * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * Make APIC ID for the CPU based on topology and IDs of each topology lev= el. * - * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + * The caller must make sure the ID of each level doesn't exceed the width= of + * the level. */ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo= _ids) --=20 2.34.1 From nobody Fri Dec 19 20:29:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 05 Dec 2024 10:11:11 -0500 Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 07:11:07 -0800 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa006.fm.intel.com with ESMTP; 05 Dec 2024 07:11:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733411469; x=1764947469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5wJyvwlOPKfr/u0glTCnSt2gyjP+AJEu8XtdgGtzWR8=; b=ej9PdSKlxacpSCiYJXmCPRAx5WH6Z3hWmZQhvshG/byFwQPoeel9Ae0e 61GxvnZIjHmF9HkQxMrQsx2t3/pU11/LKl8lTnpl47SS+7/1Nd/RgXxWQ ojBN/ZzpbzJtEjD3ccvlizZEtiidB+jIXov55nTrMoYNxtPBmcAYKLyy0 ZTObzkfGdzpRPhPkH3E2888JJgSGmq0+Oum/L6nELVnMTWE0j09Gallvl swOzLAod6RxTjTS3LtO79b1T74Fl8UBSK8inc/Y8amdULnuxTJvpdaeS3 dGqO4q5VbsLSOvpgDD6dTQdoe9A44BtyKi7pjNcbgguCoZKRzk3fTHJZt A==; X-CSE-ConnectionGUID: o96jG/OVS3yhfUIpmvz4sw== X-CSE-MsgGUID: oUNRJB3STXy+PTw/HAalGg== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="33786137" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="33786137" X-CSE-ConnectionGUID: 91Q0Wg6HShCwjfjgZBXwfA== X-CSE-MsgGUID: R7TUV8f/R7OlcA1ES63rHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="93803100" From: Xiaoyao Li To: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov Cc: xiaoyao.li@intel.com, Marcel Apfelbaum , Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Richard Henderson , Cameron Esfahani , Roman Bolshakov , Marcelo Tosatti , qemu-devel@nongnu.org Subject: [RFC PATCH 2/4] i386: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT Date: Thu, 5 Dec 2024 09:57:14 -0500 Message-Id: <20241205145716.472456-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205145716.472456-1-xiaoyao.li@intel.com> References: <20241205145716.472456-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.17; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.822, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1733411532952116600 Content-Type: text/plain; charset="utf-8" There are duplicated code to setup the value of MSR_CORE_THREAD_COUNT. Extract a common function for it. Signed-off-by: Xiaoyao Li Acked-by: Igor Mammedov --- target/i386/cpu.h | 11 +++++++++++ target/i386/hvf/x86_emu.c | 3 +-- target/i386/kvm/kvm.c | 5 +---- target/i386/tcg/sysemu/misc_helper.c | 3 +-- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4c239a6970fd..5795a497e567 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2390,6 +2390,17 @@ static inline void cpu_x86_load_seg_cache_sipi(X86CP= U *cpu, cs->halted =3D 0; } =20 +static inline uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + uint64_t val; + + val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + + return val; +} + int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, target_ulong *base, unsigned int *limit, unsigned int *flags); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 015f760acb39..69c61c9c0737 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -765,8 +765,7 @@ void simulate_rdmsr(CPUX86State *env) val =3D env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..= 0 */ - val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..1= 6 */ + val =3D cpu_x86_get_msr_core_thread_count(cpu); break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8e17942c3ba1..18a1bd1297a4 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2602,10 +2602,7 @@ static bool kvm_rdmsr_core_thread_count(X86CPU *cpu, uint32_t msr, uint64_t *val) { - CPUState *cs =3D CPU(cpu); - - *val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - *val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + *val =3D cpu_x86_get_msr_core_thread_count(cpu); =20 return true; } diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index 094aa56a20d1..ff7b201b44d8 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -468,8 +468,7 @@ void helper_rdmsr(CPUX86State *env) val =3D x86_cpu->ucode_rev; break; case MSR_CORE_THREAD_COUNT: { - CPUState *cs =3D CPU(x86_cpu); - val =3D (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); + val =3D cpu_x86_get_msr_core_thread_count(x86_cpu); break; } case MSR_APIC_START ... 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Tsirkin" , Richard Henderson , Cameron Esfahani , Roman Bolshakov , Marcelo Tosatti , qemu-devel@nongnu.org Subject: [RFC PATCH 3/4] i386: Track cores_per_module in CPUX86State Date: Thu, 5 Dec 2024 09:57:15 -0500 Message-Id: <20241205145716.472456-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205145716.472456-1-xiaoyao.li@intel.com> References: <20241205145716.472456-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.17; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.822, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1733411531419116600 Content-Type: text/plain; charset="utf-8" x86 is the only user of CPUState::nr_cores. Define cores_per_module in CPUX86State, which can serve as the substitute of CPUState::nr_cores. After x86 switches to use CPUX86State::cores_per_module, CPUState::nr_cores will lose the only user and QEMU can drop it. Signed-off-by: Xiaoyao Li Acked-by: Igor Mammedov --- hw/i386/x86-common.c | 2 ++ target/i386/cpu.c | 2 +- target/i386/cpu.h | 9 +++++++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index dc031af66217..f7a20c1da30c 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,6 +271,8 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 init_topo_info(&topo_info, x86ms); =20 + env->nr_cores =3D ms->smp.cores; + if (ms->smp.modules > 1) { env->nr_modules =3D ms->smp.modules; set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3725dbbc4b3f..15b50c44ae79 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6503,7 +6503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, =20 topo_info.dies_per_pkg =3D env->nr_dies; topo_info.modules_per_die =3D env->nr_modules; - topo_info.cores_per_module =3D cs->nr_cores / env->nr_dies / env->nr_m= odules; + topo_info.cores_per_module =3D env->nr_cores; topo_info.threads_per_core =3D cs->nr_threads; =20 cores_per_pkg =3D topo_info.cores_per_module * topo_info.modules_per_d= ie * diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5795a497e567..c37a49a1a02b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2051,6 +2051,9 @@ typedef struct CPUArchState { /* Number of modules within one die. */ unsigned nr_modules; =20 + /* Number of cores within one module. */ + unsigned nr_cores; + /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); } CPUX86State; @@ -2393,10 +2396,12 @@ static inline void cpu_x86_load_seg_cache_sipi(X86C= PU *cpu, static inline uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu) { CPUState *cs =3D CPU(cpu); + CPUX86State *env =3D &cpu->env; uint64_t val; + uint64_t cores_per_package =3D env->nr_cores * env->nr_modules * env->= nr_dies; =20 - val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + val =3D cs->nr_threads * cores_per_package; /* thread count, bits 15.= .0 */ + val |=3D (cores_per_package << 16); /* core count, bits 31..16 */ =20 return val; } --=20 2.34.1 From nobody Fri Dec 19 20:29:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1733411545; cv=none; d=zohomail.com; s=zohoarc; b=Kpagl/yUIww+Y7vo0a9ACWFxhjpfpi9R8arafU8ESRrr7dIvhIeDO5cx30kz8RujblBVDjHH2BwV2EcgrPsNRUwwdFI+0ycvhfOnfeO1Wa5Qbkmtt/N6beJxqt5zk/WZhbbdicrDZwTWVlETnPChc2LZwPfZ/wdOj29e/LKKEmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733411545; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: /o/c8ISuR9aGHuWotCn/XA== X-CSE-MsgGUID: GfallRMqTmuJndHOoLlT1A== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="33786185" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="33786185" X-CSE-ConnectionGUID: M6PpUGHlSvSFoAXumBbZFg== X-CSE-MsgGUID: xl2h8GJlRpuDZZ5t5zSsXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="93803132" From: Xiaoyao Li To: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov Cc: xiaoyao.li@intel.com, Marcel Apfelbaum , Yanan Wang , Zhao Liu , "Michael S. Tsirkin" , Richard Henderson , Cameron Esfahani , Roman Bolshakov , Marcelo Tosatti , qemu-devel@nongnu.org Subject: [RFC PATCH 4/4] cpu: Remove nr_cores from struct CPUState Date: Thu, 5 Dec 2024 09:57:16 -0500 Message-Id: <20241205145716.472456-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205145716.472456-1-xiaoyao.li@intel.com> References: <20241205145716.472456-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.17; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.822, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1733411547010116600 Content-Type: text/plain; charset="utf-8" There is no user of it now, remove it. Signed-off-by: Xiaoyao Li Acked-by: Igor Mammedov Reviewed-by: Zhao Liu --- hw/core/cpu-common.c | 1 - hw/i386/x86-common.c | 2 +- include/hw/core/cpu.h | 2 -- system/cpus.c | 1 - 4 files changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 09c79035949b..77089d4ed304 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -243,7 +243,6 @@ static void cpu_common_initfn(Object *obj) cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ - cpu->nr_cores =3D 1; cpu->nr_threads =3D 1; cpu->cflags_next_tb =3D -1; =20 diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index f7a20c1da30c..2dd7d8e34b76 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -377,7 +377,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, */ /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private - * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ + * CPUState::nr_threads fields instead of globals */ x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c3ca0babcb3f..fb397cdfc53d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -407,7 +407,6 @@ struct qemu_work_item; * Under TCG this value is propagated to @tcg_cflags. * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. - * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU core. * @thread: Host thread details, only live once @created is #true * @sem: WIN32 only semaphore used only for qtest @@ -466,7 +465,6 @@ struct CPUState { CPUClass *cc; /*< public >*/ =20 - int nr_cores; int nr_threads; =20 struct QemuThread *thread; diff --git a/system/cpus.c b/system/cpus.c index 1c818ff6828c..909d8128e81b 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -666,7 +666,6 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms =3D MACHINE(qdev_get_machine()); =20 - cpu->nr_cores =3D machine_topo_get_cores_per_socket(ms); cpu->nr_threads =3D ms->smp.threads; cpu->stopped =3D true; cpu->random_seed =3D qemu_guest_random_seed_thread_part1(); --=20 2.34.1