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Thu, 05 Dec 2024 03:23:12 -0800 (PST) From: baturo.alexey@gmail.com To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v12 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Date: Thu, 5 Dec 2024 14:23:00 +0300 Message-Id: <20241205112304.593204-4-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241205112304.593204-1-baturo.alexey@gmail.com> References: <20241205112304.593204-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733397899839116600 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 5 +++ target/riscv/cpu_helper.c | 74 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 417ff45544..74d7076f5a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -768,8 +768,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, =20 bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +int riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dba04851d5..2558f869f2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -214,6 +214,80 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, *pflags =3D flags; } =20 +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ + RISCVPmPmm pmm =3D PMM_FIELD_DISABLED; +#ifndef CONFIG_USER_ONLY + if (get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MXR)) { + return pmm; + } + int priv_mode =3D cpu_address_mode(env); + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + if (riscv_cpu_cfg(env)->ext_smmpm) { + pmm =3D get_field(env->mseccfg, MSECCFG_PMM); + } + break; + case PRV_S: + if (riscv_cpu_cfg(env)->ext_smnpm) { + if (get_field(env->mstatus, MSTATUS_MPV)) { + pmm =3D get_field(env->henvcfg, HENVCFG_PMM); + } else { + pmm =3D get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + case PRV_U: + if (riscv_has_ext(env, RVS)) { + if (riscv_cpu_cfg(env)->ext_ssnpm) { + pmm =3D get_field(env->senvcfg, SENVCFG_PMM); + } + } else { + if (riscv_cpu_cfg(env)->ext_smnpm) { + pmm =3D get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + default: + g_assert_not_reached(); + } +#endif + return pmm; +} + +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +{ + bool virt_mem_en =3D false; +#ifndef CONFIG_USER_ONLY + int satp_mode =3D 0; + int priv_mode =3D cpu_address_mode(env); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + satp_mode =3D get_field(env->satp, SATP32_MODE); + } else { + satp_mode =3D get_field(env->satp, SATP64_MODE); + } + virt_mem_en =3D ((satp_mode !=3D VM_1_10_MBARE) && (priv_mode !=3D PRV= _M)); +#endif + return virt_mem_en; +} + +int riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } + return -1; +} + #ifndef CONFIG_USER_ONLY =20 /* --=20 2.39.5