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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ef270089b8sm1905830a91.14.2024.12.04.13.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 13:12:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733346771; x=1733951571; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qe8Fwjt3cZmqYIi+Ypk/U57pACJEEsU9bKkurpvi7fE=; b=W/TsJ2W9pCwBXOmRctFooKw6w7b9E4ht9tKE8fgkw9xSxO9P7we4nlxQaCO2U77qDZ /1cNVveX5W7u2Qp/Q2jbCiQQFpYwND9bvAycipsOYAT8NznrZCxQwlf8flFBcHeO4JQv clGyqGn+OX2l7wSzD/lag00qxewaUZAcN/4CRvkxFGGV/7X7fxnEl7aX6zZhAiVESMSp i8I8/LEWVcMF4PN5i7BpyK6s/n4HdGxwR91yjQCjrxsfGoQ5AlcH0XO9XYLrMOIm9bp+ exnPXGNJlo3kVCMVilthFpeb/H0dPZsGPPXR8q1ypspdZJCewnZDXdCzISvNQlrrW9u5 Vt2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733346771; x=1733951571; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qe8Fwjt3cZmqYIi+Ypk/U57pACJEEsU9bKkurpvi7fE=; b=arJyOSil+R9IGRISj8Y9bo+wG3MttP+B/0q0RcHELrgMsuf2tFxQQbuhVKE/zdUavG cbbBvV2v0rgSaVU2e2NXMzHetpT0f3AXaLER5nnUyecWf9GJJnyQsvLixHvO8gOr6Q+O 3xnSPCGUO6C9+VzQQlbvRTWZQWlqrhLb2hXSyOZtSW2FRH3SM8WGxvDOyiUD60E0LtYz 4lUk+Zl0KZPjCb+q5TEnj4h9r8GJpjiQ18tFIdC2skJKYoqK5SzlgBgScMEiOfRe++O0 Ao41AF0OTHPeCboaS4VwP0TlRwQyKDZtul8+6CVDeuWPpq2gzjZEsRFhjWSetlJ+sCZm 8wAQ== X-Gm-Message-State: AOJu0YxpOElj3fjn3jhgG7oaLoU14eVe37HA89jJiOcYfJHVxoOmr/dA h+D/yAaKFCUYwr2g0xIeOf2+nW60Lij1mMPZDQegq6GfI0l4naIk6HyWrFCRpBG73w5G2fGZ4bS PNIQ= X-Gm-Gg: ASbGncukAB3yj9YSX7UeN7T+jajG7zDG+UGJ/43WseDOKbsBLlNl7KEANTqjX4uqA0v 1u9K5Plm7KLjSQ+H9pf1KX+lvfZPxTCv6RaXVSdQEFhX1y7gS22mYDplql0ZhDA1RNLc/hqsrah ieZY0gBIsa3UC32jQKg7mNIdCzzNcy3tfw3ofCLi2erWlV91A94e/HkROHbIcmOISWaAWhZRalo WAcFfk3sNnmUuakD63IJtUeohh50c3XAhLsx5wwmein1K9I3XdGDe8mTdFAThJa/ZIU75Mtu0lf nWQLyPUr X-Google-Smtp-Source: AGHT+IGAEJ+IkibZZ4NSFezHeXS0d9EMISHj3eKyt1xgsrO1FUjC0J5L6HjQJ7RuCRU5lP1yls71kg== X-Received: by 2002:a17:90b:394f:b0:2ee:4b8f:a5b1 with SMTP id 98e67ed59e1d1-2ef0126210dmr11045969a91.24.1733346766435; Wed, 04 Dec 2024 13:12:46 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Paolo Bonzini , alex.bennee@linaro.org, Fabiano Rosas , qemu-arm@nongnu.org, Peter Maydell , Pierrick Bouvier Subject: [PATCH 1/2] target/arm: add new property to select pauth-qarma5 Date: Wed, 4 Dec 2024 13:12:33 -0800 Message-Id: <20241204211234.3077434-2-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241204211234.3077434-1-pierrick.bouvier@linaro.org> References: <20241204211234.3077434-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1733346836502116600 Content-Type: text/plain; charset="utf-8" Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=3Don ... Signed-off-by: Pierrick Bouvier --- docs/system/arm/cpu-features.rst | 5 ++++- target/arm/cpu.h | 1 + target/arm/arm-qmp-cmds.c | 2 +- target/arm/cpu64.c | 20 ++++++++++++++------ tests/qtest/arm-cpu-features.c | 15 +++++++++++---- 5 files changed, 31 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index a5fb929243c..d69ebc2b852 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -219,7 +219,10 @@ Below is the list of TCG VCPU features and their descr= iptions. ``pauth-qarma3`` When ``pauth`` is enabled, select the architected QARMA3 algorithm. =20 -Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled, +``pauth-qarma5`` + When ``pauth`` is enabled, select the architected QARMA5 algorithm. + +Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, the architected QARMA5 algorithm is used. The architected QARMA5 and QARMA3 algorithms have good cryptographic properties, but can be quite slow to emulate. The impdef algorithm used by QEMU is diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d86e641280d..b7500bebd7f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1062,6 +1062,7 @@ struct ArchCPU { bool prop_pauth; bool prop_pauth_impdef; bool prop_pauth_qarma3; + bool prop_pauth_qarma5; bool prop_lpa2; =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 3cc8cc738bb..33cea080d11 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -94,7 +94,7 @@ static const char *cpu_model_advertised_features[] =3D { "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", "kvm-no-adjvtime", "kvm-steal-time", - "pauth", "pauth-impdef", "pauth-qarma3", + "pauth", "pauth-impdef", "pauth-qarma3", "pauth-qarma5", NULL }; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 458d1cee012..34ef46d148f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -520,9 +520,12 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } =20 if (cpu->prop_pauth) { - if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { + if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) || + (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) || + (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) { error_setg(errp, - "cannot enable both pauth-impdef and pauth-qarm= a3"); + "cannot enable pauth-impdef, pauth-qarma3 and " + "pauth-qarma5 at the same time"); return; } =20 @@ -532,13 +535,15 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } else if (cpu->prop_pauth_qarma3) { isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); - } else { + } else { /* default is pauth-qarma5 */ isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); } - } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { - error_setg(errp, "cannot enable pauth-impdef or " - "pauth-qarma3 without pauth"); + } else if (cpu->prop_pauth_impdef || + cpu->prop_pauth_qarma3 || + cpu->prop_pauth_qarma5) { + error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or " + "pauth-qarma5 without pauth"); error_append_hint(errp, "Add pauth=3Don to the CPU property li= st.\n"); } } @@ -553,6 +558,8 @@ static Property arm_cpu_pauth_impdef_property =3D DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); static Property arm_cpu_pauth_qarma3_property =3D DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); +static Property arm_cpu_pauth_qarma5_property =3D + DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false); =20 void aarch64_add_pauth_properties(Object *obj) { @@ -573,6 +580,7 @@ void aarch64_add_pauth_properties(Object *obj) } else { qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_proper= ty); qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_proper= ty); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_proper= ty); } } =20 diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cfd6f773535..98d6c970ea5 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -419,21 +419,28 @@ static void pauth_tests_default(QTestState *qts, cons= t char *cpu_type) assert_has_feature_enabled(qts, cpu_type, "pauth"); assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3"); + assert_has_feature_disabled(qts, cpu_type, "pauth-qarma5"); assert_set_feature(qts, cpu_type, "pauth", false); assert_set_feature(qts, cpu_type, "pauth", true); assert_set_feature(qts, cpu_type, "pauth-impdef", true); assert_set_feature(qts, cpu_type, "pauth-impdef", false); assert_set_feature(qts, cpu_type, "pauth-qarma3", true); assert_set_feature(qts, cpu_type, "pauth-qarma3", false); + assert_set_feature(qts, cpu_type, "pauth-qarma5", true); + assert_set_feature(qts, cpu_type, "pauth-qarma5", false); assert_error(qts, cpu_type, - "cannot enable pauth-impdef or pauth-qarma3 without pauth= ", + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5= without pauth", "{ 'pauth': false, 'pauth-impdef': true }"); assert_error(qts, cpu_type, - "cannot enable pauth-impdef or pauth-qarma3 without pauth= ", + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5= without pauth", "{ 'pauth': false, 'pauth-qarma3': true }"); assert_error(qts, cpu_type, - "cannot enable both pauth-impdef and pauth-qarma3", - "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': t= rue }"); + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5= without pauth", + "{ 'pauth': false, 'pauth-qarma5': true }"); + assert_error(qts, cpu_type, + "cannot enable pauth-impdef, pauth-qarma3 and pauth-qarma= 5 at the same time", + "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': t= rue," + " 'pauth-qarma5': true }"); } =20 static void test_query_cpu_model_expansion(const void *data) --=20 2.39.5 From nobody Mon Feb 9 18:42:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1733346833; cv=none; d=zohomail.com; s=zohoarc; b=YZrCq7Ra+rEhdy9VQOP+3zpqFqMNe/pifYsLNxRDFbenLgHCKhi/zvKkX9uZ1EFq9p/nGsLv6/LYlLVUZo2JZwVt0/t7K2fv78J1SBA1wqVGj3HHitG6wBAJUd5DmKGq1SLJMQgne4csKUcKaiCGCiOpQl/KQKOINoHjbX0ygFc= ARC-Message-Signature: i=1; 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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ef270089b8sm1905830a91.14.2024.12.04.13.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 13:12:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733346772; x=1733951572; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=okXND1T4OJuVtkNA/GEh6VGd1mAgkVoLXbl0XLbMi40=; b=r1AlSc5gHSRDWbP7vh6LzhhPXu3ZK0xtw1oPLNRxYDMbky2iIXf39cUeIVOL01eih/ JIvAegVjGL8JLM7b81KQgntqDfyIRh7pHGY6fyrCnPpjVWxwk9jIdCC4+96S7lSYSn3I 54wniYzuDtCXuB7HsppVHPms7ptl4R/nHHQ5TYqTenkb7Zy7QjrSTXpcbAtVXk+NDK1y U+IfDhzSCm7qPAft/v6oHPIoLOCRtXgkrjULZSaJx+m/tsjT6wSTXNHQIPlIsoVMSyAA sQFV+3712UDT+nNXsPgacRJ2Hcy0I4+DvXe9RBCk6xWXZdyYR8aXZjP+FPPIzNBe9WSQ wavg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733346772; x=1733951572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=okXND1T4OJuVtkNA/GEh6VGd1mAgkVoLXbl0XLbMi40=; b=gVv44awxanX6IjgaNyersMF3GrL9p71GMKCSV48omyWs4QE0q96PCVloOb96nax1f5 EQm6q6b8uNwv7Qy/VkqDQhRSG3pnkxYibYJ7Ok5kBFzghX2lP7KHEC8Z8yBrtzoOjaJN vu8+9DefQH3DjEw0omTU9jKTgLql8zVBurt/S24g+s06Nz4c/kyMX+SOI193lRdFm6ap uWakOWhv7noCvnZvCnUcKVC9mnUglG8WidtiiSt1FJLTNUTo8N0LwidHzR9IQr3e9ACH 2s9gXr5P1Zug2RbrUPj0FjaLtTKPBcmZdvMZXRi9KZqDYCHGN7FHSJ/RdyJ6qJtgTR+g LwGQ== X-Gm-Message-State: AOJu0YwO+66lbSGEqqXm+QhI5pl9xwEOeJwiNzXhO+3YbMpluJ9NXpg1 l1/+QV3UKYFW8ARcLqeAIM4vpu5rSgpupMb6faboL3Rb2+kNrxwOxpEh9UKRs+lkMWnZgiXBnT+ 5Zj4= X-Gm-Gg: ASbGncsdAsXauhgAQEaSiLkPsIlEgbP4kDOCro+YZ85VyjJfcmrtf2cpeJf57ZDb0hF zcbJV+E8JAPUj7WqGDNJ8QSCkw2PdPABEnYyqV3FSR8KuLPxsjZ1QawZKWHKEOHlXp6XbLVmDFa w/gUQwT31xZM3pjDqDqQLRN7eEc0ENrvU1V+A5EyXITGleo7G+xpFahPKrmYIHeA66Ba3RmBKR8 JLy3DEtFVnsi9/BEdqm7WwrWALs26PS1BwDNxyuBdFKGyw8t4/4tD5fxo2CPW4/UkZqjvnwuoto G/wAP/2F X-Google-Smtp-Source: AGHT+IFs6zydCz/aedghNnDWrbYfsm75thqJc6ke8CFCc8uPywde2n7KPs8HxmzH15WSEGUhXju5qA== X-Received: by 2002:a17:90b:3b4f:b0:2ee:d63f:d77 with SMTP id 98e67ed59e1d1-2ef011fb85bmr11125389a91.9.1733346767525; Wed, 04 Dec 2024 13:12:47 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Laurent Vivier , Paolo Bonzini , alex.bennee@linaro.org, Fabiano Rosas , qemu-arm@nongnu.org, Peter Maydell , Pierrick Bouvier Subject: [PATCH 2/2] target/arm: change default pauth algorithm to impdef Date: Wed, 4 Dec 2024 13:12:34 -0800 Message-Id: <20241204211234.3077434-3-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241204211234.3077434-1-pierrick.bouvier@linaro.org> References: <20241204211234.3077434-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1733346834386116600 Content-Type: text/plain; charset="utf-8" Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=3Don). The advice is always: use pauth-impdef=3Don. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we change the default to use impdef by default. This does not affect kvm or hvf acceleration, since pauth algorithm used is the one from host cpu. This change is retro compatible, in terms of cli, with previous versions, as the semantic of using -cpu max,pauth-impdef=3Don, and -cpu max,pauth-qarma3=3Don is preserved. The new option introduced in previous patch and matching old default is -cpu max,pauth-qarma5=3Don. Signed-off-by: Pierrick Bouvier --- docs/system/arm/cpu-features.rst | 2 +- docs/system/introduction.rst | 2 +- target/arm/cpu64.c | 12 ++++++------ 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index d69ebc2b852..37d5dfd15b3 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -223,7 +223,7 @@ Below is the list of TCG VCPU features and their descri= ptions. When ``pauth`` is enabled, select the architected QARMA5 algorithm. =20 Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, -the architected QARMA5 algorithm is used. The architected QARMA5 +the QEMU impdef algorithm is used. The architected QARMA5 and QARMA3 algorithms have good cryptographic properties, but can be quite slow to emulate. The impdef algorithm used by QEMU is non-cryptographic but significantly faster. diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst index 746707eb00e..338d3745c3c 100644 --- a/docs/system/introduction.rst +++ b/docs/system/introduction.rst @@ -169,7 +169,7 @@ would default to it anyway. =20 .. code:: =20 - -cpu max,pauth-impdef=3Don \ + -cpu max \ -smp 4 \ -accel tcg \ =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 34ef46d148f..8b1f26a9664 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -529,15 +529,15 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) return; } =20 - if (cpu->prop_pauth_impdef) { - isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, API, features); - isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); + if (cpu->prop_pauth_qarma5) { + isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); + isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); } else if (cpu->prop_pauth_qarma3) { isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); - } else { /* default is pauth-qarma5 */ - isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); - isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); + } else { /* default is pauth-impdef */ + isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, API, features); + isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); } } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3 || --=20 2.39.5