From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317103; cv=none; d=zohomail.com; s=zohoarc; b=OQU5b8MhtUCxcnP8bYIE0AbR2+qKM/30dh43TTTITHxZ+TLrqZ/NqegkJzvckviFFWhidiu9wwn0kuJVhuspXlaksQIURnlNSQtoYK4kYvmM7zMRC/gow5iBQSNcXMLUT/96BkZORL8DlDZZoetQZVlFeDznz3m1ot63rE4arYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1FnTMiXuPkhQQ6QNckrBef68BYhMTfBUPg6gnsrR5Ck=; b=gB9Rc1odhAmSzcwIQBsbD1xhp76wf4pUmkQNwAGfGNGPKR0RAHBMjJ9uiNxrq4WDJW1zYytCkJFeqBVIjGyvT3VC05t2H367p50zWMj+4usndKaDkdI6NJG7JEtN/YTKPvdbSse7n1CWqFGTRHdZUwg9+cQSeWSJmKlt9VQ0jUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317103053214.50666666474513; Wed, 4 Dec 2024 04:58:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIowy-0007zx-Qm; Wed, 04 Dec 2024 07:57:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIowl-0007z1-HP for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:39 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIowg-0007WZ-R2 for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:36 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so4467711f8f.2 for ; Wed, 04 Dec 2024 04:57:34 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317053; x=1733921853; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1FnTMiXuPkhQQ6QNckrBef68BYhMTfBUPg6gnsrR5Ck=; b=0ElfBWAUAgE7f9PZhz7G9CWRXGOH+MlN4ADTz0XBtSHRYFymppJV1T7vDU39acTDmc kXncucj8WZTKz+IvCCDK48HOO4JmuYDNgjzY20InUxPlmqEkM+2KC3frENQCkX9i3yLc y9HxgT/HRH9z3Zxm7bnl5weesHcp0L5tmELBzF844koXrWe1/CudU5od1+hAcHTD7FQF tT8sPePT8ZYfhyxXz2X4f/8aPlBJ9sVCJPOsMIbGB5lj9nsFSvwxlfLmOENnbiwzAC5Z 9LPc8xdD4RT5MgMOhxqEP9Cv5yRcDWmX31+A76UdHjHXyCG9xhynlTwgVLBoYEx5TQza J+3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317053; x=1733921853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1FnTMiXuPkhQQ6QNckrBef68BYhMTfBUPg6gnsrR5Ck=; b=IHTVSQ+ZajQatswHKG2xBQtmSEFYEN/kgAQbQPtHKfjOzR+8LkJX9uS5PzHzsUWThp r3p3cs4SnzD4V9yWIQPItjzXKX7Uh+JMhJ0283DzKUn28CDqsKd6EXaLNufr3wGJYsno 4zc6ELkU9PrHzc/w4A5mDn83UNT5jT79D3hISZDSunhCXCG5yH4HUEhtlA7vY6Ba4lv+ 9zYrBjhHIiofHsRxb64DTLQ0WGW4WCskQHg8YipaKa7d6sDGiyH8XcX4CF7pq+RP4YFX Y7fEcAd4k9RoWpWIPAOhSG+N01EVuassdnNPAGL1bZapVDgFBwvVOE9shNZnUW/zdJ/6 h6TA== X-Forwarded-Encrypted: i=1; AJvYcCW5aPaiORTHqWdUriZeLye7wrIfr5HGoqanFuH9t4pmFQwTgJw2aBo3MUJbM6DtQ74e9eUIRq++L7WM@nongnu.org X-Gm-Message-State: AOJu0Yz+xLrztPa89QSKPiF1mnaNpNBclNltMgs8pHPktBRCSphSRbry k4NWARsvpRIqIG4zvmXfChrN2POOtXWWbr5P9DAPyPHURLuNR+j1SPkdIh4uLho= X-Gm-Gg: ASbGncvXxo7gN0NEZ8YeWTAIIndQAxtJ7zEQDYFzTvLSc1NYxlw+Cczke8iKUqP08E9 sKxStXGSbjNUWyrMR+frtEMZ3lUw24WPTB9QIIuZ453nXS+9oUTnRaR8ZyGVklCtDLE5HwHaMoO M+T0mndjN4TRnDA1fl02O7nHLcl9rjB0+GYTQAkpfmek6UVY08aDRKzBTDyIlelg1Zc1UPzMVGv 4RtHfE/upfL/aUQ9XzdgE94V8kUk0ywS9NVBH53kE4erfGVtt0FOhyT5dytFc7dCQ9X9Uu/zBj2 I+57DA== X-Google-Smtp-Source: AGHT+IHXkLFcZy8q0ESesZOdwe4vvvKXPZsJb8jBgsIgEB9bwXOOGSqTey68BE/qrv5v89z2J7N7Ug== X-Received: by 2002:a05:6000:70d:b0:385:e17a:ce6f with SMTP id ffacd0b85a97d-385fd3e9d2fmr6051925f8f.24.1733317053279; Wed, 04 Dec 2024 04:57:33 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 1/7] target/riscv: Remove obsolete sfence.vm instruction Date: Wed, 4 Dec 2024 17:56:39 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-1-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317105473116600 Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis Reviewed-by: Jason Chien --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.c.inc | 5 ----- 2 files changed, 6 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e9139ec1b9cfdb2dc5029dd28430933a2b4e1442..a2b4c0ddd47ad9464b4b180fb19= e6a3b64dbe4e5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -119,7 +119,6 @@ sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index ecd3b8b2c9e6c698f63c9bd3b3e5758426fcfe63..0bdfa9a0ed3313223ce9032fb24= 484c3887cddf9 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -127,8 +127,3 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfe= nce_vma *a) #endif return false; } - -static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) -{ - return false; -} --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317114; cv=none; d=zohomail.com; s=zohoarc; b=jlUm56Cn14hvw4evlf2WwNdCEE13H1EuTc2iy9QL6fJZKS+Er2vv9P8tiiW/HBmlIrd+ffJFiwRo4MJezv+7lMaCtDv8DR4HEo6Kcuq+ndxFGpyD9Q/I/T3hGobJiFdj8zyGqpQ1+jYOFs5QegKm2b7JbFwbxquedA+oddd58y0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317114; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dKK0HxgyWErZpULPkOBeN+5cbb09ulxZHM3ugRtmLQo=; b=UbqskfuumRPBAHOHOVNr6zWZk0nerNSAAY+mvXnh6lJKc8XL7QIYh65y0VlW4JPlCD3t+9FK1dOmLlLoOWIg8fWaO/lHPGlsqCEX5B7S5ZUewqKhNNBMLsy3bIuovZIKNQ1Hc/h/akQz545r0C75hyFSCenKSuOYhUB0mKkCVXs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317114700526.5146125499614; Wed, 4 Dec 2024 04:58:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxD-00089f-EA; Wed, 04 Dec 2024 07:58:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIown-0007zN-42 for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:41 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIowl-0007t1-AX for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:40 -0500 Received: by mail-wm1-x341.google.com with SMTP id 5b1f17b1804b1-434a45f05feso82141205e9.3 for ; Wed, 04 Dec 2024 04:57:38 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317057; x=1733921857; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dKK0HxgyWErZpULPkOBeN+5cbb09ulxZHM3ugRtmLQo=; b=HC7MrqIzZbuAo1Ez+JgSLRdRu+RQJwwUWsf6Fxf4CeXHK2935SloRwUuym36f4diHR /akd0eZ434YIUp39UW6s49fe6x7ICpnVCtf4YUCtF62P+MkIOhiOP+RKptKvfEtN7bcF 14ENDrj6gweRA0nLaYeuTwQNKL3Rv9jcb0EUbyL1E6k7aMwYD1ri+VtAWuk5Z54ofs49 TQ0NCagP+phNnhTFtV4BOW8yh87RHDcV5bmnlwEqDYaV9v9Qm2cDBMyhyBll/6bj465i ySJ4YL9ve0tuAWxOxLXIOlesqHHi0TgsaWrK2kfBZw8X5bsxTlvr6T53INaRiWLya2en 0E+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317057; x=1733921857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dKK0HxgyWErZpULPkOBeN+5cbb09ulxZHM3ugRtmLQo=; b=v8+z8MirsqewjEu6TVl6gkN9C+C3NQkOZxr44J2o3HO4QIR3FE5F8H1HkFWtZKAZWY RqIAAMehYN9AH7dJrs301xhbOlWK+bXpq7NL8LzZ7mT/jcddX2KEF0kAg+zy9R0kVU0e 2jqHajKoo8o3PdKZ4YNRT+XTiDT7533nHTtlipwzGed06PnV6rMwXn7Uu3t/Q7rQsbyW yNfITub7XmBEmr28vnC0uC3/jGacpEEAg2duj48K8pPJHOL9kEBqoe3Oq2Uq+g3T01dx pby6DNzy1qLDZDnkuc8LPbYSl22Y+lyX27CU+4TBlRMfq+brWdd5bwQnfal7O9GT8CCA glxA== X-Forwarded-Encrypted: i=1; AJvYcCWFTOZ7w1BvnBHM03SM1l+EWRkOQ4o+0L8YblccYIdP+weexMm2Hx2jwjkM7T+ns4PL0knQnql9Q5X+@nongnu.org X-Gm-Message-State: AOJu0YzO7NZaaK7rOy9hLN4/YFkHbXvpKCx0lWXeFyR+Hku4AwETHG8x rMG24wgrbXaFZ6xEFqWTMlO7ihPmXXVhJkweC66tydMVRaAVsMp1q3UtLSeDPT0= X-Gm-Gg: ASbGncvy2h9YKZQm+WxUd4VrgSbMhI3ETsZUeJ21mLVbmoapvVuUQHvprV3oNHhRtjR ++SAny+2HBJ/tuIh83LmFkIH2VSVf2dRjZditQMVxhD97NR/1o7ull0neUTjgnAIt6rNCHIe1vX LXugmz+xVWNPTC5M4NxmX8rMfNj43oLuJzvL9jDVe70YNP5XSM22H53tRowJ3iSxsH0NfgUWKwW lJcg279v/aybVtFn9Gp7jc+Y/toqPf+9pIuGfc1wvp+nEgVfh399hgU5dPZH0Lmh42NnDHUsVny wrxs+A== X-Google-Smtp-Source: AGHT+IFUHXj7aFuWfolDkK33VgorI5QZ3Xut0WWHc0WQ/V7UWP3JtoLZVMo1xKnTFCJWPfmC43xvqQ== X-Received: by 2002:a05:6000:2c6:b0:385:ebaf:3824 with SMTP id ffacd0b85a97d-385fd3f2d22mr6762977f8f.27.1733317057126; Wed, 04 Dec 2024 04:57:37 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 2/7] target/riscv: Add Control Transfer Records CSR definitions. Date: Wed, 4 Dec 2024 17:56:40 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-2-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x341.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317117103116600 The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_r= c5 Signed-off-by: Rajnesh Kanwal Acked-by: Alistair Francis --- target/riscv/cpu_bits.h | 94 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 94 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4ac065ac5e5a688d5ec9bbb8288c3deb82f05314..0cf6ef133ce9565f4a19e99f3cf= d1d73da77f47a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -247,6 +247,17 @@ #define CSR_SIEH 0x114 #define CSR_SIPH 0x154 =20 +/* Machine-Level Control transfer records CSRs */ +#define CSR_MCTRCTL 0x34e + +/* Supervisor-Level Control transfer records CSRs */ +#define CSR_SCTRCTL 0x14e +#define CSR_SCTRSTATUS 0x14f +#define CSR_SCTRDEPTH 0x15f + +/* VS-Level Control transfer records CSRs */ +#define CSR_VSCTRCTL 0x24e + /* Hpervisor CSRs */ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -344,6 +355,7 @@ #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) +#define SMSTATEEN0_CTR (1ULL << 54) #define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) @@ -877,6 +889,88 @@ typedef enum RISCVException { #define UMTE_U_PM_INSN U_PM_INSN #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) =20 +/* CTR control register commom fields */ +#define XCTRCTL_U BIT_ULL(0) +#define XCTRCTL_S BIT_ULL(1) +#define XCTRCTL_RASEMU BIT_ULL(7) +#define XCTRCTL_STE BIT_ULL(8) +#define XCTRCTL_BPFRZ BIT_ULL(11) +#define XCTRCTL_LCOFIFRZ BIT_ULL(12) +#define XCTRCTL_EXCINH BIT_ULL(33) +#define XCTRCTL_INTRINH BIT_ULL(34) +#define XCTRCTL_TRETINH BIT_ULL(35) +#define XCTRCTL_NTBREN BIT_ULL(36) +#define XCTRCTL_TKBRINH BIT_ULL(37) +#define XCTRCTL_INDCALLINH BIT_ULL(40) +#define XCTRCTL_DIRCALLINH BIT_ULL(41) +#define XCTRCTL_INDJMPINH BIT_ULL(42) +#define XCTRCTL_DIRJMPINH BIT_ULL(43) +#define XCTRCTL_CORSWAPINH BIT_ULL(44) +#define XCTRCTL_RETINH BIT_ULL(45) +#define XCTRCTL_INDLJMPINH BIT_ULL(46) +#define XCTRCTL_DIRLJMPINH BIT_ULL(47) + +#define XCTRCTL_MASK (XCTRCTL_U | XCTRCTL_S | XCTRCTL_RASEMU | = \ + XCTRCTL_STE | XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ | = \ + XCTRCTL_EXCINH | XCTRCTL_INTRINH | XCTRCTL_TRETINH |= \ + XCTRCTL_NTBREN | XCTRCTL_TKBRINH | XCTRCTL_INDCALLIN= H | \ + XCTRCTL_DIRCALLINH | XCTRCTL_INDJMPINH | = \ + XCTRCTL_DIRJMPINH | XCTRCTL_CORSWAPINH | = \ + XCTRCTL_RETINH | XCTRCTL_INDLJMPINH | XCTRCTL_DIRLJM= PINH) + +#define XCTRCTL_INH_START 32U + +/* CTR mctrctl bits */ +#define MCTRCTL_M BIT_ULL(2) +#define MCTRCTL_MTE BIT_ULL(9) + +#define MCTRCTL_MASK (XCTRCTL_MASK | MCTRCTL_M | MCTRCTL_MTE) +#define SCTRCTL_MASK XCTRCTL_MASK +#define VSCTRCTL_MASK XCTRCTL_MASK + +/* sctrstatus CSR bits. */ +#define SCTRSTATUS_WRPTR_MASK 0xFF +#define SCTRSTATUS_FROZEN BIT(31) +#define SCTRSTATUS_MASK (SCTRSTATUS_WRPTR_MASK | SCTRSTATUS_FR= OZEN) + +/* sctrdepth CSR bits. */ +#define SCTRDEPTH_MASK 0x7 +#define SCTRDEPTH_MIN 0U /* 16 Entries. */ +#define SCTRDEPTH_MAX 4U /* 256 Entries. */ + +#define CTR_ENTRIES_FIRST 0x200 +#define CTR_ENTRIES_LAST 0x2ff + +#define CTRSOURCE_VALID BIT(0) +#define CTRTARGET_MISP BIT(0) + +#define CTRDATA_TYPE_MASK 0xF +#define CTRDATA_CCV BIT(15) +#define CTRDATA_CCM_MASK 0xFFF0000 +#define CTRDATA_CCE_MASK 0xF0000000 + +#define CTRDATA_MASK (CTRDATA_TYPE_MASK | CTRDATA_CCV | \ + CTRDATA_CCM_MASK | CTRDATA_CCE_MASK) + +typedef enum CTRType { + CTRDATA_TYPE_NONE =3D 0, + CTRDATA_TYPE_EXCEPTION =3D 1, + CTRDATA_TYPE_INTERRUPT =3D 2, + CTRDATA_TYPE_EXCEP_INT_RET =3D 3, + CTRDATA_TYPE_NONTAKEN_BRANCH =3D 4, + CTRDATA_TYPE_TAKEN_BRANCH =3D 5, + CTRDATA_TYPE_RESERVED_0 =3D 6, + CTRDATA_TYPE_RESERVED_1 =3D 7, + CTRDATA_TYPE_INDIRECT_CALL =3D 8, + CTRDATA_TYPE_DIRECT_CALL =3D 9, + CTRDATA_TYPE_INDIRECT_JUMP =3D 10, + CTRDATA_TYPE_DIRECT_JUMP =3D 11, + CTRDATA_TYPE_CO_ROUTINE_SWAP =3D 12, + CTRDATA_TYPE_RETURN =3D 13, + CTRDATA_TYPE_OTHER_INDIRECT_JUMP =3D 14, + CTRDATA_TYPE_OTHER_DIRECT_JUMP =3D 15, +} CTRType; + /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317150; cv=none; d=zohomail.com; s=zohoarc; b=T6FkDpV38McAtT5cLGGAAfh5B1NJ3nUE9ECGsyLefcb9hWiY8VFzVOE0agaOUe+oP4QB+gxRNBk/9eeUluapXeelU7rptSCukL/fRdYyEfYnCqyj7ezi9U6P6YbSc2LP1xUxQAP0dyWnbvhX/jvrmQWOtElr3C/BGGt/jKVxZhA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317150; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HFBSeg/00KOb1P9GKLTrphr5EfKkf3HOkFUqzsFQb00=; b=Mw5NXajItFi6LYDA8/ECwEajvaoGQy71wQNJdYEJrgky5yu90nFqa7ljUtyXaNgK8i2+fnWTbhreDsYTAnIgrmBUabBgVtV8Pz/IhLgAKH90qYQ83Uhd/S7PGtfihOwwO9WD2T5AanNxoGo8csQ+I8OEb/w/lKVlBzgCY0VQ6gA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317150172127.30512165117398; Wed, 4 Dec 2024 04:59:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxF-0008BZ-Ot; Wed, 04 Dec 2024 07:58:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIows-000808-EQ for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:52 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIowo-0008Ag-Aw for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:44 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-434aa222d96so82331165e9.0 for ; Wed, 04 Dec 2024 04:57:41 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317061; x=1733921861; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HFBSeg/00KOb1P9GKLTrphr5EfKkf3HOkFUqzsFQb00=; b=MGpaBX/829Nc2mS19SM2XuDXXxf+hwoCv6kN93+YzDnrMZV4On/xYIJU/jPT2HzjVO CJandalG+dx7bgEVkHvzQcRX7pP/64qQozvpw/9eE1UanQoXjdGkpuBDZ0q+mFkfQY09 c8rFVHMMhgqwy4L46RdG/mx97hvyrMTai+Wr7RI4QlVDOwOYxtcuBfvnLzc3XVd+k4kS NRCBiJdpIf1SPEsO8BxIaiGEom0tLAi5x/IdbgLz9fCMuKFBdEkXKk16bsRKTq7Woonk oeBB+MOKLIkXz5Y1vwtRlOVYkw6iLZ3VPLRX/IXSD2pH5GUCpxzYAG86sv6zaz+QY6sD kWeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317061; x=1733921861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HFBSeg/00KOb1P9GKLTrphr5EfKkf3HOkFUqzsFQb00=; b=Vb082YL+PRIXnbOan9BAtB5cg/YendoM4Eud6t6/V0z2Li8L1Zf/czHny23ryN+aoL bRCmfNfue07ld3QFAPP2/+SHtfyiSh1zCsrTImKgLOzkHOrhTnrWK1CKBnZVxDr/05bN zKs7iKu+w19fe4H6ussJLJHoG+5H5IY9evrrhbgy9fgU8ZgUnY+9RQfS0BvmBgjQm2fQ gyz9KfTiKl/gWwViCey440gJutOLUcKKdAtQJ7SMi7Q3I1j/JVGGOOjjmYzzQ2xybKeQ SnKfRKvFVFZgPNp0SGTzP/h0tyfsm5s8PN6oDmOf7A91jbrtudgOQDbUhBSYkptCvbjQ iPLg== X-Forwarded-Encrypted: i=1; AJvYcCVPl9qoer82n40T9gCfzaxuV/lQtlYkAwPmfx/lfGesSkuuH3USHJPokTgB6ZR+CFshGHZyVA/OAojK@nongnu.org X-Gm-Message-State: AOJu0Ywrs+xI1oXAAayjkLqjvNQ+tfQToNd+dqM/8xHKhm4mnvHIkbKH LssJ8QcCIo4haLpZw9SdTQQWUOuf4Z0DIgjN+/6I0kZ/M5XYG2kSf4G1xhjLx8A= X-Gm-Gg: ASbGncs++05RKGPubW4+dhtq2lTFKavwDZO8I/9f1Rj/mLy9v6L/HkC9JnVRY57N3CG FzqG9gD+V0jbroiP99yTjniuq490NUh3R8eFcrW/bpSleerNcrPtqpe5gIFEe8KzC24ooclU7Ww Ha3+S1JcZvncwV5jAChbI0jwMeJuSWPMNHJWadRamAOCgOK+/alr9IvMchPLI2ND8QxOYQJMgYH fH5J3O7lTRAyr8EZqheMSrgZFqVJlnJlxMqgVHChJoWCTp8EeK0mmau4OgA5h5jCdfsmAmQ9O0C m8uV+g== X-Google-Smtp-Source: AGHT+IGtCkJHHKwuxrbOYd7h8pASExTS/9+yJbRakiBxDEaDD4p2tXg9Tfoxh/YnuHegzdJ+ns/kbw== X-Received: by 2002:a05:600c:3ca7:b0:434:a923:9321 with SMTP id 5b1f17b1804b1-434d09b2e5emr61006995e9.5.1733317060605; Wed, 04 Dec 2024 04:57:40 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 3/7] target/riscv: Add support for Control Transfer Records extension CSRs. Date: Wed, 4 Dec 2024 17:56:41 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-3-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317151189116600 This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 144 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 151 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 903268626374474306f0e0259f37128326b354d4..da14ac2f874b81d3f01bc31b006= 4d020f2dbdf61 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -305,6 +305,11 @@ struct CPUArchState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + uint64_t mctrctl; + uint32_t sctrdepth; + uint32_t sctrstatus; + uint64_t vsctrctl; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ae2b019703fe4849eb7f264b4d90743d4c013b86..e365a368d71a695b1b99c3b6ae3= 30347143d3422 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -130,6 +130,8 @@ struct RISCVCPUConfig { bool ext_zvfhmin; bool ext_smaia; bool ext_ssaia; + bool ext_smctr; + bool ext_ssctr; bool ext_sscofpmf; bool ext_smepmp; bool rvv_ta_all_1s; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 31ea8b8ec20db5a5af23e829757cccaafc02e2da..7e03065d3dcd8713e2cadae3017= ed355c9f9bf10 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -651,6 +651,48 @@ static RISCVException pointer_masking(CPURISCVState *e= nv, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +/* + * M-mode: + * Without ext_smctr raise illegal inst excep. + * Otherwise everything is accessible to m-mode. + * + * S-mode: + * Without ext_ssctr or mstateen.ctr raise illegal inst excep. + * Otherwise everything other than mctrctl is accessible. + * + * VS-mode: + * Without ext_ssctr or mstateen.ctr raise illegal inst excep. + * Without hstateen.ctr raise virtual illegal inst excep. + * Otherwise allow sctrctl (vsctrctl), sctrstatus, 0x200-0x2ff entry range. + * Always raise illegal instruction exception for sctrdepth. + */ +static RISCVException ctr_mmode(CPURISCVState *env, int csrno) +{ + /* Check if smctr-ext is present */ + if (riscv_cpu_cfg(env)->ext_smctr) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + +static RISCVException ctr_smode(CPURISCVState *env, int csrno) +{ + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); + + if (!cfg->ext_smctr && !cfg->ext_ssctr) { + return RISCV_EXCP_ILLEGAL_INST; + } + + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_CTR); + if (ret =3D=3D RISCV_EXCP_NONE && csrno =3D=3D CSR_SCTRDEPTH && + env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return ret; +} + static RISCVException aia_hmode(CPURISCVState *env, int csrno) { int ret; @@ -3160,6 +3202,10 @@ static RISCVException write_mstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); } =20 + if (riscv_cpu_cfg(env)->ext_ssctr) { + wr_mask |=3D SMSTATEEN0_CTR; + } + return write_mstateen(env, csrno, wr_mask, new_val); } =20 @@ -3199,6 +3245,10 @@ static RISCVException write_mstateen0h(CPURISCVState= *env, int csrno, wr_mask |=3D SMSTATEEN0_P1P13; } =20 + if (riscv_cpu_cfg(env)->ext_ssctr) { + wr_mask |=3D SMSTATEEN0_CTR; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } =20 @@ -3253,6 +3303,10 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); } =20 + if (riscv_cpu_cfg(env)->ext_ssctr) { + wr_mask |=3D SMSTATEEN0_CTR; + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 @@ -3292,6 +3346,10 @@ static RISCVException write_hstateen0h(CPURISCVState= *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (riscv_cpu_cfg(env)->ext_ssctr) { + wr_mask |=3D SMSTATEEN0_CTR; + } + return write_hstateenh(env, csrno, wr_mask, new_val); } =20 @@ -4005,6 +4063,86 @@ static RISCVException write_satp(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_= mask) +{ + uint64_t mask =3D wr_mask & SCTRDEPTH_MASK; + + if (ret_val) { + *ret_val =3D env->sctrdepth; + } + + env->sctrdepth =3D (env->sctrdepth & ~mask) | (new_val & mask); + + /* Correct depth. */ + if (mask) { + uint64_t depth =3D get_field(env->sctrdepth, SCTRDEPTH_MASK); + + if (depth > SCTRDEPTH_MAX) { + depth =3D SCTRDEPTH_MAX; + env->sctrdepth =3D set_field(env->sctrdepth, SCTRDEPTH_MASK, d= epth); + } + + /* Update sctrstatus.WRPTR with a legal value */ + depth =3D 16 << depth; + env->sctrstatus =3D + env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1)); + } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_sctrstatus(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr= _mask) +{ + uint32_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); + uint32_t mask =3D wr_mask & SCTRSTATUS_MASK; + + if (ret_val) { + *ret_val =3D env->sctrstatus; + } + + env->sctrstatus =3D (env->sctrstatus & ~mask) | (new_val & mask); + + /* Update sctrstatus.WRPTR with a legal value */ + env->sctrstatus =3D env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth= - 1)); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_xctrctl(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_= mask) +{ + uint64_t csr_mask, mask =3D wr_mask; + uint64_t *ctl_ptr =3D &env->mctrctl; + + if (csrno =3D=3D CSR_MCTRCTL) { + csr_mask =3D MCTRCTL_MASK; + } else if (csrno =3D=3D CSR_SCTRCTL && !env->virt_enabled) { + csr_mask =3D SCTRCTL_MASK; + } else { + /* + * This is for csrno =3D=3D CSR_SCTRCTL and env->virt_enabled =3D= =3D true + * or csrno =3D=3D CSR_VSCTRCTL. + */ + csr_mask =3D VSCTRCTL_MASK; + ctl_ptr =3D &env->vsctrctl; + } + + mask &=3D csr_mask; + + if (ret_val) { + *ret_val =3D *ctl_ptr & csr_mask; + } + + *ctl_ptr =3D (*ctl_ptr & ~mask) | (new_val & mask); + + return RISCV_EXCP_NONE; +} + static RISCVException read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) { @@ -5984,6 +6122,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, write_spmbase = }, =20 + [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, + [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, + [CSR_VSCTRCTL] =3D { "vsctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, + [CSR_SCTRDEPTH] =3D { "sctrdepth", ctr_smode, NULL, NULL, rmw_sctrd= epth }, + [CSR_SCTRSTATUS] =3D { "sctrstatus", ctr_smode, NULL, NULL, rmw_sctrs= tatus }, + /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317159; cv=none; d=zohomail.com; s=zohoarc; b=CXPn2sytwAibvJ2M8qJVJ7q9NUzIgoDnMHHwV5jI11CsOnHvvvdl9fFg52n3qSzenwj7uI6pGP20UGKGsYtujSu5X+EJ6sRRnC5yNg2hw7MBC4uJ85YmgBTFvLhcPqKvbXhz9EysfofCjuSiYVosYNJWzDcziTWLV1a+CEFCE3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317159; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WnDf7QI/RLhzrBa9OwVRAWfNBRyfJIuIUVfxmyQq/YM=; b=bPcz+rIpm6qCQvTp8w83mgOSbaQmMnKxV3ctZakkVGA30LxBUgHM+6YZDJgEGo0vpbICB91RB3vv41GuavJP76SPq3yQZpYi8hBVI23e9aGsdrKwW7QPT5Lw3ZdOM3JXcCIr7h85JubsaYBkWbO9/y7bOl5N5apO2Hox4FHcht8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317159757703.8274260161536; Wed, 4 Dec 2024 04:59:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxI-0008EN-VR; Wed, 04 Dec 2024 07:58:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIoww-00080c-Rw for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:52 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIows-0008Tr-5k for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:48 -0500 Received: by mail-wr1-x444.google.com with SMTP id ffacd0b85a97d-385dece873cso2773283f8f.0 for ; Wed, 04 Dec 2024 04:57:44 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317064; x=1733921864; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WnDf7QI/RLhzrBa9OwVRAWfNBRyfJIuIUVfxmyQq/YM=; b=OvWgPRLThaw76imqANQUMSn473O52td9OSejPc1OygLd73UvTanktVShGy7TgQGB+e FqOk6+n4072m4lletq9FKq1NRppNh5zC6QM0x757CJe3tKMQaNBCI0tCUWT/Xw9J01X6 oO/BDafR/UxUJ3QMX+RMtYdtimD5j0+ZFBoWkIasFakC8iUCvfVChnbLT3H2n/lEqOjh DPunCaaksNpYvV7AUqR5coXPica5O6cYKOW3omhZLJzXvS6P0c9cXmil34ZMGwax6vHZ 3o4rXQB39hysexDhUq8Pcvnf2f/kZNHbitxHW47WVztydJ8oxzL0fZKDG0dF40XLTgSN e8JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317064; x=1733921864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WnDf7QI/RLhzrBa9OwVRAWfNBRyfJIuIUVfxmyQq/YM=; b=tRi0df79BOBGFghRPthFBtCUAYPbcGiDwn5Jm3pokF+DywNAQnw8rix+glMzt/fbGf 76aesCnMBlC18M9GM/wdQbo76wlGsyAaLQCS0J9ZrebrWfO7KRwLG/sc0GCkWyl8ao5k cpSauiLln7D3xOedQ4hNLyVhMH5dr/joWDflOmTDjddFm3k9NQpSFNMn4swC1Ki8iJsy RXjnx3o+W7ykru8TFk7H3mHRYN4yZMXdMEZBgx4HTi9JGiMUekvgpPf7zcd6V6/1UbZ1 VqZBBUX8WMyfUgCt0cu1ehdpd4KSo2lFFcQsl2eIhZ0VSWvHGPM1+AsHUgAVHbZ3bH+P L8ZQ== X-Forwarded-Encrypted: i=1; AJvYcCVXTYcVd2iHzfUj2wZo58xNRMMKbBiIwupC8xjravP5m9e0/2nbTl96WnMSPbE8siA1vCqgZ5UTmfTU@nongnu.org X-Gm-Message-State: AOJu0YyR0VC5SHEhgGJNNJ8aIYb0v/QfEdnxDVuKwbi2cKjcLnQ5QwCJ 1EkKWG29K3bzFlQtM5dUEVRXAVhhkyWgXqAcCchEGfl8NCh6OrPHFxvmw2Yaxro= X-Gm-Gg: ASbGncuS94J+Hwe2Luqg90oR6HSARkWnlSro9G/9vwHXcWEboOaSGqsdf5za0+GDT/B +mTZnM/w5fKqrGNgxxIgJ/w5sxMa98RlP1lgE5eL8XVZcwTVspxiIl5fJHXyyx3NJjPv16KRGUT QFg3Htcq4QlQkKSXeS0O4TriP4aVtlSFCN8nLs/xppPSBDFbE5Lo7H/Jr8zwNWuQQbLpwMitX2M 4xHjti48Ptskqkvhr8FM1m5li+ADygQ/GPI58+yiF8SMwaQJKEh86/JborOsSdmHQvEp6alZqTl bYmMKA== X-Google-Smtp-Source: AGHT+IF3skSmAkZWjpjbIkPQj48IAZvP6vXMwY8KQ3NYz59yG5qvkSEH94LVOM7f1Cl0QKHtv6Qu0g== X-Received: by 2002:a05:6000:1acc:b0:385:e30a:e0f7 with SMTP id ffacd0b85a97d-38607ace5f0mr3553121f8f.22.1733317063834; Wed, 04 Dec 2024 04:57:43 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 4/7] target/riscv: Add support to record CTR entries. Date: Wed, 4 Dec 2024 17:56:42 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-4-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x444.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317161900116600 This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 7 + target/riscv/cpu_helper.c | 259 +++++++++++++++++++++= ++++ target/riscv/helper.h | 5 +- target/riscv/insn_trans/trans_privileged.c.inc | 6 +- target/riscv/insn_trans/trans_rvi.c.inc | 70 +++++++ target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++ target/riscv/op_helper.c | 23 ++- target/riscv/translate.c | 44 +++++ 8 files changed, 430 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index da14ac2f874b81d3f01bc31b0064d020f2dbdf61..f39ca48d37332c4e5907ca87040= de420f78df2e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -310,6 +310,10 @@ struct CPUArchState { uint32_t sctrstatus; uint64_t vsctrctl; =20 + uint64_t ctr_src[16 << SCTRDEPTH_MAX]; + uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; + uint64_t ctr_data[16 << SCTRDEPTH_MAX]; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; @@ -607,6 +611,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int= index, uint64_t bit); =20 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en); =20 +void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, + enum CTRType type, target_ulong prev_priv, bool prev_virt); + void riscv_translate_init(void); G_NORETURN void riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69eabaf0e395fc7c78868640a4216573ee..dbdad4e29d7de0713f7530c46e9= fab03d3c459a4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -771,6 +771,247 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env= , uint32_t priv, } } =20 +static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask, + bool virt) +{ + uint64_t ctl =3D virt ? env->vsctrctl : env->mctrctl; + + assert((freeze_mask & (~(XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ))) =3D=3D 0); + + if (ctl & freeze_mask) { + env->sctrstatus |=3D SCTRSTATUS_FROZEN; + } +} + +static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) +{ + switch (priv) { + case PRV_M: + return MCTRCTL_M; + case PRV_S: + if (virt) { + return XCTRCTL_S; + } + return XCTRCTL_S; + case PRV_U: + if (virt) { + return XCTRCTL_U; + } + return XCTRCTL_U; + } + + g_assert_not_reached(); +} + +static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv, + bool virt) +{ + switch (priv) { + case PRV_M: + return env->mctrctl; + case PRV_S: + case PRV_U: + if (virt) { + return env->vsctrctl; + } + return env->mctrctl; + } + + g_assert_not_reached(); +} + +/* + * This function assumes that src privilege and target privilege are not s= ame + * and src privilege is less than target privilege. This includes the virt= ual + * state as well. + */ +static bool riscv_ctr_check_xte(CPURISCVState *env, target_long src_prv, + bool src_virt) +{ + target_long tgt_prv =3D env->priv; + bool res =3D true; + + /* + * VS and U mode are same in terms of xTE bits required to record an + * external trap. See 6.1.2. External Traps, table 8 External Trap Ena= ble + * Requirements. This changes VS to U to simplify the logic a bit. + */ + if (src_virt && src_prv =3D=3D PRV_S) { + src_prv =3D PRV_U; + } else if (env->virt_enabled && tgt_prv =3D=3D PRV_S) { + tgt_prv =3D PRV_U; + } + + /* VU mode is an outlier here. */ + if (src_virt && src_prv =3D=3D PRV_U) { + res &=3D !!(env->vsctrctl & XCTRCTL_STE); + } + + switch (src_prv) { + case PRV_U: + if (tgt_prv =3D=3D PRV_U) { + break; + } + res &=3D !!(env->mctrctl & XCTRCTL_STE); + /* fall-through */ + case PRV_S: + if (tgt_prv =3D=3D PRV_S) { + break; + } + res &=3D !!(env->mctrctl & MCTRCTL_MTE); + /* fall-through */ + case PRV_M: + break; + } + + return res; +} + +/* + * Special cases for traps and trap returns: + * + * 1- Traps, and trap returns, between enabled modes are recorded as norma= l. + * 2- Traps from an inhibited mode to an enabled mode, and trap returns fr= om an + * enabled mode back to an inhibited mode, are partially recorded. In such + * cases, the PC from the inhibited mode (source PC for traps, and target = PC + * for trap returns) is 0. + * + * 3- Trap returns from an inhibited mode to an enabled mode are not recor= ded. + * Traps from an enabled mode to an inhibited mode, known as external trap= s, + * receive special handling. + * By default external traps are not recorded, but a handshake mechanism e= xists + * to allow partial recording. Software running in the target mode of the= trap + * can opt-in to allowing CTR to record traps into that mode even when the= mode + * is inhibited. The MTE, STE, and VSTE bits allow M-mode, S-mode, and VS= -mode, + * respectively, to opt-in. When an External Trap occurs, and xTE=3D1, suc= h that + * x is the target privilege mode of the trap, will CTR record the trap. I= n such + * cases, the target PC is 0. + */ +/* + * CTR arrays are implemented as circular buffers and new entry is stored = at + * sctrstatus.WRPTR, but they are presented to software as moving circular + * buffers. Which means, software get's the illusion that whenever a new e= ntry + * is added the whole buffer is moved by one place and the new entry is ad= ded at + * the start keeping new entry at idx 0 and older ones follow. + * + * Depth =3D 16. + * + * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F] + * WRPTR W + * entry 7 6 5 4 3 2 1 0 F E D C B A 9 8 + * + * When a new entry is added: + * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F] + * WRPTR W + * entry 8 7 6 5 4 3 2 1 0 F E D C B A 9 + * + * entry here denotes the logical entry number that software can access + * using ctrsource, ctrtarget and ctrdata registers. So xiselect 0x200 + * will return entry 0 i-e buffer[8] and 0x201 will return entry 1 i-e + * buffer[7]. Here is how we convert entry to buffer idx. + * + * entry =3D isel - CTR_ENTRIES_FIRST; + * idx =3D (sctrstatus.WRPTR - entry - 1) & (depth - 1); + */ +void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, + enum CTRType type, target_ulong src_priv, bool src_virt) +{ + bool tgt_virt =3D env->virt_enabled; + uint64_t src_mask =3D riscv_ctr_priv_to_mask(src_priv, src_virt); + uint64_t tgt_mask =3D riscv_ctr_priv_to_mask(env->priv, tgt_virt); + uint64_t src_ctrl =3D riscv_ctr_get_control(env, src_priv, src_virt); + uint64_t tgt_ctrl =3D riscv_ctr_get_control(env, env->priv, tgt_virt); + uint64_t depth, head; + bool ext_trap =3D false; + + /* + * Return immediately if both target and src recording is disabled or = if + * CTR is in frozen state. + */ + if ((!(src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) || + env->sctrstatus & SCTRSTATUS_FROZEN) { + return; + } + + /* + * With RAS Emul enabled, only allow Indirect, direct calls, Function + * returns and Co-routine swap types. + */ + if (tgt_ctrl & XCTRCTL_RASEMU && + type !=3D CTRDATA_TYPE_INDIRECT_CALL && + type !=3D CTRDATA_TYPE_DIRECT_CALL && + type !=3D CTRDATA_TYPE_RETURN && + type !=3D CTRDATA_TYPE_CO_ROUTINE_SWAP) { + return; + } + + if (type =3D=3D CTRDATA_TYPE_EXCEPTION || type =3D=3D CTRDATA_TYPE_INT= ERRUPT) { + /* Case 2 for traps. */ + if (!(src_ctrl & src_mask)) { + src =3D 0; + } else if (!(tgt_ctrl & tgt_mask)) { + /* Check if target priv-mode has allowed external trap recordi= ng. */ + if (!riscv_ctr_check_xte(env, src_priv, src_virt)) { + return; + } + + ext_trap =3D true; + dst =3D 0; + } + } else if (type =3D=3D CTRDATA_TYPE_EXCEP_INT_RET) { + /* + * Case 3 for trap returns. Trap returns from inhibited mode are = not + * recorded. + */ + if (!(src_ctrl & src_mask)) { + return; + } + + /* Case 2 for trap returns. */ + if (!(tgt_ctrl & tgt_mask)) { + dst =3D 0; + } + } + + /* Ignore filters in case of RASEMU mode or External trap. */ + if (!(tgt_ctrl & XCTRCTL_RASEMU) && !ext_trap) { + /* + * Check if the specific type is inhibited. Not taken branch filte= r is + * an enable bit and needs to be checked separatly. + */ + bool check =3D tgt_ctrl & BIT_ULL(type + XCTRCTL_INH_START); + if ((type =3D=3D CTRDATA_TYPE_NONTAKEN_BRANCH && !check) || + (type !=3D CTRDATA_TYPE_NONTAKEN_BRANCH && check)) { + return; + } + } + + head =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); + + depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); + if (tgt_ctrl & XCTRCTL_RASEMU && type =3D=3D CTRDATA_TYPE_RETURN) { + head =3D (head - 1) & (depth - 1); + + env->ctr_src[head] &=3D ~CTRSOURCE_VALID; + env->sctrstatus =3D + set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head); + return; + } + + /* In case of Co-routine SWAP we overwrite latest entry. */ + if (tgt_ctrl & XCTRCTL_RASEMU && type =3D=3D CTRDATA_TYPE_CO_ROUTINE_S= WAP) { + head =3D (head - 1) & (depth - 1); + } + + env->ctr_src[head] =3D src | CTRSOURCE_VALID; + env->ctr_dst[head] =3D dst & ~CTRTARGET_MISP; + env->ctr_data[head] =3D set_field(0, CTRDATA_TYPE_MASK, type); + + head =3D (head + 1) & (depth - 1); + + env->sctrstatus =3D set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, = head); +} + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); @@ -1806,10 +2047,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + const bool prev_virt =3D env->virt_enabled; + const target_ulong prev_priv =3D env->priv; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + target_ulong src; int sxlen =3D 0; int mxlen =3D 0; =20 @@ -1960,6 +2204,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S, virt); + + src =3D env->sepc; } else { /* handle the trap in M-mode */ /* save elp status */ @@ -1997,6 +2243,19 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M, virt); + src =3D env->mepc; + } + + if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) { + if (async && cause =3D=3D IRQ_PMU_OVF) { + riscv_ctr_freeze(env, XCTRCTL_LCOFIFRZ, virt); + } else if (!async && cause =3D=3D RISCV_EXCP_BREAKPOINT) { + riscv_ctr_freeze(env, XCTRCTL_BPFRZ, virt); + } + + riscv_ctr_add_entry(env, src, env->pc, + async ? CTRDATA_TYPE_INTERRUPT : CTRDATA_TYPE_EXCE= PTION, + prev_priv, prev_virt); } =20 /* diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a4f6138a06afb1e4abc0c838acb283e..065d82d3997b1df46a0ed1b96d3= 3bee13c049fad 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -129,12 +129,13 @@ DEF_HELPER_2(csrr_i128, tl, env, int) DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_1(sret, tl, env) -DEF_HELPER_1(mret, tl, env) +DEF_HELPER_2(sret, tl, env, tl) +DEF_HELPER_2(mret, tl, env, tl) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) +DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 0bdfa9a0ed3313223ce9032fb24484c3887cddf9..a5c2410cfa0779b1a928e7b89bd= 2ee5bb24216e4 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -78,9 +78,10 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); decode_save_opc(ctx, 0); translator_io_start(&ctx->base); - gen_helper_sret(cpu_pc, tcg_env); + gen_helper_sret(cpu_pc, tcg_env, src); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -95,9 +96,10 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); decode_save_opc(ctx, 0); translator_io_start(&ctx->base); - gen_helper_mret(cpu_pc, tcg_env); + gen_helper_mret(cpu_pc, tcg_env, src); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 96c218a9d7875c6419287ac3aa9746251be3f442..fc182e7b18a289e13ad212f10a3= 233aca25fae41 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -93,6 +93,50 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) return true; } =20 +#ifndef CONFIG_USER_ONLY +/* + * Indirect calls + * - jalr x1, rs where rs !=3D x5; + * - jalr x5, rs where rs !=3D x1; + * - c.jalr rs1 where rs1 !=3D x5; + * + * Indirect jumps + * - jalr x0, rs where rs !=3D x1 and rs !=3D x5; + * - c.jr rs1 where rs1 !=3D x1 and rs1 !=3D x5. + * + * Returns + * - jalr rd, rs where (rs =3D=3D x1 or rs =3D=3D x5) and rd !=3D x1 and r= d !=3D x5; + * - c.jr rs1 where rs1 =3D=3D x1 or rs1 =3D=3D x5. + * + * Co-routine swap + * - jalr x1, x5; + * - jalr x5, x1; + * - c.jalr x5. + * + * Other indirect jumps + * - jalr rd, rs where rs !=3D x1, rs !=3D x5, rd !=3D x0, rd !=3D x1 and = rd !=3D x5. + */ +static void helper_ctr_jalr(DisasContext *ctx, arg_jalr *a) +{ + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + TCGv type; + + if ((a->rd =3D=3D 1 && a->rs1 !=3D 5) || (a->rd =3D=3D 5 && a->rs1 != =3D 1)) { + type =3D tcg_constant_tl(CTRDATA_TYPE_INDIRECT_CALL); + } else if (a->rd =3D=3D 0 && a->rs1 !=3D 1 && a->rs1 !=3D 5) { + type =3D tcg_constant_tl(CTRDATA_TYPE_INDIRECT_JUMP); + } else if ((a->rs1 =3D=3D 1 || a->rs1 =3D=3D 5) && (a->rd !=3D 1 && a-= >rd !=3D 5)) { + type =3D tcg_constant_tl(CTRDATA_TYPE_RETURN); + } else if ((a->rs1 =3D=3D 1 && a->rd =3D=3D 5) || (a->rs1 =3D=3D 5 && = a->rd =3D=3D 1)) { + type =3D tcg_constant_tl(CTRDATA_TYPE_CO_ROUTINE_SWAP); + } else { + type =3D tcg_constant_tl(CTRDATA_TYPE_OTHER_INDIRECT_JUMP); + } + + gen_helper_ctr_add_entry(tcg_env, src, cpu_pc, type); +} +#endif + static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { TCGLabel *misaligned =3D NULL; @@ -130,6 +174,12 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } } =20 +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + helper_ctr_jalr(ctx, a); + } +#endif + lookup_and_goto_ptr(ctx); =20 if (misaligned) { @@ -219,6 +269,9 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_SIGN); target_ulong orig_pc_save =3D ctx->pc_save; +#ifndef CONFIG_USER_ONLY + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); +#endif =20 if (get_xl(ctx) =3D=3D MXL_RV128) { TCGv src1h =3D get_gprh(ctx, a->rs1); @@ -231,6 +284,15 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TC= GCond cond) } else { tcg_gen_brcond_tl(cond, src1, src2, l); } + +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + TCGv type =3D tcg_constant_tl(CTRDATA_TYPE_NONTAKEN_BRANCH); + TCGv dest =3D tcg_constant_tl(ctx->base.pc_next + ctx->cur_insn_le= n); + gen_helper_ctr_add_entry(tcg_env, src, dest, type); + } +#endif + gen_goto_tb(ctx, 1, ctx->cur_insn_len); ctx->pc_save =3D orig_pc_save; =20 @@ -243,6 +305,14 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TC= GCond cond) gen_pc_plus_diff(target_pc, ctx, a->imm); gen_exception_inst_addr_mis(ctx, target_pc); } else { +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + TCGv type =3D tcg_constant_tl(CTRDATA_TYPE_TAKEN_BRANCH); + TCGv dest =3D tcg_constant_tl(ctx->base.pc_next + a->imm); + + gen_helper_ctr_add_entry(tcg_env, src, dest, type); + } +#endif gen_goto_tb(ctx, 0, a->imm); } ctx->pc_save =3D -1; diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index cd234ad960724c936b92afb6fd1f3c7c2a37cb80..07b51d9f4d847c4411165b422a8= 43fea65c86d45 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -204,6 +204,13 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bo= ol ret, bool ret_val) if (ret) { TCGv ret_addr =3D get_gpr(ctx, xRA, EXT_SIGN); tcg_gen_mov_tl(cpu_pc, ret_addr); +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + TCGv type =3D tcg_constant_tl(CTRDATA_TYPE_RETURN); + gen_helper_ctr_add_entry(tcg_env, src, cpu_pc, type); + } +#endif tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp =3D DISAS_NORETURN; } @@ -309,6 +316,21 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_ja= lt *a) gen_set_gpr(ctx, xRA, succ_pc); } =20 +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + + if (a->index >=3D 32) { + TCGv type =3D tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL); + gen_helper_ctr_add_entry(tcg_env, src, addr, type); + } else { + TCGv type =3D tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP); + gen_helper_ctr_add_entry(tcg_env, src, addr, type); + } + } +#endif + + tcg_gen_mov_tl(cpu_pc, addr); =20 tcg_gen_lookup_and_goto_ptr(); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b4f191127b6378d4c2dbfd747123f9e..b55b7f3ac3d209d39b16075e79c= 2342b89bdf805 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -259,10 +259,12 @@ void helper_cbo_inval(CPURISCVState *env, target_ulon= g address) =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env) +target_ulong helper_sret(CPURISCVState *env, target_ulong curr_pc) { uint64_t mstatus; target_ulong prev_priv, prev_virt =3D env->virt_enabled; + const target_ulong src_priv =3D env->priv; + const bool src_virt =3D env->virt_enabled; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -318,10 +320,15 @@ target_ulong helper_sret(CPURISCVState *env) } env->mstatus =3D set_field(env->mstatus, MSTATUS_SPELP, 0); =20 + if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) { + riscv_ctr_add_entry(env, curr_pc, retpc, CTRDATA_TYPE_EXCEP_INT_RE= T, + src_priv, src_virt); + } + return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env) +target_ulong helper_mret(CPURISCVState *env, target_ulong curr_pc) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -367,9 +374,21 @@ target_ulong helper_mret(CPURISCVState *env) } env->mstatus =3D set_field(env->mstatus, MSTATUS_MPELP, 0); =20 + if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) { + riscv_ctr_add_entry(env, curr_pc, retpc, CTRDATA_TYPE_EXCEP_INT_RE= T, + PRV_M, false); + } + return retpc; } =20 +void helper_ctr_add_entry(CPURISCVState *env, target_ulong src, + target_ulong dest, target_ulong type) +{ + riscv_ctr_add_entry(env, src, dest, (enum CTRType)type, + env->priv, env->virt_enabled); +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bccaf8e89a650fdc08e866f2edc4f22910e6c328..7c7eb591c1608a2e5a5cba29119= 98e5d7261f381 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -563,6 +563,44 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_n= um, TCGv_i64 t) } } =20 +#ifndef CONFIG_USER_ONLY +/* + * Direct calls + * - jal x1; + * - jal x5; + * - c.jal. + * - cm.jalt. + * + * Direct jumps + * - jal x0; + * - c.j; + * - cm.jt. + * + * Other direct jumps + * - jal rd where rd !=3D x1 and rd !=3D x5 and rd !=3D x0; + */ +static void helper_ctr_jal(DisasContext *ctx, int rd, target_ulong imm) +{ + TCGv dest =3D tcg_constant_tl(ctx->base.pc_next + imm); + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + TCGv type; + + /* + * If rd is x1 or x5 link registers, treat this as direct call otherwi= se + * its a direct jump. + */ + if (rd =3D=3D 1 || rd =3D=3D 5) { + type =3D tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL); + } else if (rd =3D=3D 0) { + type =3D tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP); + } else { + type =3D tcg_constant_tl(CTRDATA_TYPE_OTHER_DIRECT_JUMP); + } + + gen_helper_ctr_add_entry(tcg_env, src, dest, type); +} +#endif + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { TCGv succ_pc =3D dest_gpr(ctx, rd); @@ -577,6 +615,12 @@ static void gen_jal(DisasContext *ctx, int rd, target_= ulong imm) } } =20 +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + helper_ctr_jal(ctx, rd, imm); + } +#endif + gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); gen_set_gpr(ctx, rd, succ_pc); =20 --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317103; cv=none; d=zohomail.com; s=zohoarc; b=WpVv7SIgbD9w/RAV1BHvuRnhr969fWUL115sv0eKIasvJqZ6LDVoDepq5FjAUl99W7/DzNKdHqTfaNDEX0kiHW+cpCfyL3RV1CYFXNhmp7xVmCaxoXtqsttVugKI7ZGfBAKauQVDEhPosEK6D9uAVCrDk91omfHl+WLYaL2zaR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k0BdiPoCW2sPd1Y1VSCMikmuF5uV1Ceplm251HQmWDI=; b=MEqIbB8Va4Bv/b6GSkCZLK+DJyG31L3JZDd/H4RdBSHnvHIBGsCj6x/Sh7T9859lz8C21z8JsE60pvEWJNJXxcfO8lFr5IEoGq3xvTn8Ey7XVKX4atOUDQ3k31jVKAVzPlXFXDheQPMwGF6Mmv3wv8jZrLdwevlzOmVMqYOnX4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317103044456.1151918571145; Wed, 4 Dec 2024 04:58:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxE-0008BA-DG; Wed, 04 Dec 2024 07:58:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIox0-00081T-I2 for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:57 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIoww-0000Af-K3 for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:54 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385e87b25f0so533606f8f.0 for ; Wed, 04 Dec 2024 04:57:48 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317067; x=1733921867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k0BdiPoCW2sPd1Y1VSCMikmuF5uV1Ceplm251HQmWDI=; b=X0CEa57X2xpecqbGTsiFlb6KGu44LQyFrwGL8gmop2j7nF8IZrN4U5LltqXUvFIINa SqmncoerpvmG3ZNSfzdPNISvPDmYLT9whcuYzQv3VcOT+v83v/gj6t2rVNmD7XwEjGW3 h0uwl79VO/GzPVW2/JaRo/3Ae2fePAylqdTutHHOykQSk6Nn5PCyMwuteLHEwYeJYrPa XNm9OQVV8v/JXwX9HSmtOWisxkKMhQBbxotBu8lk/DAd1F8rXZiubxFadxMMgCy28TA2 g7I3iXl5MgQtUbjbIRRSd3OVjwTepQ/+D0IFsw0dfxa2qcBPwbZgQihQeATPI9ThZbdV VfKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317067; x=1733921867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k0BdiPoCW2sPd1Y1VSCMikmuF5uV1Ceplm251HQmWDI=; b=Bu9uMXAhX87uPW2JmyXBnfPqnbKSCHMsVFWR3HtX3Swpb7jp9U0gv6ceLggfebC0E1 dExcuvzZB0RaU8bjQuLtEqKywKuyO3hnkto7ijI7bSR4lYkxHRmElmUJJ9ZcLBmCZwiI RGBAtM2gkzOopD0WYNd735l37ILf/QfEeFBS+/Yw1KMISWZ7St7LkBsYKaX/DQpZN+95 kw/lJY/gDqJBu+P9Ve9p9SP+GPKsGo1cMtdR4IfbYCADKLHPnbB9AgmdXPUygSp6EHZg JMLaqfnDY5QivZxzlCbGb/HO6q1T+yQJrGroF2hpEDbn5jzKyleSSjfzYvOA5JuF/7b2 Lapg== X-Forwarded-Encrypted: i=1; AJvYcCVmvkxvQHrIJRcwm6aswXG5VaA823/wCD4i3LEvA6bTfTBC1EiT0eTW9gGhkZ91LtlmrQ4QLotrMg+u@nongnu.org X-Gm-Message-State: AOJu0Yx28wLuZnjtK3WwA4vkFssTD97gsRpCxfeBl0A+qogbaAhqlqRh dZYkdwzeABpxxX40ThN+8O9k2PqnWkPDxXNhvpozI4V4ZQnDJpr27FhHw0IgkHc= X-Gm-Gg: ASbGnctquzsPulibpQbuvp03VrB0sbGnYqPJlQ5qTZ4g+1iRr53ml/ICZXe/A33lLpE 7y/y9iADWHrtOXw+/g6uY2qjcokNlt4cOnPbUaC1YNx2QuQauYVijhaRMyfsiheKp6llXzCCTBx W2TPVFbdVZLTwEH0b7mQrLPMK2iHqZSztxojPGhaJesH9M5FqlHCO8mP8ioZ7PS9nSMAyWCqDLT NVlM8zE22FP4YDeh99w95vEkbXHE1ASca5DbFWmpORq6x+MiW8LgxGHZPZY0q42Qr2NiaB3y6Ea Hzm9sw== X-Google-Smtp-Source: AGHT+IGiLay281z8PTNaBbazh+tyFb0W1NTtFnXmNW2Yil1btTT5tmrmXaW11Jss3r5JIZxo08lBDw== X-Received: by 2002:a05:6000:156b:b0:385:faf5:ebb8 with SMTP id ffacd0b85a97d-385fd97725emr5363344f8f.7.1733317067402; Wed, 04 Dec 2024 04:57:47 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 5/7] target/riscv: Add CTR sctrclr instruction. Date: Wed, 4 Dec 2024 17:56:43 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-5-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317105416116600 CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 +++++++ target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_privileged.c.inc | 11 ++++++++++ target/riscv/op_helper.c | 29 ++++++++++++++++++++++= ++++ 6 files changed, 50 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f39ca48d37332c4e5907ca87040de420f78df2e4..85ca2bfe435d0c9d245f2690fe3= bde3e076d3b2f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -613,6 +613,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv, bool virt_en); =20 void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, enum CTRType type, target_ulong prev_priv, bool prev_virt); +void riscv_ctr_clear(CPURISCVState *env); =20 void riscv_translate_init(void); G_NORETURN void riscv_raise_exception(CPURISCVState *env, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dbdad4e29d7de0713f7530c46e9fab03d3c459a4..b1130180710b0e01e8ebe33f097= 4edd8d5abe56d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -783,6 +783,13 @@ static void riscv_ctr_freeze(CPURISCVState *env, uint6= 4_t freeze_mask, } } =20 +void riscv_ctr_clear(CPURISCVState *env) +{ + memset(env->ctr_src, 0x0, sizeof(env->ctr_src)); + memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst)); + memset(env->ctr_data, 0x0, sizeof(env->ctr_data)); +} + static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) { switch (priv) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 065d82d3997b1df46a0ed1b96d33bee13c049fad..79899b9cebd6a6731370097e56c= ea3f5e3ee6a5e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a2b4c0ddd47ad9464b4b180fb19e6a3b64dbe4e5..8188113bcc90482733f67622785= 8829bac5c5462 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -114,6 +114,7 @@ # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 +sctrclr 000100000100 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index a5c2410cfa0779b1a928e7b89bd2ee5bb24216e4..1d7a17373e06a9f3226c1c14a54= beb1a56e17b83 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -69,6 +69,17 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *= a) return true; } =20 +static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { + gen_helper_ctr_clear(tcg_env); + return true; + } +#endif + return false; +} + static bool trans_uret(DisasContext *ctx, arg_uret *a) { return false; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b55b7f3ac3d209d39b16075e79c2342b89bdf805..d22609347ee63be183ab253e7a0= 158a19ff0bf52 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -389,6 +389,35 @@ void helper_ctr_add_entry(CPURISCVState *env, target_u= long src, env->priv, env->virt_enabled); } =20 +void helper_ctr_clear(CPURISCVState *env) +{ + /* + * It's safe to call smstateen_acc_ok() for umode access regardless of= the + * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the= bit + * is zero, smstateen_acc_ok() will return the correct exception code = and + * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that + * scenario the U-mode check below will handle that case. + */ + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_CTR); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + if (env->priv =3D=3D PRV_U) { + /* + * One corner case is when sctrclr is executed from VU-mode and + * mstateen.CTR =3D 0, in which case we are supposed to raise + * RISCV_EXCP_ILLEGAL_INST. This case is already handled in + * smstateen_acc_ok(). + */ + uint32_t excep =3D env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION= _FAULT : + RISCV_EXCP_ILLEGAL_INST; + riscv_raise_exception(env, excep, GETPC()); + } + + riscv_ctr_clear(env); +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317178; cv=none; d=zohomail.com; s=zohoarc; b=hvczidlHxVD2R9bL+to35a0yY9Fy8nUAq3/czRaKjCPxgkUUJxd6gD/OUv875oHB767BvXDsnFc8SE9q4T6m47jgujmznx3gDclIpcv0fdAztIijUqGmwZuayJFdsznUnJofODZ3ndVoZ+tvME3Iu+qDaPD/3NoZCJcMdCWU304= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317178; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mRwquVuCbBdC2gMEt9pTfxsQTxkyyzI8HC99Y7f0E5E=; b=f+TADteDVHtxsToJBpRfsn/q/O2ah0CKKcoG4RpQ1bDC7ZG4v1oSB31Vq7bjUA0fRxjCeOSr/64xj2IzgvI/GGtGp4WCaO2Le9unBPdhUnaHyU+LKO6tk8zhwlFJOfv4K4wG2lGh8Ga3LeGUuon03KMUbOFy0cDKRUtMfBlyqo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17333171781686.151848674673374; Wed, 4 Dec 2024 04:59:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxH-0008Db-0G; Wed, 04 Dec 2024 07:58:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIox4-00084c-Gp for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:59 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIox0-0000B5-Ag for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:56 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-385ea29eee1so2870693f8f.3 for ; Wed, 04 Dec 2024 04:57:52 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317071; x=1733921871; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mRwquVuCbBdC2gMEt9pTfxsQTxkyyzI8HC99Y7f0E5E=; b=Hy/OTL8SAUsj40GRTmGYUN6kou0gXL6lUUUrx6JW3/AhuqxbuLDEYgtENrep+PaPr7 nr+r5iO5R+1WefytNCxeBMgqoiC69rR2DjvyaVFz6UtjxXT3OLlTiIBXrxZVuD/LX+UX cDp7WpH96lY8/EWXrXPRV8s8KPhYIWZs1x8oLd8avk5eZVsBBMqxdp8HXBr3xj20w/8F OK/IFecdx1+gBusnka0fRrWRflQ6DJSwxZj8hZ+iyVpSobERFQIMwfFF9ok6aMjdGm5L lvH5uf5IJqdMgSu2l1ne/A4EGjX+PP3epjdzZRoVkI5bMgMtAJndzWMZ/wJhHVRV+Ial Aotw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317071; x=1733921871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mRwquVuCbBdC2gMEt9pTfxsQTxkyyzI8HC99Y7f0E5E=; b=nWqErCkfcMMw9qIn1xjFNl5VlwQGzcEdEArMbFn7LBY1wM8HSUybEI1RWJTDZQSdEu Gk51CXq91BmGzJUXBGz42ijYHSvzfJ0Qp3yMHTjvl1Hwe5DIRAnAsM0dG+lO1d6VIDgi GqU4iWyEU6fxXjpMecqls7uz+gStrnjTb5R9uV1OU9GlST7aP8to/4Qmfn2ns9x7icNM vRqc0fEnXsFNJomrsWZ9VWsLcJIVokJjR9dINKzEkeqD7hDYXA+wHBNGTbZWIpx4IL+A lPQnuA5Lj5xAz7er9eLbfWTvBu31ryIrJ4xH/cMPIKGbuxK6oLxLBmZGkA40Q4IBbRFW IREw== X-Forwarded-Encrypted: i=1; AJvYcCWHvIFklm9jJMtopubdZwM2g1kOstTV8B6M0RkeOmVZdu2JN6Je9B3UbIajzeTSrpQBLoCsSeB7yQGJ@nongnu.org X-Gm-Message-State: AOJu0Yy+kcCJ+NO7M6CBaUSjCzq0OtC0xJGHISXbHY7eU69NrzwNNUGF aBhZvxm0yvsLNYae5p1q9HzrSR80f0rO8ayrEcwbXQgoqr+VZ49atmOnw93K/HI= X-Gm-Gg: ASbGncvFgYcSS6SszlRrqd3r2bSB3f28cCl+uANkjWg+udafwXJj9Q3fRZcHwZMz/M5 azgmTc32fCBKIMtT7xWrgyjXXLc4WkReUJjqOEzoyDedTG3HTnsDMZyNQI90G6kAiJqcnpXb0Di EUdAez66QhV7bfKXRwNKNa/sAuiKYz0yFZ1/X7TSpu8XhfbgtovSaRt7SBZYk2Oo/Qpv8FLb/dM OMt9vDR3jMjHVIvZBKlXHi1/cw63v9xxj3yvQw+zjNCYo7No4CFoLBCHPGFqZCLPqGIt+31XQVq xpNv+w== X-Google-Smtp-Source: AGHT+IHA1xY60qXbvemAL7B9DAzydnTxEROtAIWBZfCHxpookzVuBilbA3rVqr/68l04uyHFpnaWzQ== X-Received: by 2002:a05:6000:2a8:b0:385:fd31:ca34 with SMTP id ffacd0b85a97d-385fd54df23mr5406266f8f.54.1733317071103; Wed, 04 Dec 2024 04:57:51 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 6/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. Date: Wed, 4 Dec 2024 17:56:44 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-6-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317179326116600 CTR entries are accessed using ctrsource, ctrtarget and ctrdata registers using smcsrind/sscsrind extension. This commits extends the csrind extension to support CTR registers. ctrsource is accessible through xireg CSR, ctrtarget is accessible through xireg1 and ctrdata is accessible through xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=3Dtrue and ssctr=3Dtrue now. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.c | 26 +++++++- target/riscv/csr.c | 150 +++++++++++++++++++++++++++++++++++++++++= +++- target/riscv/tcg/tcg-cpu.c | 11 ++++ 3 files changed, 185 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2a4f285a974ffc62e7f3e938691dbffe376a7e46..751029e924d4690aaa5de65456f= d5a5ec25b916a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -199,6 +199,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), + ISA_EXT_DATA_ENTRY(smctr, PRIV_VERSION_1_12_0, ext_smctr), + ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), @@ -1481,6 +1483,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), + MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false), + MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), @@ -2656,6 +2660,26 @@ static RISCVCPUImpliedExtsRule SSCFG_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule SMCTR_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_smctr), + .implied_misa_exts =3D RVS, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_sscsrind), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule SSCTR_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_ssctr), + .implied_misa_exts =3D RVS, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_sscsrind), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL @@ -2674,7 +2698,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, - NULL + &SMCTR_IMPLIED, &SSCTR_IMPLIED, NULL }; =20 static Property riscv_cpu_properties[] =3D { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7e03065d3dcd8713e2cadae3017ed355c9f9bf10..d80684a708891e062393deebe88= 0650fb4df44ab 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2401,6 +2401,13 @@ static bool xiselect_cd_range(target_ulong isel) return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST); } =20 +static bool xiselect_ctr_range(int csrno, target_ulong isel) +{ + /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */ + return CTR_ENTRIES_FIRST <=3D isel && isel <=3D CTR_ENTRIES_LAST && + csrno < CSR_MIREG; +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -2446,6 +2453,124 @@ static int rmw_iprio(target_ulong xlen, return 0; } =20 +static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + /* + * CTR arrays are treated as circular buffers and TOS always points to= next + * empty slot, keeping TOS - 1 always pointing to latest entry. Given = entry + * 0 is always the latest one, traversal is a bit different here. See = the + * below example. + * + * Depth =3D 16. + * + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] = [F] + * TOS H + * entry 6 5 4 3 2 1 0 F E D C B A 9 8 = 7 + */ + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MAS= K); + uint64_t idx; + + /* Entry greater than depth-1 is read-only zero */ + if (entry >=3D depth) { + if (val) { + *val =3D 0; + } + return 0; + } + + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); + idx =3D (idx - entry - 1) & (depth - 1); + + if (val) { + *val =3D env->ctr_src[idx]; + } + + env->ctr_src[idx] =3D (env->ctr_src[idx] & ~wr_mask) | (new_val & wr_m= ask); + + return 0; +} + +static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + /* + * CTR arrays are treated as circular buffers and TOS always points to= next + * empty slot, keeping TOS - 1 always pointing to latest entry. Given = entry + * 0 is always the latest one, traversal is a bit different here. See = the + * below example. + * + * Depth =3D 16. + * + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] = [F] + * head H + * entry 6 5 4 3 2 1 0 F E D C B A 9 8 = 7 + */ + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MAS= K); + uint64_t idx; + + /* Entry greater than depth-1 is read-only zero */ + if (entry >=3D depth) { + if (val) { + *val =3D 0; + } + return 0; + } + + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); + idx =3D (idx - entry - 1) & (depth - 1); + + if (val) { + *val =3D env->ctr_dst[idx]; + } + + env->ctr_dst[idx] =3D (env->ctr_dst[idx] & ~wr_mask) | (new_val & wr_m= ask); + + return 0; +} + +static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + /* + * CTR arrays are treated as circular buffers and TOS always points to= next + * empty slot, keeping TOS - 1 always pointing to latest entry. Given = entry + * 0 is always the latest one, traversal is a bit different here. See = the + * below example. + * + * Depth =3D 16. + * + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] = [F] + * head H + * entry 6 5 4 3 2 1 0 F E D C B A 9 8 = 7 + */ + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; + const uint64_t mask =3D wr_mask & CTRDATA_MASK; + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MAS= K); + uint64_t idx; + + /* Entry greater than depth-1 is read-only zero */ + if (entry >=3D depth) { + if (val) { + *val =3D 0; + } + return 0; + } + + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); + idx =3D (idx - entry - 1) & (depth - 1); + + if (val) { + *val =3D env->ctr_data[idx]; + } + + env->ctr_data[idx] =3D (env->ctr_data[idx] & ~mask) | (new_val & mask); + + return 0; +} + static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) @@ -2596,6 +2721,27 @@ done: return ret; } =20 +static int rmw_xireg_ctr(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) { + return -EINVAL; + } + + if (csrno =3D=3D CSR_SIREG || csrno =3D=3D CSR_VSIREG) { + return rmw_ctrsource(env, isel, val, new_val, wr_mask); + } else if (csrno =3D=3D CSR_SIREG2 || csrno =3D=3D CSR_VSIREG2) { + return rmw_ctrtarget(env, isel, val, new_val, wr_mask); + } else if (csrno =3D=3D CSR_SIREG3 || csrno =3D=3D CSR_VSIREG3) { + return rmw_ctrdata(env, isel, val, new_val, wr_mask); + } else if (val) { + *val =3D 0; + } + + return 0; +} + /* * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 * @@ -2607,11 +2753,13 @@ static int rmw_xireg_csrind(CPURISCVState *env, int= csrno, target_ulong isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - int ret =3D -EINVAL; bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false; + int ret =3D -EINVAL; =20 if (xiselect_cd_range(isel)) { ret =3D rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask); + } else if (xiselect_ctr_range(csrno, isel)) { + ret =3D rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask); } else { /* * As per the specification, access to unimplented region is undef= ined diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2b57aa4d1704b176f314dbe0b120cfcc943bf4f8..575b5692c7f68a5f6d37edbc172= 69e41f496f682 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -652,6 +652,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && + (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || + cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { + error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"= ); + return; + } + cpu->cfg.ext_smctr =3D false; + cpu->cfg.ext_ssctr =3D false; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. --=20 2.34.1 From nobody Tue Dec 23 10:23:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1733317180; cv=none; d=zohomail.com; s=zohoarc; b=i6xZXD7z51sNmof6X1q1dOfd5qZQNagU8gAZEsLpWlAum279xLv3xIj8orjMUSNngRw7ffuErox9R6kOxbuvulg7+RrBWw5Fqvl+cIG17gQGSuiKIGPorWcL+m83O5E4c+91uyh90MxejTKfdPDhrVmCMHCjDdaNH2Al6PszLGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733317180; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AdfctVdNv45/VmWP+SA5e4bfBEoBz0UqYA7wpbj9RiY=; b=EX2e8kXm8q7EvNUZMr2+qX7pr9otH4LPf7IXiMAnaYN5Z81P3QmD5X+PbnbFTQmbN5v4HvJQCfsQpkQpwAxcN9p5xKxN1WCyzWtqD5H+V+jS0o2VvWT5bHtnF7kdFrvI1D4IXejcHxFc8TocA4diHQIzidKJqsYjkyoLxMYloiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733317180349264.7742474425298; Wed, 4 Dec 2024 04:59:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIoxE-0008BB-HM; Wed, 04 Dec 2024 07:58:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIox5-00084u-Rh for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:58:03 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIox4-0000By-3F for qemu-devel@nongnu.org; Wed, 04 Dec 2024 07:57:59 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385e1721716so2648889f8f.3 for ; Wed, 04 Dec 2024 04:57:56 -0800 (PST) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com ([137.59.223.84]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385deeb6acdsm15826428f8f.81.2024.12.04.04.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 04:57:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1733317074; x=1733921874; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AdfctVdNv45/VmWP+SA5e4bfBEoBz0UqYA7wpbj9RiY=; b=bwMA+H/iMSonJS3+RDyPvkbUdiEo/7guL+v+Q68zahU5CdSZPSScTeyLf/fHgCF1rc T+djVy6S3KyuDqONrC7f7p+enNVOzL6iqlHR8SuWg+KURw/jJcwBVwLIyv2OsD2z3IUG 5AU5rZ56dBh4y6CYQywc5PVxFIBK1I/cyn1LsE+yChykixF5+NbVQ21qArUxIYas1yg/ bhSxFdeiV6eE9UiU2fm9KjjTrsrWSsRr1cBkyNnXYQHqwOJZ4jk+tx5dvdwXagZL1T5V wa9Q0lKsqc5Hpu0gIQ0SF13g/6Yx0R778nJO9m7qKv2eIvq6+pN2RmlGTimxe/8bqtgD dKmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733317075; x=1733921875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AdfctVdNv45/VmWP+SA5e4bfBEoBz0UqYA7wpbj9RiY=; b=OeZxmgsA6/CDPmHM91zEx+phdQCNSZMr9eXHK7lWUe1BJzSYFLXK5YMZKHM/K137kS 77EfbyurOKig3YDRsjyAoYGByxfGy/TuOBKXr7aYCz8KOAYN/kelQNVJvwy6x+ilU56q nwpq9/80zwgsXfv+5jKjmNfdQUx4M/92YbRehIGU7pftZRefkiHwgv8zGDAwCDU22gbM M0AbbMIDIbJTA6P6AFWelIqLEloaqS6/B0EhLNKj8PfZJcfYTBzZKrPjPL+qTbQVvsJu H3+GYp0pE2prC/uvzCgu2IyWEmHpCGXmUqWjML1t9LF6qbU+VZ+ZX4irHQ0uQT16xGYv Y4vw== X-Forwarded-Encrypted: i=1; AJvYcCVKzJba/B9ujVgl2HaxZo52rmp0vaAR3TR1bLTegGNlgUPG6fCaBbPbBNI1yfcf33IigqgSSEC9oQBh@nongnu.org X-Gm-Message-State: AOJu0Yz8kTGVtX8WaER78vFUA5QxvzCdxLXtTf6b3wO+urHvAhVdpI0M qOo7/+TERXxLKyYXI7HVrwNvBsnb7BIib1Gm1+95wYwc4gRN0lJfKtEf3jHRZGM= X-Gm-Gg: ASbGnctesqxdnKYweT6vTrl2kbODiiGZXiLPcrWPeDFF6EUcgSlXOxxYDkcSXwK0OJ2 KjB+nrq0KVzmfKGysdKopU2Mj78oIikypTcrXwTMJ7htBH1iVIFWZAusxFCMiEnk9IVIPtBEjNw ZzDOf+xfWNTCSovWFZodp/E0BjqWa/wB5zfb68WDxWUOERETAUL3FWhfY0IppvkpdUA18cMEkM2 DpSXlWw1BWay16ffCdBbhm/0VMaQyfbMwN0ECriGncAekoD3AoamMqkvofE5bwESgmhc0c224RY 3kvDqQ== X-Google-Smtp-Source: AGHT+IFsnyml7eLyL8nD58SX/Ykhd+WFATkHK4nrvyDmdvnvZFFQQgf2F3F1C2ODw+bDkjHLgO4+4g== X-Received: by 2002:a05:6000:4601:b0:385:fb40:e57b with SMTP id ffacd0b85a97d-385fd3cd413mr5382365f8f.15.1733317074609; Wed, 04 Dec 2024 04:57:54 -0800 (PST) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Subject: [PATCH v4 7/7] target/riscv: machine: Add Control Transfer Record state description Date: Wed, 4 Dec 2024 17:56:45 +0500 Message-Id: <20241204-b4-ctr_upstream_v3-v4-7-d3ce6bef9432@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> References: <20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1733317180980116600 Add a subsection to machine.c to migrate CTR CSR state Signed-off-by: Rajnesh Kanwal --- target/riscv/machine.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index e1bdc31c7c53a8a4f539113d501c8e46f7a914e9..b67e660ef03b6053fa00d5a79e2= ab20ecf3331b8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -311,6 +311,30 @@ static const VMStateDescription vmstate_envcfg =3D { } }; =20 +static bool ctr_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr; +} + +static const VMStateDescription vmstate_ctr =3D { + .name =3D "cpu/ctr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ctr_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(env.mctrctl, RISCVCPU), + VMSTATE_UINT32(env.sctrdepth, RISCVCPU), + VMSTATE_UINT32(env.sctrstatus, RISCVCPU), + VMSTATE_UINT64(env.vsctrctl, RISCVCPU), + VMSTATE_UINT64_ARRAY(env.ctr_src, RISCVCPU, 16 << SCTRDEPTH_MAX), + VMSTATE_UINT64_ARRAY(env.ctr_dst, RISCVCPU, 16 << SCTRDEPTH_MAX), + VMSTATE_UINT64_ARRAY(env.ctr_data, RISCVCPU, 16 << SCTRDEPTH_MAX), + VMSTATE_END_OF_LIST() + } +}; + static bool pmu_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -461,6 +485,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_jvt, &vmstate_elp, &vmstate_ssp, + &vmstate_ctr, NULL } }; --=20 2.34.1