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Tue, 03 Dec 2024 05:36:21 -0800 (PST) From: Tomita Moeko To: qemu-devel@nongnu.org Cc: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Tomita Moeko Subject: [PATCH v2 6/9] vfio/igd: add macro for declaring mirrored registers Date: Tue, 3 Dec 2024 21:35:45 +0800 Message-ID: <20241203133548.38252-7-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241203133548.38252-1-tomitamoeko@gmail.com> References: <20241203133548.38252-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733233117634116600 Content-Type: text/plain; charset="utf-8" igd devices have multipe registers mirroring mmio address and pci config space, more than a single BDSM register. To support this, the read/write functions are made common and a macro is defined to simplify the declaration of MemoryRegionOps. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 60 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index fea9be0b2d..522845c509 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -418,16 +418,9 @@ static const MemoryRegionOps vfio_igd_index_quirk =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -#define IGD_BDSM_MMIO_OFFSET 0x1080C0 - -static uint64_t vfio_igd_quirk_bdsm_read(void *opaque, - hwaddr addr, unsigned size) +static uint64_t vfio_igd_pci_config_read(VFIOPCIDevice *vdev, uint64_t off= set, + unsigned size) { - VFIOPCIDevice *vdev =3D opaque; - uint64_t offset; - - offset =3D IGD_BDSM_GEN11 + addr; - switch (size) { case 1: return pci_get_byte(vdev->pdev.config + offset); @@ -438,21 +431,17 @@ static uint64_t vfio_igd_quirk_bdsm_read(void *opaque, case 8: return pci_get_quad(vdev->pdev.config + offset); default: - hw_error("igd: unsupported read size, %u bytes", size); + hw_error("igd: unsupported pci config read at %lx, size %u", + offset, size); break; } =20 return 0; } =20 -static void vfio_igd_quirk_bdsm_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) +static void vfio_igd_pci_config_write(VFIOPCIDevice *vdev, uint64_t offset, + uint64_t data, unsigned size) { - VFIOPCIDevice *vdev =3D opaque; - uint64_t offset; - - offset =3D IGD_BDSM_GEN11 + addr; - switch (size) { case 1: pci_set_byte(vdev->pdev.config + offset, data); @@ -467,17 +456,37 @@ static void vfio_igd_quirk_bdsm_write(void *opaque, h= waddr addr, pci_set_quad(vdev->pdev.config + offset, data); break; default: - hw_error("igd: unsupported read size, %u bytes", size); + hw_error("igd: unsupported pci config write at %lx, size %u", + offset, size); break; } } =20 -static const MemoryRegionOps vfio_igd_bdsm_quirk =3D { - .read =3D vfio_igd_quirk_bdsm_read, - .write =3D vfio_igd_quirk_bdsm_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, +#define VFIO_IGD_QUIRK_MIRROR_REG(reg, name) \ +static uint64_t vfio_igd_quirk_read_##name(void *opaque, \ + hwaddr addr, unsigned size) \ +{ \ + VFIOPCIDevice *vdev =3D opaque; \ + return vfio_igd_pci_config_read(vdev, reg + addr, size); \ +} \ + \ +static void vfio_igd_quirk_write_##name(void *opaque, hwaddr addr, \ + uint64_t data, unsigned size) \ +{ \ + VFIOPCIDevice *vdev =3D opaque; \ + vfio_igd_pci_config_write(vdev, reg + addr, data, size); \ +} \ + \ +static const MemoryRegionOps vfio_igd_quirk_mirror_##name =3D { \ + .read =3D vfio_igd_quirk_read_##name, \ + .write =3D vfio_igd_quirk_write_##name, \ + .endianness =3D DEVICE_LITTLE_ENDIAN, \ }; =20 +VFIO_IGD_QUIRK_MIRROR_REG(IGD_BDSM_GEN11, bdsm) + +#define IGD_BDSM_MMIO_OFFSET 0x1080C0 + void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) { VFIOQuirk *quirk; @@ -507,10 +516,11 @@ void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, i= nt nr) quirk =3D vfio_quirk_alloc(1); quirk->data =3D vdev; =20 - memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_bdsm_qui= rk, - vdev, "vfio-igd-bdsm-quirk", 8); + memory_region_init_io(&quirk->mem[1], OBJECT(vdev), + &vfio_igd_quirk_mirror_bdsm, vdev, + "vfio-igd-bdsm-quirk", 8); memory_region_add_subregion_overlap(vdev->bars[0].region.mem, - IGD_BDSM_MMIO_OFFSET, &quirk->mem[= 0], + IGD_BDSM_MMIO_OFFSET, &quirk->mem[= 1], 1); =20 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); --=20 2.45.2