From nobody Fri Dec 19 14:28:33 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1733224011; cv=none; d=zohomail.com; s=zohoarc; b=ZYxvUXUhWnwV63WF2HcGw9DnOg2Mcv00BQNql8lbYrNcfDpq3hSkY5xA4V+AZTTzIPQOHUeeQgn24RuM5RS1AtO/T9CIEkeum8aYZp5KeuxL/volsm473p9ipAh6rkrnSae/fC2squ3b2dA4XaL4hjdfZgsUPp5yFdkwUN0IcVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733224011; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gHdmag75iaWZnkfBuSd+viy7kreS7aX/TkGtbBNIJSA=; b=eNJLdpyDr++VomWIRlX3h/goL+rO5gdVoMaEoLlwKcy2aWQRmGRf5qHOmpJCFtgLA/x936RUKMYzopRPybNqD09DfBFWtRu8ezrbyiwntmwkjfD2CvzEuIgwxhExyMutFksWvyc7gEKjgQ0hOhmamdfuOXPWW49up9yjWzKRKT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733224011034582.497224587886; Tue, 3 Dec 2024 03:06:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIQj6-0001hA-B6; Tue, 03 Dec 2024 06:05:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIQj2-0001gd-Ub; Tue, 03 Dec 2024 06:05:53 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIQj0-0005yT-U2; Tue, 03 Dec 2024 06:05:52 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385dece873cso2066906f8f.0; Tue, 03 Dec 2024 03:05:50 -0800 (PST) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434b0d9bc11sm190052535e9.4.2024.12.03.03.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 03:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733223948; x=1733828748; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gHdmag75iaWZnkfBuSd+viy7kreS7aX/TkGtbBNIJSA=; b=HoIgsHmQOVWYl6LpGticfhuaau7En4dAA8blfPCUb2RYLiwMCS7hhfjIxgubhyfnav fNamVFry/YXcApr5EM7K0uamjx0mrHKuKqU7J9vRrYBbBd+uDtXW/2Q4EwL+VN/dRQEc ANRuneWJ7TcDJmYGmvWQy7Qs1497H2d3kfEdjYBydFV0q9+118RtS2FF/T0607wEGV9a 7MTo1leSw6vo7jYQCjBhDZqCUQzhiH5tflX5PnZpIWcZNptL1uffh4kVAzoq5W0e55iJ 2XdtI9QlIjFKt+frBjTzZG+94d3X9/NZZ0UEb4pjIKhpf45au3WFlHdQRb3rwkLINvq9 DWmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733223948; x=1733828748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gHdmag75iaWZnkfBuSd+viy7kreS7aX/TkGtbBNIJSA=; b=SQOP/t3SmcWpUt1oRjFZh+fDmXqhx2eqLQKL2qWLG4RUf4Js9dY8BgehZmFb5rMXSA 9P97XxQTqkZQN0OMBu7pS3BlICmYjfOgdvgkWzZVEBeTXQzbw/zCVzhusV2Hov9RY/I5 urqF0ifL48ap+Ocsn/FFDIgpt3tSXJhUC0hNHruJgWFV7tPGXC77uea5H6bZAgH85QD/ r1hQsmqYy99d7BQeSjC6ow7wTpYZrjkilFgp8idJcMa2G5hEqzXWleIkJlHbojuHCJhK T+/1ZPI9gOMMlkzfuL/jJHnIN3hjs5qZhvF9ccSloA7D3S1m+0kyOkmf9y0DRW11Rzvl t1pQ== X-Forwarded-Encrypted: i=1; AJvYcCUYq1/JAiapWrMa7oRNRFx3qi4hGsbQEi5CVT6l1qT6dbcTzqO4cPctqqkI94F/6Ab2jIM8aQzr+rqjMg==@nongnu.org X-Gm-Message-State: AOJu0YwY+nxEkl+YIr9nOzHAAQ71dh3g2bfR1Yj+S9cFNHBHrTEW+6up w2ImhBFEf6Fc/9FexFaBLXRgJW2CSvvpJZsjrNX1606nu+4yiLHC2jqkEA== X-Gm-Gg: ASbGncvJmTnRUzqkI9fYfT2C9wvCvtwSEuKzs9lAt2LOJ+DIYo4i9H546XJwc/RejbE jEAW8m7AjzD3qkSbWuPbJcoU/FmzUrrfA8tKHqPpirGL6gXgbc2GT2khlFlAWyfFk8fdk9Jb5r7 p8oPccodSixLW52UBeGJEX6V0h30GsObhihVknqJS5/IQ6GDOTDdYiiXzs8p7ftyCgNeUH57Ddq l4HYMT6ToeAQVE4VKm2VJs1qiRoVbVc3SoDfZQDdjEYYZSET2ryaIXBqQNZBQT7bina0BQC0L/1 MQUI4WnBqXSukg== X-Google-Smtp-Source: AGHT+IE1Xodmw1U0bXJD7a49TyPA4XwARYukb6gaESWAhI8L2A78gL3N9Tpi4X46HcQmI+7GalKNyA== X-Received: by 2002:a05:6000:1445:b0:385:f060:b7fc with SMTP id ffacd0b85a97d-385fd3e6cc1mr1295102f8f.25.1733223948238; Tue, 03 Dec 2024 03:05:48 -0800 (PST) From: Stafford Horne To: QEMU Development Cc: Ahmad Fatoum , qemu-stable@nongnu.org, Stafford Horne , Peter Maydell , Jia Liu Subject: [PATCH v3 1/2] hw/openrisc/openrisc_sim: keep serial@90000000 as default Date: Tue, 3 Dec 2024 11:05:35 +0000 Message-ID: <20241203110536.402131-2-shorne@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241203110536.402131-1-shorne@gmail.com> References: <20241203110536.402131-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shorne@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733224014692116600 Content-Type: text/plain; charset="utf-8" From: Ahmad Fatoum We used to only have a single UART on the platform and it was located at address 0x90000000. When the number of UARTs was increased to 4, the first UART remained at it's location, but instead of being the first one to be registered, it became the last. This caused QEMU to pick 0x90000300 as the default UART, which broke software that hardcoded the address of 0x90000000 and expected it's output to be visible when the user configured only a single console. This caused regressions[1] in the barebox test suite when updating to a newer QEMU. As there seems to be no good reason to register the UARTs in inverse order, let's register them by ascending address, so existing software can remain oblivious to the additional UART ports. Changing the order of uart registration alone breaks Linux which was choosing the UART at 0x90000300 as the default for ttyS0. To fix Linux we fix three things in the device tree: 1. Define stdout-path only one time for the first registered UART instead of incorrectly defining for each UART. 2. Change the UART alias name from 'uart0' to 'serial0' as almost all Linux tty drivers look for an alias starting with "serial". 3. Add the UART nodes so they appear in the final DTB in the order starting with the lowest address and working upwards. In summary these changes mean that the QEMU default UART (serial_hd(0)) is now setup where: * serial_hd(0) is the lowest-address UART * serial_hd(0) is listed first in the DTB * serial_hd(0) is the /chosen/stdout-path one * the /aliases/serial0 alias points at serial_hd(0) [1]: https://lore.barebox.org/barebox/707e7c50-aad1-4459-8796-0cc54bab32e2@= pengutronix.de/T/#m5da26e8a799033301489a938b5d5667b81cef6ad Fixes: 777784bda468 ("hw/openrisc: support 4 serial ports in or1ksim") Cc: qemu-stable@nongnu.org Signed-off-by: Ahmad Fatoum [stafford: Change to serial0 alias and update change message, reverse uart registration order] Signed-off-by: Stafford Horne Reviewed-by: Peter Maydell --- Since v2: - Fruther updates of commit message indicating the changes to the DTB registation order. Since v1: - Fix commit message and reverse registration order as pointed out by Pete= r. hw/openrisc/openrisc_sim.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 9fb63515ef..42f002985b 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -250,7 +250,7 @@ static void openrisc_sim_serial_init(Or1ksimState *stat= e, hwaddr base, void *fdt =3D state->fdt; char *nodename; qemu_irq serial_irq; - char alias[sizeof("uart0")]; + char alias[sizeof("serial0")]; int i; =20 if (num_cpus > 1) { @@ -265,7 +265,7 @@ static void openrisc_sim_serial_init(Or1ksimState *stat= e, hwaddr base, serial_irq =3D get_cpu_irq(cpus, 0, irq_pin); } serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, - serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), + serial_hd(uart_idx), DEVICE_NATIVE_ENDIAN); =20 /* Add device tree node for serial. */ @@ -277,10 +277,13 @@ static void openrisc_sim_serial_init(Or1ksimState *st= ate, hwaddr base, qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MH= Z); qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); =20 - /* The /chosen node is created during fdt creation. */ - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); - snprintf(alias, sizeof(alias), "uart%d", uart_idx); + if (uart_idx =3D=3D 0) { + /* The /chosen node is created during fdt creation. */ + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); + } + snprintf(alias, sizeof(alias), "serial%d", uart_idx); qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename); + g_free(nodename); } =20 @@ -326,11 +329,22 @@ static void openrisc_sim_init(MachineState *machine) smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); } =20 - for (n =3D 0; n < OR1KSIM_UART_COUNT; ++n) + /* + * We create the UART nodes starting with the highest address and + * working downwards, because in QEMU the DTB nodes end up in the + * DTB in reverse order of creation. Correctly-written guest software + * will not care about the node order (it will look at stdout-path + * or the alias nodes), but for the benefit of guest software which + * just looks for the first UART node in the DTB, make sure the + * lowest-address UART (which is QEMU's first serial port) appears + * first in the DTB. + */ + for (n =3D OR1KSIM_UART_COUNT - 1; n >=3D 0; n--) { openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base + or1ksim_memmap[OR1KSIM_UART].size = * n, or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus, OR1KSIM_UART_IRQ, n); + } =20 load_addr =3D openrisc_load_kernel(ram_size, kernel_filename, &boot_info.bootstrap_pc); --=20 2.47.0 From nobody Fri Dec 19 14:28:33 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1733224011; cv=none; d=zohomail.com; s=zohoarc; b=mprIZw3XNRnrQMzPbLXfoWphaTSohigLwQQEwm+3oNwK0iVCOu11JeNtL6BNKfYusGPeJwCabuKQckTdhOjnOE6dPlCeKQAkyu5S4LYL21vsQ+WZbmTetZGE0guzLDpr93w/j+U/arHIi1Y+jEqbj+MlVDHHWHrws0YZ/f8bu0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1733224011; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xo3zekWsRMbBmwQmVCNu408X16nyiPiArPS5MagL8II=; b=a46rOwalOb5NIqKRn2fzFhXXjKXMWFtXu8keo2AGm6o9UGVv5LjNKKV4O8YQtbyHuZSMmfQuybaIA/VUb5GzGUuSB47O/LXdJ/jZXiZIME4fNLXYzJixJkvitgcZVQE8Mpv0sDImXTeQ+Wjf27OnhFe5Jw66n350SO7xX/B7DsM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1733224011034210.41978089126144; Tue, 3 Dec 2024 03:06:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tIQj9-0001hn-Sz; Tue, 03 Dec 2024 06:05:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tIQj5-0001hB-8L for qemu-devel@nongnu.org; Tue, 03 Dec 2024 06:05:56 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tIQj2-0005yo-I8 for qemu-devel@nongnu.org; Tue, 03 Dec 2024 06:05:55 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434a766b475so49454035e9.1 for ; Tue, 03 Dec 2024 03:05:52 -0800 (PST) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa76a981sm215097825e9.16.2024.12.03.03.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 03:05:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733223950; x=1733828750; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xo3zekWsRMbBmwQmVCNu408X16nyiPiArPS5MagL8II=; b=e1XBW1SXZMOYrXcXFHWlY1pbNXVRTlL01uPJDkQbJ4pUwLpOCUvd1fmefT9dWSR6rX YXDDY/mF5ijV2XNhtga1zFiSFxBptQJeSFDDUvl1Si1q8+7t2zwJ1R2B8G0X25dZVkF/ MDlZiouvwfo/jQkUj2gz9v3DEoaHif/hmET2WINHq2yqDqdHILiDm2DMd88WiVxSvntl y+IZUUFRuyXW5f7L2WN0WxL44v6yMRZjYwFOp5iQAfjFWCMSzISmLyCSqREV0WEQiJ/p 0H5uncGZXcdjj8ZahKM7OpnOrVS9ffPrbPmN24gAx7ESdYJ4QlLLbJh5aywn7F/9UpxR ZDJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733223950; x=1733828750; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xo3zekWsRMbBmwQmVCNu408X16nyiPiArPS5MagL8II=; b=aBOQWCXTzGth/4AEfEoCwNjYdG5sYQfCQAa2vtZ04DFJEoxfjixwg/ZKd6puzH8Skr vqSxYiRG5J2tRE0r1XVGQDhk2hgyz4vII+eqHsojDU5LTsGyFEr234j+Oi/vuwAEqMqB JGM6PRpj/ohwG1zIXDSR25qRIGEb9ix2O23G7ZkyZ09mIG+c7Y79xuIKm1S2Jst1HJ0e S1YWwCnAiX0Se65Ixnqp8rsCcTmlCjFCWqBngvLCewddimjAYzAtgQ4gkXcgd+VIRhoO aticzvakyTy7QrjRuEnI9iplHfQ3w7820ea774hX8o2UaaY1pL2Pu5dwK6f7f8f/0Zo4 i6nQ== X-Gm-Message-State: AOJu0YzQKBIz2QoHTWFfiM67rqlswbNMKRnzBZTT0J0MI2XTOt/o3dQO ivzkNViYhS3LGBtr24RBH9bZ9IS4oIOwY8c3wdHMqfBcMMaliO0DhRtepA== X-Gm-Gg: ASbGncukEzy6eSxh9Nqf547/4eVOM7QZI47Bb0m3+juSEL7YQmxnqBiQF4SGbP8tdbq dkXa/Drb9YLVoKtVD7aPX/oxcdvy8XBi4qQMxQmdTiajtyJAu5S9aQ80SOZcZeOOw41wl4NDrb3 0JuchLS87dtYLJ1WuR41sDFRte9elcO6QAZUJjZ9BIl+ACTVr0zA1aiRmDymWNwBboBdjlDJnqc S8TGrOnEKbhNBQ37ojtm9SHcgWD6biZNi/IyXe/bMAcIYzwLcFX3RNynJ4K9DcM8Jd1ouXJ8wVo bL7q9JaRLPX6bg== X-Google-Smtp-Source: AGHT+IG890fkmtWmzAl18WQUj3eGdHgCxd6C5+7JMfRBxuBPw8yNdbgoHdWDSErnhty+RnTFocg3+A== X-Received: by 2002:a05:600c:4fc9:b0:434:a0bf:98ea with SMTP id 5b1f17b1804b1-434d09c0b88mr18054435e9.9.1733223950220; Tue, 03 Dec 2024 03:05:50 -0800 (PST) From: Stafford Horne To: QEMU Development Cc: Joel Holdsworth , Stafford Horne Subject: [PATCH v3 2/2] hw/openrisc: Fixed undercounting of TTCR in continuous mode Date: Tue, 3 Dec 2024 11:05:36 +0000 Message-ID: <20241203110536.402131-3-shorne@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241203110536.402131-1-shorne@gmail.com> References: <20241203110536.402131-1-shorne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=shorne@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1733224013445116600 Content-Type: text/plain; charset="utf-8" From: Joel Holdsworth In the existing design, TTCR is prone to undercounting when running in continuous mode. This manifests as a timer interrupt appearing to trigger a few cycles prior to the deadline set in SPR_TTMR_TP. When the timer triggers, the virtual time delta in nanoseconds between the time when the timer was set, and when it triggers is calculated. This nanoseconds value is then divided by TIMER_PERIOD (50) to compute an increment of cycles to apply to TTCR. However, this calculation rounds down the number of cycles causing the undercounting. A simplistic solution would be to instead round up the number of cycles, however this will result in the accumulation of timing error over time. This patch corrects the issue by calculating the time delta in nanoseconds between when the timer was last reset and the timer event. This approach allows the TTCR value to be rounded up, but without accumulating error over time. Signed-off-by: Joel Holdsworth [stafford: Incremented version in vmstate_or1k_timer, checkpatch fixes] Signed-off-by: Stafford Horne --- Since v2: - Nothing Since v1: - Use DIVIDE_ROUND_UP instead of open coding as pointed out by Richard - Fix off-by-1 bug in TTCR patch pointed out by Richard hw/openrisc/cputimer.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index 835986c4db..87aa353323 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -29,7 +29,8 @@ /* Tick Timer global state to allow all cores to be in sync */ typedef struct OR1KTimerState { uint32_t ttcr; - uint64_t last_clk; + uint32_t ttcr_offset; + uint64_t clk_offset; } OR1KTimerState; =20 static OR1KTimerState *or1k_timer; @@ -37,6 +38,8 @@ static OR1KTimerState *or1k_timer; void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) { or1k_timer->ttcr =3D val; + or1k_timer->ttcr_offset =3D val; + or1k_timer->clk_offset =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); } =20 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) @@ -53,9 +56,8 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu) return; } now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - or1k_timer->ttcr +=3D (uint32_t)((now - or1k_timer->last_clk) - / TIMER_PERIOD); - or1k_timer->last_clk =3D now; + or1k_timer->ttcr =3D or1k_timer->ttcr_offset + + DIV_ROUND_UP(now - or1k_timer->clk_offset, TIMER_PERIOD); } =20 /* Update the next timeout time as difference between ttmr and ttcr */ @@ -69,7 +71,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) } =20 cpu_openrisc_count_update(cpu); - now =3D or1k_timer->last_clk; + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 if ((cpu->env.ttmr & TTMR_TP) <=3D (or1k_timer->ttcr & TTMR_TP)) { wait =3D TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; @@ -110,7 +112,8 @@ static void openrisc_timer_cb(void *opaque) case TIMER_NONE: break; case TIMER_INTR: - or1k_timer->ttcr =3D 0; + /* Zero the count by applying a negative offset to the counter */ + or1k_timer->ttcr_offset -=3D (cpu->env.ttmr & TTMR_TP); break; case TIMER_SHOT: cpu_openrisc_count_stop(cpu); @@ -137,17 +140,18 @@ static void openrisc_count_reset(void *opaque) /* Reset the global timer state. */ static void openrisc_timer_reset(void *opaque) { - or1k_timer->ttcr =3D 0x00000000; - or1k_timer->last_clk =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + OpenRISCCPU *cpu =3D opaque; + cpu_openrisc_count_set(cpu, 0); } =20 static const VMStateDescription vmstate_or1k_timer =3D { .name =3D "or1k_timer", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(ttcr, OR1KTimerState), - VMSTATE_UINT64(last_clk, OR1KTimerState), + VMSTATE_UINT32(ttcr_offset, OR1KTimerState), + VMSTATE_UINT64(clk_offset, OR1KTimerState), VMSTATE_END_OF_LIST() } }; --=20 2.47.0