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Fri, 29 Nov 2024 07:43:15 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 1/3] MAINTAINERS: Cover RISC-V HTIF interface Date: Fri, 29 Nov 2024 16:43:02 +0100 Message-ID: <20241129154304.34946-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732895097675019100 The HTIF interface is RISC-V specific, add it within the MAINTAINERS section covering hw/riscv/. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- IMHO 'RISC-V TCG CPUs' should cover target/riscv/ which are the accelerator-facing implementations, and each machine or device in hw/riscv/ should have its own section. Not going to clean that in this patch. --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2b1c4abed65..046e05dd28d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,8 +324,10 @@ S: Supported F: configs/targets/riscv* F: docs/system/target-riscv.rst F: target/riscv/ +F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* +F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ --=20 2.45.2 From nobody Thu Dec 26 22:26:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1732895031; cv=none; d=zohomail.com; s=zohoarc; b=AujYJy7LZmVyq7doZPH57PkcVd9dRAIiFuIVX1nC7BYqxdrtGWSZBoP2mc5V2BMB3wSgXOo8N0dEEYceUa0GBtw31yfJga6ljgKOJ+ZvWKr7nMqBk64fvY7KJ6S+O4gfgeiIz4a8JrNHYT1AB9g4NYmS+5R4ty4Q+ZMZP9IgozY= ARC-Message-Signature: i=1; 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Fri, 29 Nov 2024 07:43:21 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation Date: Fri, 29 Nov 2024 16:43:03 +0100 Message-ID: <20241129154304.34946-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732895033177019100 Since our RISC-V system emulation is only built for little endian, the HTIF device aims to interface with little endian memory accesses, thus we can explicit htif_mm_ops:endianness being DEVICE_LITTLE_ENDIAN. In that case tswap64() is equivalent to le64_to_cpu(), as in "convert this 64-bit little-endian value into host cpu order". Replace to simplify. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- hw/char/riscv_htif.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 0345088e8b3..3f84d8d6738 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -29,7 +29,7 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" -#include "exec/tswap.h" +#include "qemu/bswap.h" #include "sysemu/dma.h" #include "sysemu/runstate.h" =20 @@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, ui= nt64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall)= ); - if (tswap64(syscall[0]) =3D=3D PK_SYS_WRITE && - tswap64(syscall[1]) =3D=3D HTIF_DEV_CONSOLE && - tswap64(syscall[3]) =3D=3D HTIF_CONSOLE_CMD_PUTC) { + if (le64_to_cpu(syscall[0]) =3D=3D PK_SYS_WRITE && + le64_to_cpu(syscall[1]) =3D=3D HTIF_DEV_CONSOLE && + le64_to_cpu(syscall[3]) =3D=3D HTIF_CONSOLE_CMD_PUTC) { uint8_t ch; - cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); + cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch,= 1); /* * XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks @@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps htif_mm_ops =3D { .read =3D htif_mm_read, .write =3D htif_mm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, --=20 2.45.2 From nobody Thu Dec 26 22:26:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1732895031; cv=none; d=zohomail.com; s=zohoarc; b=CtgjO2jkUlNibqIsXMR/Q5Awz+nNBLNv1ka56xwaO1qcHvJs2zmikt/6X9Fv9rl7xECUeDOcFY0wa6E+YETYsJfM8x9Q/w+ZYS2y67KOGETNP5dHkqDlf2iQ+H6r4LmiUdWG7OEE8ejBIyXWtDd+B76y0Vk5g0api5U9wXjV3Uc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 29 Nov 2024 07:43:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Date: Fri, 29 Nov 2024 16:43:04 +0100 Message-ID: <20241129154304.34946-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732895033151019100 Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- Notes 1/ these variables belong to HTIFState but are declared statically! static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr; 2/ I believe a 64-bit implementation would simplify the logic. 3/ This is a non-QOM device model! Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/char/riscv_htif.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 3f84d8d6738..db69b5e3ca7 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops =3D { .read =3D htif_mm_read, .write =3D htif_mm_write, .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, }; =20 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, --=20 2.45.2